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    Problem of Sequential Circuit ATPG Time-Frame Expansion

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    Sequential Circuits have memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output.

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    Problem of Sequential Circuit ATPG Time-Frame Expansion

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    Sequential Circuits have memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output.

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    sequential ckt testing - 1

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    Sequential Circuits have memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    46 views22 pages

    Problem of Sequential Circuit ATPG Time-Frame Expansion

    Uploaded by

    api-78343547
    Sequential Circuits have memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
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    of 22

    Lecture 13 Sequential Circuit ATPG

    Time-Frame Expansion

    Problem of sequential circuit ATPG Time-frame expansion

    Nine-valued logic ATPG implementation and drivability Complexity of ATPG Cycle-free and cyclic circuits Asynchronous circuits

    Summary
    VLSI Test: Bushnell-Agrawal/Lecture 13 1

    Feb. 23, 2001

    Sequential Circuits

    A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which

    Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Time-frame expansion methods Simulation-based methods

    Methods of sequential circuit ATPG


    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    Example: A Serial Adder


    1

    An Bn
    1 s-a-0 1 1

    Cn X
    Combinational logic

    X
    Cn+1 Sn X
    1

    FF
    Feb. 23, 2001 VLSI Test: Bushnell-Agrawal/Lecture 13

    Time-Frame Expansion
    An-1 Bn-1
    1 1

    Time-frame -1
    s-a-0 1

    An Bn
    1 1

    Time-frame 0
    s-a-0 1

    D D

    X X

    D D

    D
    1

    Cn-1
    X

    Cn
    1

    Cn+1
    1

    Combinational logic

    Sn-1
    X

    Combinational logic

    Sn
    D

    FF

    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    Concept of Time-Frames

    If the test sequence for a single stuck-at fault contains n vectors,


    Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic
    Vector -n+1 Vector -1 Vector 0

    Fault
    Unknown or given Init. state

    Comb. block
    Feb. 23, 2001

    Timeframe -n+1

    State variables

    Timeframe -1 PO -1

    Timeframe 0 PO 0

    Next state

    PO -n+1

    VLSI Test: Bushnell-Agrawal/Lecture 13

    Example for Logic Systems

    FF1

    s-a-1

    FF2

    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    Five-Valued Logic (Roth) 0,1, D, D, X


    A 0
    s-a-1

    A 0
    s-a-1

    D
    FF1 FF2

    D X D X
    FF1 FF2

    X X

    Time-frame -1
    Feb. 23, 2001

    B X

    Time-frame 0

    B X
    7

    VLSI Test: Bushnell-Agrawal/Lecture 13

    0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X


    A 0
    s-a-1 0/1 FF1 FF2

    Nine-Valued Logic (Muth)


    A X
    s-a-1 0/X

    X/1
    0/X FF1 FF2

    X X

    0/1

    X/1

    Time-frame -1
    Feb. 23, 2001

    B X

    Time-frame 0

    0/1
    8

    VLSI Test: Bushnell-Agrawal/Lecture 13

    Implementation of ATPG

    Select a PO for fault detection based on drivability analysis. Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. Justify the output value from PIs, considering all necessary paths and adding backward time-frames. If justification is impossible, then use drivability to select another PO and repeat justification. If the procedure fails for all reachable POs, then the fault is untestable. If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the the fault is potentially

    detectable.
    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    Drivability Example
    (11, 16) (10, 15) d(0/1) = 4 d(1/0) = s-a-1 (5, 9) d(0/1) = 9 d(1/0) = FF 8 (10, 16) d(0/1) = d(1/0) = 20 8 (6, 10) d(0/1) = 109 d(1/0) = 8

    (22, 17)
    d(0/1) = d(1/0) = 32

    (4, 4)

    (17, 11) d(0/1) = 120 d(1/0) = 27

    (CC0, CC1) = (6, 4)

    CC0 and CC1 are SCOAP combinational controllabilities d(0/1) and d(1/0) of a line are effort measures for driving a specific fault effect to that line

    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    10

    Complexity of ATPG

    Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock: Cycle-free circuit No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth. Cyclic circuit Contains feedback among flipflops: May need 9Nff time-frames, where Nff is the number of flip-flops. Asynchronous circuit Higher complexity!
    TimeFrame max-1 TimeFrame max-2

    Smax

    S3

    Time- S2 Time- S1 TimeFrame Frame Frame -2 -1 0

    S0

    max = Number of distinct vectors with 9-valued elements = 9Nff


    Feb. 23, 2001 VLSI Test: Bushnell-Agrawal/Lecture 13 11

    Cycle-Free Circuits

    Characterized by absence of cycles among flip-flops and a sequential depth, dseq. dseq is the maximum number of flip-flops on any path between PI and PO. Both good and faulty circuits are initializable. Test sequence length for a fault is bounded by dseq + 1.

    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    12

    Cycle-Free Example
    Circuit
    F2 2 F1 Level = 1 F2 2 F1 Level = 1 F3 3 dseq = 3 F3 3

    s - graph

    All faults are testable. See Example 8.6.


    Feb. 23, 2001 VLSI Test: Bushnell-Agrawal/Lecture 13 13

    Cyclic Circuit Example


    Modulo-3 counter CNT F2

    F1

    s - graph F1 F2

    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    14

    Modulo-3 Counter

    Cyclic structure Sequential depth is undefined. Circuit is not initializable. No tests can be generated for any stuck-at fault. After expanding the circuit to 9Nff = 81, or fewer, time-frames ATPG program calls any given target fault untestable. Circuit can only be functionally tested by multiple observations. Functional tests, when simulated, give no fault coverage.

    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    15

    Adding Initializing Hardware


    Initializable modulo-3 counter CNT s-a-0 s-a-1 s-a-1 s - graph F1 F2 s-a-1
    Untestable fault Potentially detectable fault

    F1

    F2

    CLR

    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    16

    Benchmark Circuits
    Circuit PI PO FF Gates Structure Seq. depth Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s1196 14 14 18 529 Cycle-free 4 1242 1239 0 3 0 99.8 100.0 3 313 10 s1238 14 14 18 508 Cycle-free 4 1355 1283 0 72 0 94.7 100.0 3 308 15 s1488 8 19 6 653 Cyclic -1486 1384 2 26 76 93.1 94.8 24 525 19941 s1494 8 19 6 647 Cyclic -1506 1379 2 30 97 91.6 93.4 28 559 19183

    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    17

    Asynchronous Circuit

    An asynchronous circuit contains unclocked memory often realized by combinational feedback. Almost impossible to build, let alone test, a large asynchronous circuit. Clock generators, signal synchronizers, flipflops are typical asynchronous circuits. Many large synchronous systems contain small portions of localized asynchronous circuitry. Sequential circuit ATPG should be able to generate tests for circuits with limited asynchronous parts, even if it does not detect faults in those parts.
    VLSI Test: Bushnell-Agrawal/Lecture 13 18

    Feb. 23, 2001

    Asynchronous Model
    CK Synchronous PIs Combinational Feedback Paths: Feedback-free Combinational Logic

    Feedback set

    PPI

    PPO

    CK System Clock, CK Fast model Clock, FMCK


    Feb. 23, 2001

    Synchronous POs Clocked Flip-flops Feedback delays


    VLSI Test: Bushnell-Agrawal/Lecture 13

    Modeling circuit is Shown in orange.


    19

    Time-Frame Expansion
    Vector k PI

    Feedback set PPI

    CK

    FMCK

    FMCK

    FMCK

    Feedback set PPO

    PO Time-frame -k+1

    Asynchronous feedback stabilization Time-frame k Time-frame -k-1

    Feb. 23, 2001

    VLSI Test: Bushnell-Agrawal/Lecture 13

    20

    Asynchronous Example
    0 0 1

    s-a-0 s-a-0 s-a-0

    s-a-0

    s-a-0

    X 1

    s-a-0 s-a-1

    X 0

    1 0 1

    Vectors 1 2 3 4

    s-a-0

    Gentest results:

    0 1 1 Outputs 1 2 3 4

    Faults: total 23, detected 15, untestable 8 (shown in red), potentially detectable none Vectors: 4 Sparc 2 CPU time: test generation 33ms, fault simulation 16ms
    Feb. 23, 2001 VLSI Test: Bushnell-Agrawal/Lecture 13 21

    Summary

    Combinational ATPG algorithms are extended:

    Cycle-free circuits: Cyclic circuits:

    Time-frame expansion unrolls time as combinational array Nine-valued logic system Justification via backward time
    Require at most dseq time-frames Always initializable May need 9Nff time-frames Circuit must be initializable Partial scan can make circuit cycle-free (Chapter 14) High complexity Low coverage and unreliable tests Simulation-based methods are more useful (Section 8.3)
    VLSI Test: Bushnell-Agrawal/Lecture 13 22

    Asynchronous circuits:

    Feb. 23, 2001

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