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    Delay Test: Mar. 23, 2001 VLSI Test: Bushnell-Agrawal/Lecture 20 1

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    Muneer Mattanur
    This document provides an overview of delay testing. It defines delay testing as verifying that a circuit produces correct outputs within specified timing limits. It discusses path delay faults, where a fault is modeled as excessive delay along a signal path. It describes techniques for generating robust and non-robust tests to detect path delay faults. It also covers other delay testing methods like variable-clock and rated-clock testing that apply input patterns with different clock speeds to activate and propagate fault effects.

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    Delay Test: Mar. 23, 2001 VLSI Test: Bushnell-Agrawal/Lecture 20 1

    Uploaded by

    Muneer Mattanur
    26 views25 pages
    This document provides an overview of delay testing. It defines delay testing as verifying that a circuit produces correct outputs within specified timing limits. It discusses path delay faults, where a fault is modeled as excessive delay along a signal path. It describes techniques for generating robust and non-robust tests to detect path delay faults. It also covers other delay testing methods like variable-clock and rated-clock testing that apply input patterns with different clock speeds to activate and propagate fault effects.

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    Delay

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    This document provides an overview of delay testing. It defines delay testing as verifying that a circuit produces correct outputs within specified timing limits. It discusses path delay faults, where a fault is modeled as excessive delay along a signal path. It describes techniques for generating robust and non-robust tests to detect path delay faults. It also covers other delay testing methods like variable-clock and rated-clock testing that apply input patterns with different clock speeds to activate and propagate fault effects.

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    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    26 views25 pages

    Delay Test: Mar. 23, 2001 VLSI Test: Bushnell-Agrawal/Lecture 20 1

    Uploaded by

    Muneer Mattanur
    This document provides an overview of delay testing. It defines delay testing as verifying that a circuit produces correct outputs within specified timing limits. It discusses path delay faults, where a fault is modeled as excessive delay along a signal path. It describes techniques for generating robust and non-robust tests to detect path delay faults. It also covers other delay testing methods like variable-clock and rated-clock testing that apply input patterns with different clock speeds to activate and propagate fault effects.

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    © All Rights Reserved
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    Download as ppt, pdf, or txt
    of 25

    Lecture 20

    Delay Test

    Delay test definition


    Circuit delays and event propagation
    Path-delay tests

    Non-robust test
    Robust test
    Five-valued logic and test generation

    Path-delay fault (PDF) and other fault models


    Test application methods

    Combinational, enhanced-scan and normal-scan


    Variable-clock and rated-clock methods

    At-speed test
    Timing design and delay test
    Summary

    Mar. 23, 2001

    VLSI Test: Bushnell-

    Delay Test Definition

    A circuit that passes delay test must


    produce correct outputs when inputs are
    applied and outputs observed with
    specified timing.
    For a combinational or synchronous
    sequential circuit, delay test verifies the
    limits of delay in combinational logic.
    Delay test problem for asynchronous
    circuits is complex and not well
    understood.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    Digital Circuit Timing


    Input
    Signal
    changes

    Synchronized
    With clock

    Outputs

    Comb.
    logic

    Mar. 23, 2001

    Transient
    region

    Inputs

    Output
    Observation
    instant

    VLSI Test: Bushnell-

    time

    Clock period

    Circuit Delays

    Switching or inertial delay is the interval between


    input change and output change of a gate:

    Propagation or interconnect delay is the time a


    transition takes to travel between gates:

    Depends on input capacitance, device (transistor)


    characteristics and output capacitance of gate.
    Also depends on input rise or fall times and states of
    other inputs (second-order effects).
    Approximation: fixed rise and fall delays (or min-max
    delay range, or single fixed delay) for gate output.

    Depends on transmission line effects (distributed R, L,


    C parameters, length and loading) of routing paths.
    Approximation: modeled as lumped delays for gate
    inputs.

    See Section 5.3.5 for timing models.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    Event Propagation
    Delays

    Single lumped inertial delay modeled for each gate


    PI transitions assumed to occur without time skew
    Path P1
    1

    13

    P2

    Mar. 23, 2001

    3
    2

    246

    P3
    5

    VLSI Test: Bushnell-

    Circuit Outputs

    Each path can potentially produce one signal


    transition at the output.
    The location of an output transition in time is
    determined by the delay of the path.
    Clock period

    Final value

    Initial value
    Fast transitions

    Slow transitions

    time
    Initial value

    Mar. 23, 2001

    Final value

    VLSI Test: Bushnell-

    Singly-Testable Paths
    (Non-Robust Test)

    The delay of a target path is tested if the test


    propagates a transition via path to a path destination.
    Delay test is a combinational vector-pair, V1,V2, that:

    dont
    care
    V1 V2

    Produces a transition at path input.


    Produces static sensitization -- All off-path inputs
    assume non-controlling states in V2.
    Off-path inputs

    V1 V2

    Target
    path
    Static sensitization guarantees a test when the target path is the
    only faulty path. The test is, therefore, called non-robust. It is a test
    with minimal restriction. A path with no such test is a false path.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    Robust Test

    A robust test guarantees the detection of a


    delay fault of the target path, irrespective
    of delay faults on other paths.
    A robust test is a combinational vector-pair,
    V1, V2, that satisfies following conditions:

    Produce real events (different steady-state


    values for V1 and V2) on all on-path signals.
    All on-path signals must have controlling
    events arriving via the target path.

    A robust test is also a non-robust test.


    Concept of robust test is general robust
    tests for other fault models can be defined.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    Robust Test
    Conditions

    Real events on target path.


    Controlling events via target path.
    V1 V2

    V1 V2
    U1

    V1 V2

    S1

    U1/R1
    V1 V2

    Mar. 23, 2001

    U0/F0

    S0

    U0/F0
    V1 V2

    S0

    S1
    U0/F0

    V1 V2

    U0

    U1
    U1/R1

    U0

    U0/F0

    U1/R1

    VLSI Test: Bushnell-

    U1/R1

    A Five-Valued Algebra

    Signal States: S0, U0 (F0), S1, U1 (R1), XX.


    On-path signals: F0 and R1.
    Off-path signals: F0=U0 and R1=U1.
    Input 1

    S0
    U0
    S1
    U1
    XX

    S0 U0 S1 U1 XX
    S0
    S0
    S0
    S0
    S0

    S0
    U0
    U0
    U0
    U0

    S0
    U0
    S1
    U1
    XX

    NOT

    S0
    U0
    U1
    U1
    XX

    S0
    U0
    XX
    XX
    XX

    S0 U0 S1 U1 XX

    OR
    Input 2

    Input 2

    AND

    Input 1

    S0
    U0
    S1
    U1
    XX

    S0
    U0
    S1
    U1
    XX

    Input
    S0 U0 S1 U1 XX
    S1 U1 S0 U0 XX

    Mar. 23, 2001

    VLSI Test: Bushnell-

    U0
    U0
    S1
    U1
    XX

    S1 U1 XX
    S1 U1 XX
    S1 S1 S1
    S1 U1 U1
    S1 U1 XX
    Ref.:
    Lin-Reddy
    IEEETCAD-87

    10

    Robust Test Generation


    Test for

    P3 falling transition through path P3: Steps A through E

    E. Set input of AND gate to


    S0 to justify S0 at output
    XX S0
    C. F0 interpreted as U0;
    propagates through
    AND gate

    Path P3

    F0

    U0

    U0

    F0

    R1

    B. Propagate F0 through OR gate;


    also propagates as R1 through
    NOT gate

    Mar. 23, 2001

    D. Change off-path input


    to S0 to Propagate R1
    through OR gate
    R1

    A. Place F0 at
    path origin

    XX

    S0
    U0

    VLSI Test: Bushnell-

    Robust Test:
    S0, F0, U0

    11

    Fault

    Non-Robust Test
    Generation

    P2 rising transition through path P2 has no robust test.

    C. Set input of AND gate to


    propagate R1 to output
    XX U1

    D. R1 non-robustly propagates
    through OR gate since offR1 path input is not S0

    R1
    Path P2

    A. Place R1 at
    path origin

    U1

    R1
    R1

    U1

    U0

    XX
    U0

    Non-robust test requires


    Static sensitization:
    S0=U0, S1=U1

    B. Propagate R1 through OR gate;


    interpreted as U1 on off-path signal;
    propagates as U0 through NOT gate

    Mar. 23, 2001

    VLSI Test: Bushnell-

    Non-robust test:
    U1, R1, U0

    12

    Path-Delay Faults
    (PDF)

    Two PDFs (rising and falling transitions) for each physical


    path.
    Total number of paths is an exponential function of gates.
    Critical paths, identified by static timing analysis (e.g.,
    Primetime from Synopsys), must be tested.
    PDF tests are delay-independent. Robust tests are
    preferred, but some paths have only non-robust tests.
    Three types of PDFs (Gharaybeh, et al., JETTA (11), 1997):

    Singly-testable PDF has a non-robust or robust test.


    Multiply-testable PDF a set of singly untestable faults

    that has a non-robust or robust test. Also known as


    functionally testable PDF.
    Untestable PDF a PDF that is neither singly nor multiply
    testable.

    A singly-testable PDF has at least one single-input change


    (SIC) non-robust test.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    13

    Other Delay Fault


    Models
    Segment-delay fault -- A segment of an I/O path is

    assumed to have large delay such that all paths


    containing the segment become faulty.
    Transition fault -- A segment-delay fault with segment of
    unit length (single gate):

    Two faults per gate; slow-to-rise and slow-to-fall.


    Tests are similar to stuck-at fault tests. For example, a

    line is initialized to 0 and then tested for s-a-0 fault to


    detect slow-to-rise transition fault.
    Models spot (or gross) delay defects.

    Line-delay fault A transition fault tested through the


    longest delay path. Two faults per line or gate. Tests
    are dependent on modeled delays of gates.
    Gate-delay fault A gate is assumed to have a delay
    increase of certain amount (called fault size) while all
    other gates retain some nominal delays. Gate-delay
    faults only of certain sizes may be detectable.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    14

    Slow-Clock Test
    Combinational
    circuit

    Input
    latches
    Input
    test clock

    Test
    clock
    period

    Input
    test clock

    Rated
    clock
    period

    Output
    latches
    Output
    test clock

    Output
    test clock
    V1
    applied

    Mar. 23, 2001

    V2
    applied Output
    latched

    VLSI Test: Bushnell-

    15

    Enhanced-Scan Test
    CK
    period
    Combinational

    PO
    CK

    circuit
    CK TC
    HL

    SFF

    HL

    SFF

    HOLD

    HOLD
    V1 settles
    SCANIN
    TC

    CK TC
    CK: system clock
    TC: test control
    HOLD: hold signal
    SFF: scan flip-flop
    HL: hold latch

    Mar. 23, 2001

    Scanout
    result

    Scanin
    V1
    states
    V1 PI
    applied

    VLSI Test: Bushnell-

    Scan mode

    Normal
    mode

    SCANOUT

    Normal
    mode

    PI

    Scanin
    V2 states

    Result
    latched
    V2 PI
    applied

    16

    Normal-Scan Test
    V2 states generated, (A) by one-bit scan shift of V1, or
    (B) by V1 applied in functional mode.
    Combinational

    V1 PIs
    applied

    PO

    Scanin
    Gen. V2
    V1 states states

    circuit
    SCANOUT

    CK TC

    Slow clock

    SFF
    SFF

    SCANIN

    TC
    (A)

    Mar. 23, 2001

    Path
    tested

    Result
    scanout

    Rated
    CK period

    Scan mode

    Scan mode

    Slow CK
    period

    CK TC
    CK: system clock
    TC: test control
    SFF: scan flip-flop

    V2 PIs
    applied

    Normal
    mode

    PI

    Result
    latched

    TC
    (B) Scan mode

    VLSI Test: Bushnell-

    Normal mode

    Scan mode

    17

    Variable-Clock Sequential
    Test
    Off-path
    flip-flop

    PI

    PI

    PI
    0

    n-2

    PO

    PI

    PI

    n-1

    PO

    PI

    PO

    Initialization sequence
    (slow clock)

    D
    PO

    Path
    activation
    (rated
    Clock)

    n+1

    PO

    n+m

    PO

    Fault effect
    propagation
    sequence
    (slow clock)

    Note: Slow-clock makes the circuit fault-free in the presence of


    delay faults.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    18

    Variable-Clock Models

    Fault effect propagation can be affected by ambiguous


    states of off-path flip-flops at the end of the rated-clock
    time-frame (Chakraborty, et al., IEEETCAD, Nov. 1997):

    Fault model A Off-path flip-flops assumed to be in


    correct states; sequential non-robust test (optimistic).
    Fault model B Off-path flip-flops assumed to be in
    unknown state; sequential robust test (pessimistic).
    Fault model C Off-path flip-flops in steady (hazardfree) state retain their correct values, while others
    assume unknown state; sequential robust test.

    Test length: A test sequence of N vectors is repeated N


    times, with a different vector applied at rated-clock
    each time.

    Test time ~ N2 x (slow-clock period)

    Mar. 23, 2001

    VLSI Test: Bushnell-

    19

    Variable-Clock
    Example

    ISCAS89 benchmark s35932 (non-scan).


    2,124 vectors obtained by simulatorselection from random vectors (Parodi, et
    al., ITC-98).
    PDF coverage, 26,228/394,282 ~ 6.7%
    Longest tested PDF, 27 gates; longest path
    has 29 gates.
    Test time ~ 4,511,376 clocks.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    20

    Rated-Clock Sequential
    Test

    All vectors are applied with rated-clock.


    Paths are singly and multiply activated
    potentially in several time-frames.
    Test generation requires a 41-valued logic
    (Bose, et al., IEEETVLSI, June 1998).
    Test generation is extremely complex for nonscan circuits (Bose and Agrawal, ATS-95).
    Fault simulators are effective but work with
    conservative assumptions (Bose, et al.,
    IEEETVLSI, Dec. 1993; Parodi, et al., ITC-98).

    Mar. 23, 2001

    VLSI Test: Bushnell-

    21

    Comparing PDF Test Modes

    Combinationally
    testable PDFs

    PDFs
    testable
    by variableclock seq.
    test

    All PDFs of
    seq. circuit
    PDFs testable by
    rated-clock seq. test
    Ref.: Majumder, et al., VLSI Design - 98

    Mar. 23, 2001

    VLSI Test: Bushnell-

    22

    At-Speed Test

    At-speed test means application of test vectors at


    the rated-clock speed.
    Two methods of at-speed test.
    External test:

    Vectors may test one or more functional critical


    (longest delay) paths and a large percentage
    (~100%) of transition faults.
    High-speed testers are expensive.

    Built-in self-test (BIST):

    Hardware-generated random vectors applied to


    combinational or sequential logic.
    Only clock is externally supplied.
    Non-functional paths that are longer than the
    functional critical path can be activated and cause
    a good circuit to fail.
    Some circuits have initialization problem.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    23

    Timing Design & Delay


    Test

    Timing simulation:

    Critical paths are identified by static (vector-less)


    timing analysis tools like Primetime (Synopsys).
    Timing or circuit-level simulation using designergenerated functional vectors verifies the design.

    Layout optimization: Critical path data are used


    in placement and routing. Delay parameter
    extraction, timing simulation and layout are
    repeated for iterative improvement.
    Testing: Some form of at-speed test is
    necessary. PDFs for critical paths and all
    transition faults are tested.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    24

    Summary

    Path-delay fault (PDF) models distributed delay


    defects. It verifies the timing performance of a
    manufactured circuit.
    Transition fault models spot delay defects and is
    testable by modified stuck-at fault tests.
    Variable-clock method can test delay faults but the
    test time can be long.
    Critical paths of non-scan sequential circuits can be
    effectively tested by rated-clock tests.
    Delay test methods (including BIST) for non-scan
    sequential circuits using slow ATE require
    investigation:

    Suppression of non-functional path activation in BIST.


    Difficulty of rated-clock PDF test generation.
    Long sequences of variable-clock tests.

    Mar. 23, 2001

    VLSI Test: Bushnell-

    25

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