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    Minor Project: 16 Bit Alu Using VHDL

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    Nikhil Sharma
    This document describes a 16-bit ALU project using VHDL. It provides background on VHDL, advantages of using VHDL, an example of an AND gate in VHDL, and discusses the current progress of the 16-bit ALU project which is still under development. The full VHDL code for the 16-bit ALU is included.

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    Minor Project: 16 Bit Alu Using VHDL

    Uploaded by

    Nikhil Sharma
    56 views13 pages
    This document describes a 16-bit ALU project using VHDL. It provides background on VHDL, advantages of using VHDL, an example of an AND gate in VHDL, and discusses the current progress of the 16-bit ALU project which is still under development. The full VHDL code for the 16-bit ALU is included.

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    16 bit alu using vhdl

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    Niks

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    This document describes a 16-bit ALU project using VHDL. It provides background on VHDL, advantages of using VHDL, an example of an AND gate in VHDL, and discusses the current progress of the 16-bit ALU project which is still under development. The full VHDL code for the 16-bit ALU is included.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    56 views13 pages

    Minor Project: 16 Bit Alu Using VHDL

    Uploaded by

    Nikhil Sharma
    This document describes a 16-bit ALU project using VHDL. It provides background on VHDL, advantages of using VHDL, an example of an AND gate in VHDL, and discusses the current progress of the 16-bit ALU project which is still under development. The full VHDL code for the 16-bit ALU is included.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 13

    MINOR PROJECT

    16 BIT ALU USING VHDL


    SUBMITTED BY:

    SUBMITTED TO: Mr. J P SHIVHARE


    MRS. MEENAKSHI

    NIKHIL CHHILLAR(10 ECU 110)

    VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

    VHDL was originally developed at the behest of the U.S Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details. The initial version of VHDL, designed to IEEE standard 10761987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plusarrays of bit called bit_vector and of character called string.

    ADVANTAGES OF VHDL
    The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). Another benefit is that VHDL allows the description of a concurrent system. VHDL is a dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. A VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure). A VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base, for example VLSI with various technologies.

    AND GATE USING VHDL


    library IEEE; use IEEE.std_logic_1164.all; -- this is the entity entity ANDGATE is port ( I1 : in std_logic; I2 : in std_logic; O : out std_logic); end entity ANDGATE; -- this is the architecture architecture RTL of ANDGATE is begin O <= I1 and I2; end architecture RTL;

    PROGRESS OF PROJECT
    We have made a program in VHDL for a 16 bit alu which is still under process. The program made by us requires XILINX software which allows us to verify the program before using it in actual hardware.

    PROGRAM
    library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

    -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

    entity aluloop is Port ( x : in std_logic_vector(15 downto 0); s1: in std_logic_vector(3 downto 0); y : out std_logic; z : out std_logic_vector(15 downto 0)); end aluloop; architecture alu of aluloop is begin process(x,s1) variable u,v,w,s,p,q:std_logic; variable i,j,k,l,m,n:integer;

    begin u:='0'; v:='1'; w:='1'; s:='1'; p:='1'; q:='1'; i:=0; j:=0; k:=0; l:=0; m:=0; n:=0;

    case s1 is when "0000"=> a1:loop if(i>19)then exit; end if; u:=u or x(i); i:=i+1; end loop a1; y<=u; when "0001"=> a2:loop if(j>15)then exit;

    end if; v:=v and x(j); j:=j+1; end loop a2; y<=v; when "0010"=> a3:loop if(k>15)then exit; end if; w:=w nand x(k); k:=k+1; end loop a3; y<=w; when "0011"=> a4:loop if(l>15)then exit;

    end if; s:=s xor x(l); l:=l+1; end loop a4; y<=s; when "0100"=> a5:loop if(m>15)then exit; end if; p:=p xnor x(m); m:=m+1; end loop a5;

    y<=p; when "0101"=> a6:loop if(n>15)then exit; end if; q:=q nor x(n); n:=n+1; end loop a6; y<=q; when "0110"=> z<= not x; when others=> y<='0';

    end case; end process; end alu;

    THANK YOU

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