William Stallings Computer Organization and Architecture: CPU Structure and Function
William Stallings Computer Organization and Architecture: CPU Structure and Function
William Stallings Computer Organization and Architecture: CPU Structure and Function
CPU Structure
CPU must:
Fetch instructions Interpret instructions Fetch data Process data Write data
Registers
CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy
Addressing
Segment
How big?
Large enough to hold full address Large enough to hold full word Often possible to combine two data registers
C programming double int a; long int a;
Supervisor Mode
Intel ring zero Kernel mode Allows privileged instructions to execute Used by operating system Not available to user programs
Other Registers
May have registers pointing to:
Process control blocks (see O/S) Interrupt Vectors (see O/S)
N.B. CPU design and operating system design are closely linked
Foreground Reading
Stallings Chapter 11 Manufacturer web sites & specs
Instruction Cycle
Revision Stallings Chapter 3
Indirect Cycle
May require memory access to fetch operands Indirect addressing requires more memory accesses Can be thought of as additional instruction subcycle
Prefetch
Fetch accessing main memory Execution usually does not access main memory Can fetch next instruction during execution of current instruction Called instruction prefetch
Improved Performance
But not doubled:
Fetch usually shorter than execution
Prefetch more than one instruction?
Any jump or branch means that prefetched instructions are not the required instructions
Pipelining
Fetch instruction Decode instruction Calculate operands (i.e. EAs) Fetch operands Execute instructions Write result Overlap these operations
Timing of Pipeline
Branch in a Pipeline
Multiple Streams
Have two pipelines Prefetch each branch into a separate pipeline Use appropriate pipeline Leads to bus & register contention Multiple branches lead to further pipelines being needed
Loop Buffer
Very fast memory Maintained by fetch stage of pipeline Check buffer before fetching from memory Very good for small loops or jumps c.f. cache Used by CRAY-1
Foreground Reading
Processor examples Stallings Chapter 11 Web pages etc.