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    Processing Unit

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    Yash Dongare
    The document discusses the structure and function of the CPU. It covers the major components of the CPU including registers, instruction cycle, data flow, and prefetching. Registers are divided into user-visible and control/status registers. The instruction cycle includes fetch, execute, and interrupt stages. Data flow diagrams illustrate the instruction fetch, data fetch, and interrupt processes.

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    Processing Unit

    Uploaded by

    Yash Dongare
    9 views25 pages
    The document discusses the structure and function of the CPU. It covers the major components of the CPU including registers, instruction cycle, data flow, and prefetching. Registers are divided into user-visible and control/status registers. The instruction cycle includes fetch, execute, and interrupt stages. Data flow diagrams illustrate the instruction fetch, data fetch, and interrupt processes.

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    The document discusses the structure and function of the CPU. It covers the major components of the CPU including registers, instruction cycle, data flow, and prefetching. Registers are divided into user-visible and control/status registers. The instruction cycle includes fetch, execute, and interrupt stages. Data flow diagrams illustrate the instruction fetch, data fetch, and interrupt processes.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    9 views25 pages

    Processing Unit

    Uploaded by

    Yash Dongare
    The document discusses the structure and function of the CPU. It covers the major components of the CPU including registers, instruction cycle, data flow, and prefetching. Registers are divided into user-visible and control/status registers. The instruction cycle includes fetch, execute, and interrupt stages. Data flow diagrams illustrate the instruction fetch, data fetch, and interrupt processes.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 25

    William Stallings

    Computer Organization
    and Architecture
    8th Edition

    Chapter 12
    CPU Structure
    and Function
    CPU Structure
    • CPU must:
    —Fetch instructions
    —Interpret instructions
    —Fetch data
    —Process data
    —Write data
    CPU With Systems Bus
    CPU Internal Structure
    Registers
    • CPU must have some working space (temporary storage)
    Called registers.
    • Number and function of register vary between processor
    designs.
    • It is one of the major design decisions of processor.
    • It is at top level of memory hierarchy.
    • Two Types of registers:
    1) User-visible registers: Enable the machine/assembly
    language programmer to minimize main memory
    references by optimizing use of registers.
    2) Control & status registers: Used by the control unit
    to control the operation of processor and by privileged,
    operating system programs to control the execution of
    programs.
    User Visible Registers
    Enable the machine- or assembly language programmer
    to minimize main memory references by optimizing use
    of registers.

    We can characterize these in the following


    categories:
    • General Purpose registers
    • Data registers
    • Address registers
    • Condition Codes registers
    General Purpose Registers (1)
    • General-purpose registers can be assigned to a variety of functions
    by the programmer.
    • Sometimes their use within the instruction set is orthogonal to the
    operation. That is, any general-purpose register can contain the
    operand for any opcode.
    • This provides true general-purpose register use. Often, however,
    there are restrictions. For example, there may be dedicated
    registers for floating-point and stack operation. Can be used as
    data or address for examples:
    • Data
    — Accumulator
    • Addressing
    — Segment pointers
    — Index registers
    — Stack pointer
    General Purpose Registers (2)
    • Make them general purpose
    —Increase flexibility and programmer options
    —Increase instruction size & complexity
    • Make them specialized
    —Smaller (faster) instructions
    —Less flexibility
    Design issues of GP Registers
    • An important issue is whether to use completely
    general-purpose registers or to specialize their
    use.
    • Another design issue is the number of registers,
    either general purpose or data plus address, to
    be provided.
    • Finally, there is the issue of register length.
    How Many GP Registers?
    • Between 8 - 32
    • Fewer = more memory references
    • More does not reduce memory references and
    takes up processor real estate
    • See also RISC
    How big?
    • Large enough to hold full address
    • Large enough to hold full word
    • Often possible to combine two data registers
    —C programming
    —double int a;
    —long int a;
    Example Register Organizations
    Instruction Cycle
    An instruction cycle includes the following
    stages:
    • Fetch: Read the next instruction from memory
    into the processor.
    • Execute: Interpret the opcode and perform the
    indicated operation.
    • Interrupt: If interrupts are enabled and an
    interrupt has occurred, save the current process
    state and service the interrupt.
    Diagram of Instruction Cycle
    Indirect Cycle
    • May require memory access to fetch operands
    • Indirect addressing requires more memory
    accesses
    • Can be thought of as additional instruction
    subcycle
    Data Flow: Instruction Cycle State
    Diagram
    Data Flow (Instruction Fetch)
    Let us assume that a processor that employs a
    memory address register (MAR), a memory buffer
    register (MBR), a program counter (PC), and an
    Instruction register (IR).
    • Fetch
    —PC contains address of next instruction
    —Address moved to MAR
    —Address placed on address bus
    —Control unit requests memory read
    —Result placed on data bus, copied to MBR, then to IR
    —Meanwhile PC incremented by 1
    Data Flow (Data Fetch)
    • IR is examined
    • If indirect addressing, indirect cycle is
    performed
    —Right most N bits of MBR transferred to MAR
    —Control unit requests memory read
    —Result (address of operand) moved to MBR
    Data Flow (Fetch Diagram)
    Data Flow (Indirect Diagram)
    Data Flow (Execute)
    • May take many forms
    • Depends on instruction being executed
    • May include
    —Memory read/write
    —Input/Output
    —Register transfers
    —ALU operations
    Data Flow (Interrupt)
    • Simple
    • Predictable
    • Current PC saved to allow resumption after
    interrupt
    • Contents of PC copied to MBR
    • Special memory location (e.g. stack pointer)
    loaded to MAR
    • MBR written to memory
    • PC loaded with address of interrupt handling
    routine
    • Next instruction (first of interrupt handler) can
    be fetched
    Data Flow (Interrupt Diagram)
    Prefetch
    • Fetch accessing main memory
    • Execution usually does not access main memory
    • Can fetch next instruction during execution of
    current instruction
    • Called instruction prefetch
    Improved Performance
    • But not doubled:
    —Fetch usually shorter than execution
    – Prefetch more than one instruction?
    —Any jump or branch means that prefetched
    instructions are not the required instructions
    • Add more stages to improve performance

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