Scaling of MOSFETs and Short Channel Effects

MOSFET Scaling and
Small Geometry Effects
Design of high-density chips require a packing

density as high as possible.
Transistors fabricated should have sizes as
small as possible.
The systematic reduction in the dimensions of
devices is referred to as MOSFET scaling.
It causes change in MOSFET operational
characteristics.
There are physical limitations to the extent
of scaling.
Geometric ratios found in larger devices are usually

preserved.
It results in total area reduction
Hence gives increased overall functional density of
the chip.
Full Scaling: Constant field scaling

Constant voltage scaling
Scaling factor S>1
Scaled device dimensions = larger device dimensions
divided by S
Reduction of min feature size for a typical

CMOS gate array process:
Year
Feature
Size (m)
1985 1987 1989 1991 1993 1995 1997 1999

2.5
1.7
1.2
1.0
0.8
0.5 0.35 0.25
S ranges from 1.2 to 1.5 for every successive generations.
Full Scaling :
*Aims at preserving the magnitude of internal
electric fields in the MOSFET.
*For this, all potentials must be scaled by same
scaling factor.
*Affects the threshold voltage.
*So, the charge densities must be increased in
the same proportion.
The influence of full scaling on

C-V characteristics of MOSFET:
(Assumed that mobility is not affected significantly by scaling)
Significant power reduction is most attractive

feature of full scaling.
However power density per unit area remains
unchanged.
Constant voltage scaling:

*Peripheral and interfacing circuitry may require certain voltage
levels and hence full scaling is not advisable.
*Constant voltage scaling is preferred here.
*All dimensions of MOSFET are scaled. However, the power supply
voltage and the terminal voltages remain unchanged.
*To preserve the charge-field relations, doping densities must be
increased.
How Doping Densities are Scaled?
Short Channel Effects

Short Channel Device:
Channel length Depletion region thickness
OR
Effective channel length Source / Drain junction Depth
Attributes:
1. Limitations imposed on electron drift
characteristics in the channel
2. Modification of threshold voltage due to the
shortening of channel length
Following are major short channel effects:

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Velocity Saturation
Surface Scattering
Hot Electrons
Drain Induced Barrier Lowering (DIBL) &
Subthreshold Conductance
Gate Oxide Leakage
Gate Induced Drain Leakage (GIDL)
Lower Transconductance
Stress Induced Leakage Current (SILC)
Channel Length Modulation
Impact Ionization
VELOCITY SATURATION
At low Ey, the electron drift velocity vd in the channel varies
linearly with the electric field intensity.
However, as Ey increases above 104 V/cm, the drift velocity
tends to increase slowly, and approaches a saturation value of vd
= 107 cm/s around Ey = 105 V/cm at 300 K.
As the field increases above 104 V/cm, optical phonons are
emitted alongside acoustic phonon.
Due to this, the drift velocity cannot increase above certain

level and it becomes saturated. So, the current eventually is
found lesser than the anticipated value.
SURFACE SCATTERING
As the channel length becomes smaller, due to the lateral extension
of the depletion layer into the channel region, the longitudinal
electric field component Ey increases, and the surface mobility

becomes field-dependent.
Since the carrier transport in a MOSFET is confined within the

narrow inversion layer, and the surface scattering, that is the
collisions suffered by the electrons that are accelerated toward the
interface by Ex causes reduction of the mobility and the electrons
move with great difficulty parallel to the interface.
So, the average surface mobility becomes less as compared to that

of the bulk mobility and eventually it affects the current.
HOT ELECTRON
EFFECTS
Due to high electric field near the
Si-SiO2 interface electrons gain
sufficient energy to cross the
interface potential barrier and
enter into the oxide layer .
They are trapped causing oxide
charging which accumulate with
time.
This causes transistor threshold
shift and mobility change effecting
gates control on drain current.
It can be reduced by using better
quality oxides.
DRAIN INDUCED BARRIER LOWERING AND

SUBTHRESHOLD CURRENT
In
small-geometry
MOSFETs,
the
potential barrier is controlled by both the
gate-to-source voltage Vgs and the drainto-source voltage Vds.
If the drain voltage is increased, the
potential barrier in the channel decreases,
leading to drain-induced barrier lowering
(DIBL).
The reduction of the potential barrier
eventually allows electron flow between
the source and the drain, even if the gateto-source voltage is lower than the
threshold voltage.
The channel current that flows under this conditions (Vgs < Vt) is called the
sub-threshold current.
Punch Through:
For large drain bias voltage, the depletion
region of drain extends towards source and
merges. This is called punch through.
Punch through can be minimized by:
1.
2.
3.
4.
Thinner oxide
Larger substrate doping
Shallower junctions
Longer channels
Increased gate-oxide leakage

The gate oxide, should be made as thin as possible to increase
the channel conductivity and performance when the transistor
is on and to reduce subthreshold leakage when the transistor is
off.
However, with very thin gate oxides the quantum mechanical
phenomenon of electron tunnelling occurs between the gate and
channel, leading to increased power consumption
Insulators that have a larger dielectric constant than silicon

dioxide (referred to as high-k dielectrics), such as group IV B
metal silicates e.g. hafnium and zirconium silicates and oxides
are being used to reduce the gate leakage from the 45
nanometre technology node onwards.
GATE INDUCED DRAIN LEAKAGE (GIDL)

Vgs<0, Vds>0
Higher supply voltage and thinner oxide increase GIDL.
The n+ drain region under the gate is be

depleted and even inverted. This causes field
crowding and the peak.
So field increase, resulting in avalanche
multiplication and band-to-band tunneling.
Thus minority carriers are emitted in the drain

region underneath the gate and leakage current
flows through the substrate.
Thinner oxide, higher Vdd enhances the electric
field and therefore increase GIDL.
GIDL increases with the increase in Vdb and Vdg.
LOWER TRANSCONDUCTANCE
The transconductance of the MOSFET decides its

gain and is proportional to hole or electron mobility.
As MOSFET size is reduced, the fields in the
channel increase and the dopant impurity levels
increase. Both changes reduce the carrier mobility,
and hence the transconductance.
Velocity saturation of the carriers, limiting the
current and the transconductance.
STRESS INDUCED LEAKAGE CURRENT
Stress Induced Leakage Current (SILC) is an

increase in the gate leakage current of a MOSFET,
due to defects created in the gate oxide during
electrical stressing.
No SILC was observed for thinner films, while
thicker oxides shows large variation due to process
induced charging damage.
The effect of different gate poly-Si etching
process in a high density plasma system were also
evaluated. Only the gate that was etched with an
abnormally high bias power over etch process, and
connected to large connection antenna ratio shows
Example: SILC increases as the contact antenna size

increases in 3.7nm and 5.2nm gate oxide
Channel Length Modulation
The pinch-off point moves toward the source as VDS

increases.
The length of the inversion-layer channel becomes
shorter with increasing VDS.
ID increases (slightly) with increasing VDS in the
saturation region of operation.
I D , sat
1
W
VGS VTH
nCox
2
L
2 1 VDS VD,sat
The effect of channel-length modulation is less for a

long-channel MOSFET than for a short-channel
MOSFET.
IMPACT IONIZATION
Occurs especially in NMOS due to the high velocity of electrons in presence
of high longitudinal fields that can generate electron-hole (e-h) pairs by
impact ionization, that is, by impacting on silicon atoms and ionizing them.
Normally, most of the electrons are attracted by the drain, while the holes
enter the substrate to form part of the parasitic substrate current.
Moreover, the region between the source and the drain can act like the base
of an npn transistor, with the source playing the role of the emitter and the
drain that of the collector. If the holes are collected by the source, and the
corresponding hole current creates a voltage drop in the substrate material,
the normally reversed-biased substrate-source pn junction will conduct
appreciably.
Then electrons can be injected from the source to the substrate, similar to
the injection of electrons from the emitter to the base. They can gain enough
energy as they travel toward the drain to create new e-h pairs.
The situation can get worst if some electrons generated due to high fields
escape the drain field to travel into the substrate, thereby affecting other
devices on a chip.
An example of an incoming electron impact ionizing to

produce a new electron-hole pair

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MOSFET Scaling and

Small Geometry Effects

Design of high-density chips require a packing

Geometric ratios found in larger devices are usually

Full Scaling: Constant field scaling

Reduction of min feature size for a typical

1985 1987 1989 1991 1993 1995 1997 1999

0.5 0.35 0.25

S ranges from 1.2 to 1.5 for every successive generations.

The influence of full scaling on

Significant power reduction is most attractive

Constant voltage scaling:

How Doping Densities are Scaled?

Short Channel Effects

Following are major short channel effects:

Due to this, the drift velocity cannot increase above certain

electric field component Ey increases, and the surface mobility

Since the carrier transport in a MOSFET is confined within the

So, the average surface mobility becomes less as compared to that

DRAIN INDUCED BARRIER LOWERING AND

Increased gate-oxide leakage

Insulators that have a larger dielectric constant than silicon

GATE INDUCED DRAIN LEAKAGE (GIDL)

The n+ drain region under the gate is be

Thus minority carriers are emitted in the drain

GIDL increases with the increase in Vdb and Vdg.

The transconductance of the MOSFET decides its

STRESS INDUCED LEAKAGE CURRENT

Stress Induced Leakage Current (SILC) is an

Example: SILC increases as the contact antenna size

Channel Length Modulation

The pinch-off point moves toward the source as VDS

The effect of channel-length modulation is less for a

An example of an incoming electron impact ionizing to

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