Digital System Design Based On Data Path and Control Unit
Digital System Design Based On Data Path and Control Unit
Digital System Design Based On Data Path and Control Unit
Outline
1-2
Digital Systems
Digital systems
Control-dominated systems :
1-3
1-4
1-5
1-6
The data path contains blocks that only deal with data;
they do not provide control to any other blocks and
need to be controlled (by the CU).
Registers
1-9
Shift Registers
1-10
Modulo 7 (0,1,,6):
1-11
Three-State Devices
1-12
1-13
Design Steps
1-14
1-15
1-16
1-18
count
A single bit terminal count: indicates that a total number of
clock cycles are elapsed and the counter is back to 0
1-19
1-20
1-21
1-22
CU design
EN1=TC_30 + GE_15.cross1
EN2=TC_30 + GE_15.cross2
EN3=TC_5
CNT_RES=1
State YR: Y1=1, R2=1
State T2: R1=1, G2=1
CNT_RES=1, FF_RES=1
State RG: R1=1, G2=1
State T3: R1=1, Y2=1
CNT_RES=1
State RY: R1=1, Y2=1
State T4: G1=1, R2=1
CNT_RES=1, FF_RES=1
1-24
1-26
1-27
state
binary
code
one or more
operations
1-28
deciding
factors
deciding
factors
1-29
conditional
operations
1-30
A is a register;
1-31
Register Operations
Registers are present in the data processor for storing
and processing data. Flip-flops (1-bit registers) and
memories (set of registers) are also considered as
registers.
1-32
Register Operations
Examples of register operations:
AB
A0
A A 1
1-33
1-34
S
1
T1
A 0
F 0
A A+1
0
3 ASM blocks
A2
E 0
E 1
0
A3
T2
1
F 1
1-35
clock cycle
decision boxes are dependent on the status of the previous
clock cycle (that is, they do not depend on operations of
current block)
1-36
1-37
S
1
T1
A 0
F 0
Operations
A A+1
0
A A+1
A A+1
E 0
E 1
A A+1
A A+1
E 0
E 1
A2
E 0
E 1
0
A3
T2
1
F 1
A = A4A3A2A1
A 0
F 0
A A+1
F 1
E 0
A A+1
A A+1
E 0
E 1
Operations
1-38
1-39
1-40
T0
Initial state
T1
T2
T1
A 0
F 0
A A+1
0
A2
E 0
E 1
0
A3
T2
1
F 1
1-41
Guidelines:
always use high-level units
simplest architecture possible.
1-42
Deduce:
One 4-bit register A (e.g.: 4-bit synchronous counter with
clear/increment).
Two flip-flops needed for E and F (e.g.: JK flip-flops).
1-43
start
A3
(A
A + 1) when state = T1.
(A 0) when state = T0 and S = 1.
(E 1) when state = T1 and A2 =
1.
T0
Controller
T1
Clk
A2
T2
J
K
J
A4
A3
A2
4-bit syn.
counter A
A1
count
CP
clear
clock
1-44
Implementing Controller:
Decoder + D Flip-flops
Flip-flop input functions:
DG1 = T1.A2.A3
DG0 = T0.S + T1
Circuit:
1-45
ASMD chart
representation
1-46
1-47
1-48
Synchronous Reset
1-49
2:1 Decimator
1-50
2:1 Decimator
1-51
1-52