The ARM Architecture

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Agenda

Introduction to ARM Ltd Programmers Model Instruction Set System Design Development Tools

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ARM Ltd

Founded in November 1990

Spun out of Acorn Computers

Designs the ARM range of RISC processor cores

Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers.

ARM does not fabricate silicon itself

Also develop technologies to assist with the design-in of the ARM architecture

Software tools, boards, debug hardware, application software, bus architectures, peripherals etc

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ARM Partnership Model

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ARM Powered Products

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Intellectual Property

ARM provides hard and soft views to licencees

RTL and synthesis flows GDSII layout soft views include gate level netlists hard views are DSMs to protect ARM IP

Licencees have the right to use hard or soft views of the IP

OEMs must use hard views

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Agenda

Introduction to ARM Ltd

Programmers Model Instruction Sets System Design Development Tools

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Data Sizes and Instruction Sets

The ARM is a 32-bit architecture.

When used in relation to the ARM:

Byte means 8 bits Halfword means 16 bits (two bytes) Word means 32 bits (four bytes)

Most ARMs implement two instruction sets

32-bit ARM Instruction Set 16-bit Thumb Instruction Set

Jazelle cores can also execute Java bytecode

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Processor Modes

The ARM has seven basic operating modes:

User : unprivileged mode under which most tasks run

FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode

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The ARM Register Set

Current Visible Registers
Abort Mode Undef SVC Mode IRQ FIQ User Mode Mode Mode
r0 r1 r2 r3 r4 r5 r6

Banked out Registers

User
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

FIQ
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

IRQ

SVC

Undef

Abort

r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc)

cpsr spsr

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

spsr

spsr

spsr

spsr

spsr

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Register Organization Summary

User
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

FIQ

IRQ

SVC

Undef

Abort

User mode r0-r7, r15, and cpsr

r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

Thumb state Low registers

Thumb state High registers

r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr)

r15 (pc)
cpsr spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

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The Registers

ARM has 37 registers all of which are 32-bits long.

1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers

The current processor mode governs which of several banks is accessible. Each mode can access

a particular set of r0-r12 registers a particular r13 (the stack pointer, sp) and r14 (the link register, lr) the program counter, r15 (pc) the current program status register, cpsr

Privileged modes (except System) can also access

a particular spsr (saved program status register)

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Program Status Registers

31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q f

n s

e x

I F T c

mode

Condition code flags

Interrupt Disable bits.

N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation oVerflowed

I = 1: Disables the IRQ. F = 1: Disables the FIQ.

T Bit

Sticky Overflow flag - Q flag

Architecture 5TE/J only Indicates if saturation has occurred

Architecture xT only T = 0: Processor in ARM state T = 1: Processor in Thumb state

Mode bits

J bit

Specify the processor mode

Architecture 5TEJ only J = 1: Processor in Jazelle state

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Program Counter (r15)

When the processor is executing in ARM state:

All instructions are 32 bits wide All instructions must be word aligned Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned).

When the processor is executing in Thumb state:

All instructions are 16 bits wide All instructions must be halfword aligned Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).

When the processor is executing in Jazelle state:

All instructions are 8 bits wide Processor performs a word access to read 4 instructions at once

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Exception Handling

When an exception occurs, the ARM:

Copies CPSR into SPSR_<mode> Sets appropriate CPSR bits

Change to ARM state Change to exception mode Disable interrupts (if appropriate)

0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00

FIQ IRQ (Reserved) Data Abort Prefetch Abort

Software Interrupt Undefined Instruction

Stores the return address in LR_<mode> Sets PC to vector address Restore CPSR from SPSR_<mode> Restore PC from LR_<mode>

To return, exception handler needs to:

Reset

This can only be done in ARM state.

Vector Table
Vector table can be at 0xFFFF0000 on ARM720T and on ARM9/10 family devices

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Development of the ARM Architecture

Halfword and signed halfword / byte support System mode

4
SA-110 SA-1110

1 2 3
Early ARM architectures

Improved ARM/Thumb Interworking CLZ

5TE

Jazelle

Java bytecode execution

ARM9EJ-S ARM7EJ-S

5TEJ

Saturated maths DSP multiplyaccumulate instructions ARM1020E

ARM926EJ-S ARM1026EJ-S

Thumb instruction set ARM7TDMI ARM720T

SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support

4T
ARM9TDMI ARM940T

XScale ARM9E-S ARM966E-S

ARM1136EJ-S

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Agenda

Introduction to ARM Ltd Programmers Model

Instruction Sets System Design Development Tools

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Conditional Execution and Flags

ARM instructions can be made to execute conditionally by postfixing them with the appropriate condition code field.

This improves code density and performance by reducing the number of forward branch instructions.
CMP BEQ ADD skip r3,#0 skip r0,r1,r2 CMP r3,#0 ADDNE r0,r1,r2

By default, data processing instructions do not affect the condition code flags but the flags can be optionally set by using S. CMP does not need S.
loop SUBS r1,r1,#1 BNE loop

decrement r1 and set flags if Z flag clear then branch

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Condition Codes

The possible condition codes are listed below:

Note AL is the default and does not need to be specified

Suffix Description Equal Not equal Unsigned higher or same Unsigned lower Minus Positive or Zero Overflow No overflow Unsigned higher Unsigned lower or same Greater or equal Less than Greater than Less than or equal Always Flags tested Z=1 Z=0 C=1 C=0 N=1 N=0 V=1 V=0 C=1 & Z=0 C=0 or Z=1 N=V N!=V Z=0 & N=V Z=1 or N=!V

EQ NE CS/HS CC/LO MI PL VS VC HI LS GE LT GT LE AL
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Examples of conditional execution

Use a sequence of several conditional instructions

if (a==0) func(1); CMP r0,#0 MOVEQ r0,#1 BLEQ func

Set the flags, then use various condition codes

if (a==0) x=0; if (a>0) x=1; CMP r0,#0 MOVEQ r1,#0 MOVGT r1,#1

Use conditional compare instructions

if (a==4 || a==10) x=0; CMP r0,#4 CMPNE r0,#10 MOVEQ r1,#0

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Branch instructions

Branch : Branch with Link :

B{<cond>} label BL{<cond>} subroutine_label

31

28 27

25 24 23

Cond

1 0 1 L

Offset

Link bit

0 = Branch 1 = Branch with link

Condition field

The processor core shifts the offset field left by 2 positions, sign-extends it and adds it to the PC

32 Mbyte range How to perform longer branches?

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Data processing Instructions

Consist of :

Arithmetic: Logical: Comparisons: Data movement:

ADD AND CMP MOV

ADC ORR CMN MVN

SUB EOR TST

SBC BIC TEQ

RSB

RSC

These instructions only work on registers, NOT memory. Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2

Comparisons set flags only - they do not specify Rd Data movement does not specify Rn

Second operand is sent to the ALU via barrel shifter.

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The Barrel Shifter

LSL : Logical Left Shift
CF

ASR: Arithmetic Right Shift

Destination
CF

Destination

Multiplication by a power of 2

Division by a power of 2, preserving the sign bit

LSR : Logical Shift Right

...0

ROR: Rotate Right

Destination
CF

Destination
Division by a power of 2

CF

Bit rotate with wrap around from LSB to MSB

RRX: Rotate Right Extended

Destination
CF

Single bit rotate with wrap around from CF to MSB

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Using the Barrel Shifter: The Second Operand

Operand 1
Operand 2
Register, optionally with shift operation

Shift value can be either be:

5 bit unsigned integer Specified in bottom byte of another register.

Barrel Shifter

Used for multiplication by constant

Immediate value

8 bit number, with a range of 0-255.

ALU

Rotated right through even number of positions

Allows increased range of 32-bit constants to be loaded directly into registers

Result
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Immediate constants (1)

No ARM instruction can contain a 32 bit immediate constant

All ARM instructions are fixed as 32 bits long

The data processing instruction format has 12 bits available for operand2
11 rot x2 8 7 immed_8 0

Quick Quiz:

Shifter ROR

0xe3a004ff MOV r0, #???

4 bit rotate value (0-15) is multiplied by two to give range 0-30 in steps of 2
Rule to remember is 8-bits shifted by an even number of bit positions.

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Immediate constants (2)

Examples:
31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ror #0 ror #8 ror #30

range 0-0x000000ff step 0x00000001 range 0-0xff000000 step 0x01000000 range 0-0x000003fc step 0x00000004

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0

The assembler converts immediate values to the rotate form: MOV r0,#4096 ; uses 0x40 ror 26 ADD r1,r2,#0xFF0000 ; uses 0xFF ror 16
The bitwise complements can also be formed using MVN: MOV r0, #0xFFFFFFFF ; assembles to MVN r0,#0 Values that cannot be generated in this way will cause an error.
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Loading 32 bit constants

To allow larger constants to be loaded, the assembler offers a pseudoinstruction: LDR rd, =const This will either: Produce a MOV or MVN instruction to generate the value (if possible). or

Generate a LDR instruction with a PC-relative address to read the constant from a literal pool (Constant data area embedded in the code).

For example LDR r0,=0xFF LDR r0,=0x55555555

=> =>

MOV r0,#0xFF LDR r0,[PC,#Imm12] DCD 0x55555555

This is the recommended way of loading constants into a register

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Multiply

Syntax:

MUL{<cond>}{S} Rd, Rm, Rs MLA{<cond>}{S} Rd,Rm,Rs,Rn [U|S]MULL{<cond>}{S} RdLo, RdHi, Rm, Rs [U|S]MLAL{<cond>}{S} RdLo, RdHi, Rm, Rs

Rd = Rm * Rs Rd = (Rm * Rs) + Rn RdHi,RdLo := Rm*Rs RdHi,RdLo := (Rm*Rs)+RdHi,RdLo

Cycle time

Basic MUL instruction

2-5 cycles on ARM7TDMI 1-3 cycles on StrongARM/XScale 2 cycles on ARM9E/ARM102xE

+1 cycle for ARM9TDMI (over ARM7TDMI) +1 cycle for accumulate (not on 9E though result delay is one cycle longer) +1 cycle for long

Above are general rules - refer to the TRM for the core you are using for the exact details
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Single register data transfer

LDR LDRB LDRH LDRSB LDRSH

STR STRB STRH

Word Byte Halfword Signed byte load Signed halfword load

Memory system must support all access sizes

Syntax:

LDR{<cond>}{<size>} Rd, <address> STR{<cond>}{<size>} Rd, <address>

e.g. LDREQB

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Address accessed

Address accessed by LDR/STR is specified by a base register plus an offset For word and unsigned byte accesses, offset can be

An unsigned 12-bit immediate value (ie 0 - 4095 bytes).

LDR r0,[r1,#8]

A register, optionally shifted by an immediate value

LDR r0,[r1,r2] LDR r0,[r1,r2,LSL#2]

This can be either added or subtracted from the base register:

LDR r0,[r1,#-8] LDR r0,[r1,-r2] LDR r0,[r1,-r2,LSL#2]

For halfword and signed halfword / byte, offset can be:

An unsigned 8 bit immediate value (ie 0-255 bytes). A register (unshifted).

Choice of pre-indexed or post-indexed addressing

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Pre or Post Indexed Addressing?

Pre-indexed: STR r0,[r1,#12]

Offset 12 r1
0x20c

r0 0x5 0x5

Source Register for STR

Base Register

0x200

0x200

Auto-update form: STR r0,[r1,#12]!

Post-indexed: STR r0,[r1],#12

Updated Base Register r1 0x20c Offset 12
0x20c

r0 0x5

Original Base Register

r1
0x200
0x200

0x5

Source Register for STR

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LDM / STM operation

Syntax: <LDM|STM>{<cond>}<addressing_mode> Rb{!}, <register list> 4 addressing modes:

LDMIA / STMIA LDMIB / STMIB LDMDA / STMDA LDMDB / STMDB increment after increment before decrement after decrement before

IA
LDMxx r10, {r0,r1,r4} STMxx r10, {r0,r1,r4}
Base Register (Rb) r10
r4 r1 r0

IB
r4 r1 r0

DA

DB

r4 r1 r0 r4 r1 r0

Increasing Address

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Software Interrupt (SWI)

31 28 27 24 23 0

Cond

1 1 1 1

SWI number (ignored by processor)

Condition Field

Causes an exception trap to the SWI hardware vector The SWI handler can examine the SWI number to decide what operation has been requested. By using the SWI mechanism, an operating system can implement a set of privileged operations which applications running in user mode can request. Syntax: SWI{<cond>} <SWI number>

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PSR Transfer Instructions

31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q f

n s

e x

I F T c

mode

MRS and MSR allow contents of CPSR / SPSR to be transferred to / from a general purpose register.

Syntax:

MRS{<cond>} Rd,<psr> ; Rd = <psr> MSR{<cond>} <psr[_fields]>,Rm ; <psr[_fields]> = Rm <psr> = CPSR or SPSR [_fields] = any combination of fsxc MSR{<cond>} <psr_fields>,#Immediate

where

Also an immediate form

In User Mode, all bits can be read but only the condition flags (_f) can be written.

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ARM Branches and Subroutines

B <label>

PC relative. 32 Mbyte range. Stores return address in LR Returning implemented by restoring the PC from LR For non-leaf functions, LR will have to be stacked

BL <subroutine>

func1
: : BL func1 : :

func2
: : : :

STMFD sp!,{regs,lr}
: BL func2 : LDMFD sp!,{regs,pc}

:
MOV pc, lr

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Thumb

Thumb is a 16-bit instruction set

Optimised for code density from C code (~65% of ARM code size) Improved performance from narrow memory Subset of the functionality of the ARM instruction set Switch between ARM and Thumb using BX instruction
ADDS r2,r2,#1
0

Core has additional execution state - Thumb

31

32-bit ARM Instruction

For most instructions generated by compiler:

Conditional execution is not used Source and destination registers identical Only Low registers used Constants are of limited size Inline barrel shifter not used

15

ADD r2,#1

16-bit Thumb Instruction

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Agenda

Introduction Programmers Model Instruction Sets

System Design Development Tools

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Example ARM-based System

16 bit RAM

32 bit RAM

Interrupt Controller
nIRQ nFIQ

Peripherals

I/O

8 bit ROM

ARM Core

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AMBA
Arbiter Reset

ARM
TIC Bridge External ROM External RAM Bus Interface Timer

External Bus Interface

On-chip RAM

Remap/ Pause

Decoder

Interrupt Controller

AHB or ASB System Bus

APB Peripheral Bus

AMBA

ACT

Advanced Microcontroller Bus Architecture

AMBA Compliance Testbench

ADK

PrimeCell

Complete AMBA Design Kit

ARMs AMBA compliant peripherals

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Agenda

Introduction Programmers Model Instruction Sets System Design

Development Tools

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The RealView Product Families

Compilation Tools
ARM Developer Suite (ADS) Compilers (C/C++ ARM & Thumb), Linker & Utilities

Debug Tools
AXD (part of ADS) Trace Debug Tools Multi-ICE Multi-Trace

Platforms
ARMulator (part of ADS) Integrator Family

RealView Compilation Tools (RVCT)

RealView Debugger (RVD) RealView ICE (RVI) RealView Trace (RVT)

RealView ARMulator ISS (RVISS)

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ARM Debug Architecture

Ethernet

Debugger (+ optional trace tools)

EmbeddedICE Logic

JTAG port

Trace Port

Provides breakpoints and processor/system access Converts debugger commands to JTAG signals Compresses real-time instruction and data access trace Contains ICE features (trigger & filter logic) Captures trace in a deep buffer
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JTAG interface (ICE)

TAP controller

ETM
EmbeddedICE Logic

Embedded trace Macrocell (ETM)

Trace port analyzer (TPA)

ARM core

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