Amba Axi
Amba Axi
Amba Axi
Advanced eXtensible
Interface
Fixed burst
- Address remains the same for every transfer in the burst
- Repeat access to the same location
Incrementing burst
- Address for the each transfer in the burst is an increment of the previous address
- The increment value depends on the size of the transfer
Wrapping burst
- The start address must be aligned to the size of the transfer
- The length of the burst must be 2, 4, 8 or 16.
Start_address
0x4b
0x4a
0x49
0x48
1st transfer
0x4f
0x4e
0x4d
0x4c
2st transfer
0x43
0x42
0x41
0x40
3st transfer
0x47
0x46
0x45
0x44
4st transfer
Write Strobes
WSTRB : Write strobes. This signal indicates which byte lanes to update in memory.
There is one strobe for each eight bits of the write data bus.
WDATA : 8 1024 bits wide
WSTRB : 1 128 bits wide
WSTRB
56 55
48 47
40 39
32 31
24 23
16 15
Aligned Transfer
Address: 0x00
Transfer size: 32 bits
Burst type: incrementing
Burst length: 4 transfers
WSTRB
WSTRB
56 55
48 47
40 39
32 31
24 23
16 15
F
7
E
6
D
5
C
4
B
3
A
2
1
9
0
8
Unaligned Transfer
Address: 0x07
Transfer size: 32 bits
Burst type: incrementing
Burst length: 4 transfers
WSTRB
WSTRB
56 55
48 47
40 39
32 31
24 23
16 15
F
7
E
6
D
5
C
4
B
3
A
2
1
9
0
8
F
7
E
6
D
5
C
4
B
3
A
2
1
9
0
8
17
16
15
14
13
12
11
10
Cache Support
Support for system level caches and other performance
enhancing components
Bufferable (B) bit, ARCACHE[0] and AWCACHE[0]
Cacheable (C) bit, ARCACHE[1] and AWCACHE[1]
Read Allocate (RA) bit, ARCACHE[2] and AWCACHE[2]
Write Allocate (WA) bit, ARCACHE[3] and AWCACHE[3]
Bufferable Bit
The interconnect or any component can delay the transaction
for an arbitrary number of cycles, usually only relevant to
writes
1
A1
1 1 1
A1 A2 A3
AXI
Master2
1
A3
2 2 2 2 2 2
B1 B1 B2 B2 B3 B3
AXI
Master1
2 2 2
B1 B2 B3
1
A2
AXI
Interconnect
1 2 1 2 1 2
A1 B1 A2 B2 A3 B3
AXI
Slave1
Write interleaving
depth = 2
If non-bufferable
Final destination to provide response
Bufferable
AXI
Master1
Non-bufferable
AXI
Interconnect
AXI
Master2
AXI
Slave1
Cache Support
Cacheable Bit
Write : a number of different writes can be merged together
Read : a location can be pre-fetched or can be fetched just once for
multiple read transactions
WSTRB
56 55
48 47
40 39
32 31
24 23
16 15
Cache Encoding
ARCACHE[3:0]
AWCACHE[3:0]
C : low
RA : low
WA : low
Normal / Privileged
This is used by some masters to indicate their processing
mode. A privileged processing mode typically has a greater
lever of access within a system
AXI
Master1
CPU
AXI
Master2
Normal
access
AXI
Slave1
Privileged
access
Normal
access
AXI
Interconnect
AXI
Slave2
Secure / Non-secure
This is used in systems where a greater degree of
differentiation between processing modes is required
Non-secure
AXI
Slave1
(Secure)
Secure
AXI
Master1
AXI
Interconnect
AXI
Slave2
(Non-secure)
AXI
Slave3
(Non-secure)
SLVERR response
OKAY response
DECERR response
Non-secure slave
disappears from the
memory map during
secure accesses
Data / Instruction
This bit gives an indication if the transaction is an instruction
or a data access
When a transaction contains a mix of
instruction and data items
Its recommended that, by default, an access
is marked as a data access unless specifically
known to be an instruction access
Instruction
Data
Data
Access Signals
Response Signals
Slave-generated errors
Address decode errors
Exclusive Access
Master1
Exclusive Read
Cycle 1
2 3
2 3
Master2
Write
Cycle 2
Master1
Exclusive Write
Cycle 3
2 3