VHDL 1. ver.

7a 1

VHDL1
INTRODUCTION TO VHDL
(VERY-HIGH-SPEED-INTEGRATED-CIRCUITSHARDWARE DESCRIPTION LANGUAGE)

KH WONG (W2 BEGINS)

(Some pictures are obtained from FPGA Express

VHDL Reference Manual, it is accessible from the machines
in the lab at
/programs/Xilinx foundation series/VDHL reference manual)
 VHDL 1. ver.7a 2

You will learn

• Basic structure: the Entity contains two parts
• Entity
• declaration :
• Define the signals to be seen outside externally
• E.g. Connecting pins of a CPU, memory
• Architecture: define the internal operations of the
device
 VHDL 1. ver.7a 3

Resource & references

• Book
• Digital Design: Principles and Practices, 4/E John F. Wakerly,
Prentice Hall.
• High-Speed Digital Design: A Handbook of Black Magic by Howard
W. Johnson and Martin Graham Prentice Hall.
• BOOKBOON (Free text books)
• Online resource , software in the lab.
 VHDL 1. ver.7a 4

Web resource on VHDL (plenty)

• *Courses and tools
• http://equipe.nce.ufrj.br/gabriel/vhdlfpga.html

• VHDL Quick Reference

• http://www.doulos.co.uk/hegv/
 VHDL 1. ver.7a 5

What is an entity?
Overall structure of a VHDL file

Entity

Entity
Library Architecture
declaration
declaration body
 VHDL 1. ver.7a 6

What are they?

A VHDL file
• Library declaration,e.g.IEEE library as follows
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

Entity
Entity declaration

Architecture
Body: defines
Architecture body the processing
 VHDL 1. ver.7a 7

An example
a comparator in VHDL
•
a=[a3,a2,a1,a0]
b=[b3,b2,b1,b0]
equals

VHDL for programmable logic, Skahill, Addison Wesley

a3
a2
a1 b3 The comparator
a0 chip: eqcomp4 Equals
b2 (Equals=1 when a=b)
b1
b0
 VHDL 1. ver.7a 8

Exclusive nor (XNOR)

• Exclusive nor (XNOR)

• When a=b, Output Y = 0
• Otherwise Y =1

a b Output : Y
a
0 0 1
b
0 1 0
1 0 0
1 1 1
 An example of a comparator
1) --the code starts here , “a comment”
Library
2) library IEEE;
declaration
3) use IEEE.std_logic_1164.all;
Entity 4) entity eqcomp4 is
declaration Entity declaration: defines IOs
5) port (a, b: in std_logic_vector(3 downto 0 );
6) equals: out std_logic);
7) end eqcomp4;
8) architecture dataflow1 of eqcomp4 is
Architecture 9) begin
body 10) equals <= '1' when (a = b) else '0’;
Architecture
11) -- “comment” equals is active high Body: defines
12) end dataflow1; the processing

VHDL 1. ver.7a 9
 VHDL 1. ver.7a 10
Entity enclosed by the entity name –
How to read it? eqcomp4 (entered by the user)
•Port defines the I/O pins.

•A bus, use downto to define it.

1) --the code starts here
•E.g. in std_logic_vector(3 downto 0);
2) library IEEE;
3) use IEEE.std_logic_1164.all;
Entity
declaration 4) entity eqcomp4 is
5) port (a, b: in std_logic_vector(3 downto 0 );
6) equals: out std_logic);
7) end eqcomp4;
8) architecture dataflow1 of eqcomp4 is

Architecture 9) begin
body 10) equals <= '1' when (a = b) else '0’;
11) -- “comment” equals is active high
12) end dataflow1;
 VHDL 1. ver.7a 11
Student ID: __________________
Name: ______________________
Date:_______________ Exercise 1.1
(Submit this at the end of the lecture.)
• In the eqcomp4 VHDL • 1 entity eqcomp4 is
code: • 2 port (a, b: in std_logic_vector(3 downto 0
);
• How many Input / Output
pins? • 3 equals: out std_logic);
• Answer: _______ • 4 end eqcomp4;
• 5
• What are their names and
their types? • 6 architecture dataflow1 of eqcomp4 is
• Answer: ___________ • 7 begin
• ___________________ • 8 equals <= '1' when (a = b) else '0’;
• What is the difference • 9-- “comment” equals is active high
between std_logic and • 10 end dataflow1;
std_logic_vector?
• Answer: __________
• __________________
 VHDL 1. ver.7a 12

Entity declaration:
define the IO pins of the chip
• entity eqcomp4 is
• port (a, b:in std_logic_vector(3 downto 0 );
• equals: out std_logic);
• end eqcomp4;
Two input buses (a3,a2,a1,a0) (b3,b2,b1,b0) and one output ‘equals’
a3
a2
a1 b3 The comparator
a0 chip: eqcomp4 equals
b2
b1
b0
 VHDL 1. ver.7a 13

Concept of signals
• A signal is used to carry logic information.
• In hardware it is a wire.
• A signal can be “in” or “out” ..etc.
• There are many logic types of signals (wires)
• Bit (can only have logic 1 or 0)
• Std_logic can be 1, 0 , Z ..etc. ( Z=float.)
• Std_logic_vector is a group of wires (called bus).
• a, b: in std_logic_vector(3 downto 0); in VHDL
• means a(0), a(1), a(2), a(3) are std_logic signals
(meaning• Same for b.
Standard logic,
an IEEE standard)
 VHDL 1. ver.7a 14

Exercise 1.2
• 1 entity test1 is
• 2 port (in1,in2: in std_logic;
• 3 out1: out std_logic) ;
• 4 end test1;
• 5
• 6 architecture test1arch of test1 is
• 7 begin
• 8 out1<= in1 or in2;
• 9 end test1_arch;
• Give line numbers of (i) entity declaration, and (ii) architecture?
Also find an error in the code.
• _____________________________________________
• What are the functions of (i) entity declaration and (ii) architecture?
• _____________________________________________
• Draw the chip and names the pins. (Don’t forget the two most
important pins)
• __________________________________________________
• Underline (or list) the words that are user defined in the above
VHDL code.
• _________________________________________________
 VHDL 1. ver.7a 15

Exercise 1.3
Answer:
• Rewrite code in example
1.2, with
• Entity name is not test1 but
test1x
• Inputs are not in1 and in2 but
a,b, resp.
• Output is not out1 but out1x
• Logic type is not std_logic but
bit
• Architecture name is not
test1arch but x_arch.
 VHDL 1. ver.7a 16

ENTITY DECLARATION
Define Input/Output (IO) pins

Entity

Entity
Library Architecture
declaration
declaration body

IN port declaration
declare modes(
In out, inout, buffer)
 VHDL 1. ver.7a 17

More on Entity Declaration

• entity do_care is port(
• s : in std_logic_vector(1 downto 0);
• y : buffer std_logic);
• end do_care;
• 4 modes of IO pins in port
• in,
• out,
• inout (bidirectional) **User defined variables are in Italic.
• buffer (can be read back by the entity)
 VHDL 1. ver.7a 18

Four modes of IO signals

Example:
entity do_care is port(
• Declared in port s : in std_logic_vector(1 downto 0);
y : buffer std_logic);
declaration end do_care;
4 modes of IO pins in port

IO Signal
Modes in port

Mode: Mode: Mode: Mode:

in out inout buffer
 VHDL 1. ver.7a 19

IN, OUT, INOUT, BUFFER modes

• IN: data flows in, like an input pin
• OUT: data flows out, just like an output. The
output cannot be read back by the entity
• INOUT: bi-directional, used for data lines of a
CPU etc.
• BUFFER: similar to OUT but it can be read back
by the entity. Used for control/address pins of a
CPU etc.
 VHDL 1. ver.7a 20

Exercise 1.4 :
On IO signal modes: IN, OUT, INOUT, BUFFER
• State the difference between out and buffer.
• Answer:_______________________________________
___
• Based on the following schematic, identify the modes of
the IO pins.
A D
From
VHDL for
E programmable
logic,
B F Skahill, Addison Wesley

C
G
 VHDL 1. ver.7a 21

Difference between buffer and inout

• Buffer= it is an output but the output signal
can be read back internally. Note: It cannot act A tri-state buffer
as an input from an external signal.
• Inout: can be input or output at different times
but not at the same time.
• So why E is a buffer, F is an inout? Answer:
• E is signal with mode buffer because Z
• Z=(A and B) drives E and E is an output but also
at the same time X=(B and Z), this Z is feedback x
to the chip driving an internal signal. F cannot
y
act as an input from an external signal.
• F is signal with mode inout because
• If C is 1,X drives F, so F is an output at that time.
• However, when C is 0, F is an input that receives
an input to drive Y at that time.
• Note: F can be ‘in’ or ‘out’ at different times but
not at the same time.
 VHDL 1. ver.7a 22

Entity

Entity
Library Architecture
declaration
declaration Body

THE ARCHITECTURE
BODY

Define the internal architecture/operation

 VHDL 1. ver.7a 23

Architecture body: defines the operation of

the chip
• Begin
• …tells you the internal operation…..
• ……..
• end

• 6 architecture dataflow1 of eqcomp4 is

• 7 begin
Architecture
body •8 equals <= '1' when (a = b) else '0’;
• 9 -- “comment” equals is active high
• 10 end dataflow1;
 VHDL 1. ver.7a 24

How to read it?

• Architecture name -- dataflow1(entered by the user)
• equals, a,b are I/O signal pins designed by the user in the
entity declaration.
• The operation: equals <= '1' when (a = b) else '0’;
• “--” means comment

6 architecture dataflow1 of eqcomp4 is

7 begin
8 equals <= '1' when (a = b) else '0’;
9-- “comment” equals is active high
10 end dataflow1;
 VHDL 1. ver.7a 25

Exercise 1.5: Draw the schematic circuit

1) library IEEE;
2) use IEEE.STD_LOGIC_1164.ALL;
3) entity test2v is
4) port (in1 : in std_logic_vector (2 downto 0);
5) out1 : out std_logic_vector (3 downto 0));
6) end test2v;
7) architecture test_arch of test2v is
8) begin
9) out1(0)<=in1(1);
10) out1(1)<=in1(2);
11) out1(2)<=not (in1(0) and in1(1));
12) out1(3)<='1';
13) end test_arch ;
 26
• Exercise 1.6: Multiple choice question: What is this circuit? (a)
encoder,(b) decoder,(c)multiplexer or (d) adder. Answer:____
• Fill in the truth table of this circuit
• Fill in the blanks of the program listed below for this circuit.
In1 in2 out00 out10 out11 out01

0 0
1 0
1 1
0 1

1 entity test16 is
2 port (in1 , in2: in std_logic;
3 out00,out01,out10,out11 : out std_logic);
4 end test16;
5 architecture test16_arch of test16 is
6 begin
7 out00<=not (_______________________);
8 out10<=not (_______________________);
9 out11<=not (_______________________);
10 out01<=not (_______________________);VHDL 1. ver.7a
11 end test16_arch ;
 VHDL 1. ver.7a 27

Exercise 1.7:
• Write a VHDL program that implement the formula
• F= (/a+b)./c
 VHDL 1. ver.7a 28

Summary
• learned
• Entity
• Entity declaration
• Use of port()
• Modes of IO signals
• Structure of the Architecture body of a simple VHDL program