ADVANCED MICROPROCESSORS

Date: 16/11/2005
Prof. S. Jagannathan,
HOD – Department of Electronics and Communication
Engineering,
R.V. College of Engineering, Bangalore
Contents
• Pin Diagram of 8086
• Pin Details
• Pin Diagram of 8088
• Comparison of 8086 and 8088
8086 Pin diagram

8086 is a 40 pin DIP using

MOS technology. It has 2
GND’s as circuit
complexity demands a
large amount of current
flowing through the
circuits, and multiple
grounds help in dissipating
the accumulated heat etc.
8086 works on two modes
of operation namely,
Maximum Mode and
Minimum Mode.
 Power Connections

GND 1 40 VCC Pin Description:

GND – Pin no. 1, 20
8086 Ground
CLK – Pin no. 19 – Type I
CLK 19
Clock: provides the basic
GND 20
timing for the processor and
bus controller. It is
asymmetric with a 33% duty
cycle to provide optimized
internal timing.
VCC – Pin no. 40
VCC: +5V power supply pin
Address/ Data Lines
AD14 2
39 AD15
AD13 3
AD12 4
AD11 5
AD10 6
AD9 7
AD8 8 8086
AD7 9
AD6 10
AD5 11
AD4 12
AD3 13
AD2 14
AD1 15
AD0 16 Continued…
Pin Description

AD15-AD0 – Pin no. 2-16, 39 – Type I/O

Address Data bus: These lines constitute the time multiplexed

memory/ IO address (T1) and data (T2, T3, TW, T4) bus. A0 is
analogous to BHE* for the lower byte of the data bus, pins D7-
D0. It is low when a byte is to be transferred on the lower portion
of the bus in memory or I/O operations. Eight –bit oriented
devices tied to the lower half would normally use A0 to condition
chip select functions. These lines are active HIGH and float to 3-
state OFF during interrupt acknowledge and local bus “hold
acknowledge”.
Address Lines
A14 2 39 A15
A13 3
A12 4
38 A16
A11 5
A10 6
37 A17
A9 7
A8 8 8086
A7 9 36 A18
A6 10
A5 11 35 A19
A4 12
A3 13
A2 14
A1 15
A0 16
Continued…
A19/S6, A18/S5, A17/S4, A16/S3 – Pin no. 35-38 – Type O

Address / Status: During T1 these are the four most significant

address lines for memory operations. During I/O operations these
lines are low. During memory and I/O operations, status
information is available on these lines during T2, T3, TW and T4.
The status of the interrupt enable FLAG bit (S5) is updated at the
beginning of each CLK cycle. A17/S4 and A16/S3 are encoded as
shown.
Continued…
A17/S4 A16/S3 Characteristic
s
0 (LOW) 0 Alternate Data
0 1 Stack
1(HIGH) 0 Code or None
1 1 Data
S6 is 0information
This (LOW) indicates which relocation register is presently
being used for data accessing.
These lines float to 3-state OFF during local bus “hold
acknowledge”.
Status Pins S0-S7
38 S3
37 S4
36 S5

35 S6

34 S7
8086
28 S2 (M/I O )

27 S1 (DT/ R )

26
S 0 ( DEN )

Continued…
Pin Description

S 2 , S1 , S 0 - Pin no. 26, 27, 28 – Type O

Status: active during T4, T1 and T2 and is returned to the passive

state (1,1,1) during T3 or during TW when READY is HIGH.
This status is used by the 8288 Bus Controller to generate all
memory and I/O access control signals. Any change by , or
during T4 is used to indicate the beginning of a bus cycle and the
return to the passive state in T3 or TW is used to indicate the end
of a bus cycle.

Continued…
These signals float to 3-state OFF in “hold acknowledge”.
These status lines are encoded as shown.
S2* S1* S0* Characteristics
0(LOW) 0 0 Interrupt acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1(HIGH) 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive Continued…
Status Details
S2 S1 S0 Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive Continued…
S4 S3 Indications
0 0 Alternate data
0 1 Stack
1 0 Code or none
1 1 Data

Continued…
S5 ----- Value of Interrupt Enable flag

S6 ----- Always low (logical) indicating 8086 is

on the bus. If it is tristated another bus
master has taken control of the system bus.

S7 ----- Used by 8087 numeric coprocessor to

determine whether the CPU is a 8086 or
8088
Interrupts
Pin Description:
NMI – Pin no. 17 – Type I
8086
Non – Maskable Interrupt: an edge
triggered input which causes a type 2
NMI 17
interrupt. A subroutine is vectored to via
INTR 18 an interrupt vector lookup table located
in system memory. NMI is not maskable
internally by software. A transition from
a LOW to HIGH initiates the interrupt at
the end of the current instruction. This
input is internally synchronized.
Continued…
INTR – Pin No. 18 – Type I
Interrupt Request: is a level triggered input which is sampled
during the last clock cycle of each instruction to determine if the
processor should enter into an interrupt acknowledge operation.
A subroutine is vectored to via an interrupt vector lookup table
located in system memory. It can be internally masked by
software resetting the interrupt enable bit. INTR is internally
synchronized. This signal is active HIGH.
Min mode signals
33 VCC MN/ MX

31 HOLD

30 HLDA
29 WR
28 M/I O
8086
27 DT/ R

26 DEN

25 ALE

24 INTA

Continued…
Pin Description
HOLD, HLDA – Pin no. 31, 30 – Type I/O
HOLD: indicates that another master is requesting a local bus
“hold”. To be acknowledged, HOLD must be active HIGH. The
processor receiving the “hold” request will issue HLDA (HIGH) as
an acknowledgement in the middle of a T1 clock cycle.
Simultaneous with the issuance of HLDA the processor will float
the local bus and control lines. After HOLD is detected as being
LOW, the processor will LOWer the HLDA, and when the
processor needs to run another cycle, it will again drive the local bus
and control lines.
The same rules as apply regarding when the local bus will be
released.
HOLD is not an asynchronous input. External synchronization
should be provided if the system can not otherwise guarantee the
setup time.
Continued…
WR* - Pin no. 29 – Type O
Write: indicates that the processor is performing a write memory or
write I/O cycle, depending on the state of the M/IO* signal. WR* is
active for T2, T3 and TW of any write cycle. It is active LOW, and
floats to 3-state OFF in local bus “hold acknowledge”.

M/IO* - Pin no. 28 – type O

Status line: logically equivalent to S2 in the maximum mode. It is
used to distinguish a memory access from an I/O access. M/IO*
becomes valid in the T4 preceding a bus cycle and remains valid
until the final T4 of the cycle (M=HIGH), IO=LOW). M/IO* floats
to 3-state OFF in local bus “hold acknowledge”.

Continued…
DT/R* - Pin no. 27 – Type O
Data Transmit / Receive: needed in minimum system that desires to
use an 8286/8287 data bus transceiver. It is used to control the
direction of data flow through the transceiver. Logically DT/R* is
equivalent to S1* in the maximum mode, and its timing is the same as
for M/IO*. (T=HIGH, R=LOW). This signal floats to 3-state OFF in
local bus “hold acknowledge”.
DEN* - Pin no. 26 – Type O
Data Enable: provided as an output enable for the 8286/8287 in a
minimum system which uses the transceiver. DEN* is active LOW
during each memory and I/O access and for INTA cycles. For a read
or INTA* cycle it is active from the middle of T2 until the middle of
T4, while for a write cycle it is active from the beginning of T2 until
the middle of T4. DEN* floats to 3-state OFF in local bus “hold
acknowledge”. Continued…
ALE – Pin no. 25 – Type O
Address Latch Enable: provided by the processor to latch the
address into the 8282/8283 address latch. It is a HIGH pulse active
during T1 of any bus cycle. Note that ALE is never floated.

INTA* - Pin no. 24 – Type O

INTA* is used as a read strobe for interrupt acknowledge cycles. It
is active LOW during T2, T3 and TW of each interrupt acknowledge
cycle.
Max mode signals
33 GND
31 RQ/ GT0

30 RQ/ GT1

29 LOCK
28 S2
8086
27 S1

26 S0

25 QS0

24 QS1

Continued…
Pin Description:
RQ*/GT0*, RQ*/GT1* - Pin no. 30, 31 – Type I/O
Request /Grant: pins are used by other local bus masters to force the
processor to release the local bus at the end of the processor’s
current bus cycle. Each pin is bidirectional with RQ*/GT0* having
higher priority than RQ*/GT1*. RQ*/GT* has an internal pull up
resistor so may be left unconnected. The request/grant sequence is as
follows:
Continued…
1. A pulse of 1 CLK wide from another local bus master indicates a
local bus request (“hold”) to the 8086 (pulse 1)
2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the 8086
to the requesting master (pulse 2), indicates that the 8086 has
allowed the local bus to float and that it will enter the “hold
acknowledge” state at the next CLK. The CPU’s bus interface unit
is disconnected logically from the local bus during “hold
acknowledge”.
3. A pulse 1 CLK wide from the requesting master indicates to the
8086 (pulse 3) that the “hold” request is about to end and that the
8086 can reclaim the local bus at the next CLK.
Continued…
Each master-master exchange of the local bus is a sequence of 3
pulses. There must be one dead CLK cycle after each bus exchange.
Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle,
it will release the local bus during T4 of the cycle when all the
following conditions are met:
 Request occurs on or before T2.
 Current cycle is not the low byte of a word (on an odd address)
 Current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
 A locked instruction is not currently executing.

Continued…
LOCK* - Pin no. 29 – Type O
LOCK* : output indicates that other system bus masters are not to gain
control of the system bus while LOCK* is active LOW. The LOCK*
signal is activated by the “LOCK” prefix instruction and remains active
until the completion of the next instruction. This signal is active LOW,
and floats to 3-state OFF in “hold acknowledge”.
QS1, QS0 – Pin no. 24, 25 – Type O
Queue Status: the queue status is valid during the CLK cycle after which
the queue operation is performed.
QS1 and QS0 provide status to allow external tracking of the internal
8086 instruction queue.
Continued…
QS1 QS0 Characteristics
0(LOW) 0 No operation
0 1 First Byte of Op Code from Queue
1 (HIGH) 0 Empty the Queue
1 1 Subsequent byte from Queue
Common Signals

Continued…
Pin Description:

RD* - Pin no. 34, Type O

Read: Read strobe indicates that the processor is performing a memory of I/O read
cycle, depending on the state of the S2 pin. This signal is used to read devices
which reside on the 8086 local bus. RD* is active LOW during T2, T3 and TW of
any read cycle, and is guaranteed to remain HIGH in T2 until the 8086 local bus
has floated.
This signal floats to 3-state OFF in “hold acknowledge”.

READY – Pin no. 22, Type I

READY: is the acknowledgement from the addressed memory or I/O device that
it will complete the data transfer. The READY signal from memory / IO is
synchronized by the 8284A Clock Generator to form READY. This signal is
active HIGH. The 8086 READY input is not synchronized. Correct operation is
not guaranteed if the setup and hold times are not met.
Continued…
TEST* - Pin No 23 – Type I
TEST* : input is examined by the “Wait” instruction. If the TEST* input is LOW
execution continues, otherwise the processor waits in an “idle” state. This input is
synchronized internally during each clock cycle on the leading edge of CLK.

RESET – Pin no. 21 – Type I

Reset: causes the processor to immediately terminate its present activity. The
signal must be active HIGH for at least four clock cycles. It restarts execution, as
described in the instruction set description, when RESET returns LOW. RESET is
internally synchronized.

Continued…
BHE*/S7- Pin No. 34 – Type O
Bus High Enable / Status: During T1 the Bus High Enable signal (BHE*) should
be used to enable data onto the most significant half of the data bus, pins D15-D8.
Eight bit oriented devices tied to the upper half of the bus would normally use
BHE* to condition chip select functions. BHE* is LOW during T1 for read, write,
and interrupt acknowledge cycles when a byte is to be transferred on the high
portion of the bus. The S,7 status information is available during T2, T3 and T4.
The signal is active LOW and floats to 3-state OFF in “hold”. It is LOW during T1
for the first interrupt acknowledge cycle.

BHE* A0 Characteristics
0 0 Whole word
0 1 Upper byte from / to odd address
1 0 Lower byte from / to even address
1 1 None Continued…
MN/MX* - Pin no. 33 – Type - I
Minimum / Maximum: indicates what mode the processor is to
operate in.

If the local bus is idle when the request is made the two possible
events will follow:
 Local bus will be released during the next clock.
 A memory cycle will start within 3 clocks. Now the four
rules
for a currently active memory cycle apply with condition
number 1 already satisfied.
8088 Pin Diagram
Comparison of 8086 and 8088
1. In 8088 we have A15-8, instead of AD15-8 of 8086. this is
because, the 8088 can communicate with the outside world
using only 8 bits o data. However, the registers in 8088 and
8086 are same, and the instruction set is also the same. So,
for word operations, the 8088 has to access information
twice. Thus the execution time is increased in the case of
8088.

Continued…
2. In 8086 pin 28 is assigned for the signal M/IO* in the minimum
mode. But in 8088, this pin is assigned to the signal IO/M* in
the minimum mode. This change has been done in 8088 so that
the signal is compatible with 8085 bus structure.
3. The instruction queue length in the case of 8086 is 6 bytes. The
BIU in 8088 needs more time to fill up the queue a byte at a
time. Thus to prevent overuse of the bus by the BIU, the
instruction queue in 8088 is shortened to 4 bytes.
4. To optimize the working of the queue, the 8086 BIU will fetch a
word into the queue whenever there is a space for a word in the
queue. The 8088 BIU will fetch a byte into the queue whenever
there is space for a byte in the queue. Continued…
5. Pin number 34 of 8086 is BHE*/S7. BHE* is irrelevant for
8088, which can only access 8 bits at a time. Thus pin 34 o
8088 is assigned for the signal SSO*. This pin acts like SO*
status line in the minimum mode of operation. So, in the
minimum mode, DT/R*, IO/M*, and SSO* provide the
complete bus status as shown.

Continued…
IO/M* DT/R* SSO* Bus Cycle
1 0 0 Interrupt
acknowledge
1 0 1 Read I/O port
1 1 0 Write I/O port
1 1 1 Halt
0 0 0 Code Access
0 0 1 Read Memory
0 1 0 Write Memory
0 1 1 Passive Continued…
6. In the maximum mode for 8088 the SSO* (pin 34) signal is
always a 1. In the maximum mode for 8086, the BHE*/S7
(pin 34) will provide BHE* information during the first clock
cycle, and will be 0 during subsequent clock cycles. In
maximum mode, 8087 will monitor this pin to identify the
CPU as a 8088 or a 8086, and accordingly sets its own queue
length to 4 or 6 bytes.