Boundary Scan Logic
Boundary Scan Logic
Boundary Scan Logic
Introduction
• This group, known as the Joint European Test Action Group (JETAG), finally
concluded that the best way to address this problem is to create a serial shift-
register around the boundary of the chip similar to scan design to get I/O
accessibility of the chip.
• Through the efforts of JTAG, the idea of “boundary scan” was formally converted
into a test architecture and a set of associated design rules, which were quickly
approved by the IEEE as a test standard (Std. 1149.1) in 1990.
Principle of Boundary scan
• A memory element is added on each primary
input (input cell) and primary output (output
cell) of a chip is called boundary scan cell.
(TDO)
• parallel unload operation (update)
– Output side
• The captured values of core response in R1 are
parallely unload to the PO’s in the output cells (R1 to
R2 if output cell).
– Input side
• The captured values of PI’s in R1 are parallely passed
into the core logic through R2in the input cells (R1 (TDI)
to core in input cells through R2)
Basic boundary scan cell
• basic universal boundary-scan cell
known BC_1.
interconnect structure
between two devices is
called Extest.
• Parallel-load from driver of
chi1 to sensor of chi2 and
serial-shift-out from sensor
of chip2. Transmitter or Driver:
Update register of output cell(R2)
Receiver or Sensor
Capture register of the input cell(R1)
Intest
• Using the boundary scan
cells(BSC), test the internal
functionality of the device is
called Intest.
• Test1: Verify that the TAP FSM can skip the SHIFT-DR state via
– IDLE -> SELECT-DR -> CAPTURE-DR(load default value 0) -> EXIT1-DR -> PAUSE-DR
• Load BYPASS register(1-bit register) with a logic one (1-bit through TDI) : scan-in 1
• Compare the standard-imposed(previous(default) loaded) value of logic zero in TDO(scan-out 0).
• End shifting in PAUSE-DR state
• Load BYPASS register with a zero(scan-in 0)(Skipping capture-DR state).
• Compare TDO with previous scanned-in value of one(scan-out 1).
• End shifting in PAUSE-DR state
• Test2 : Verify that the TAP FSM can skip the IDLE state between two DR-STATES, via
– PAUSE-DR -> EXIT2-DR -> UPDATE-DR -> SELECT-DR -> CAPTURE-DR -> EXIT1-DR -> PAUSE-DR.
• Load BYPASS register with a logic one.
• Compare BYPASS captured value with the standard-imposed value of logic zero.
• End shifting in IDLE state
• Load IR with BYPASS instruction: 1111111111111111111111111111.
• Load BYPASS register with a logic one.
• Compare BYPASS captured value with the standard-imposed value of logic zero.
• End shifting in PAUSE-DR state
• Load BYPASS register with a zero (Skipping capture-DR state).
• Compare TDO with previous scanned-in value of one.
• End shifting in IDLE state
Where to Place Boundary-Scan Cells?
• Two boundary-scan
cells are required for
tri-state pins:
– One on the output side
– One on the status
control signal into the
output driver amplifier
output
driver control
Application at the Board Level
Testing a boundary scan board
• The first test that should be performed for a PCB test is called the infra-
structure test.
• This test is used to determine whether all the components are installed
correctly.
• This test take-place by using the last two bits of the instruction register
(IR) are always ``01''.