Asynchronous Sequential Circuits
Asynchronous Sequential Circuits
Asynchronous Sequential Circuits
Circuits
Asynch. vs. Synch.
2
Asynch. Sequential Circuit
x1 z1
x2 z2
inputs outputs
Combinational
xn zm
Circuit
y1 Y1
Next
Current y2 Y2
State
State yk Yk
delay
delay
delay
3
Asynch. Sequential Circuit
4
Advantages and Disadvantages
• Advantages:
– Low power
– High performance
– No need for clock
• Disadvantages:
– Complexity of design process
5
Synchronous Moore
Inputs
Machine
Combinational
Memory
logic circuit Output
Elements
{Input decoder} decoder
Outputs
Next state
Present state
State signals
Clock
6
Asynchronous Moore
Inputs
Machine
Combinational
logic circuit Output
{Input decoder} decoder
Outputs
State signals
7
Synchronous Mealy
Inputs Machine
Combinational
Memory
logic circuit Output
Elements
{Input decoder} decoder
Next state
Present state
State signals
Clock
8
Asynchronous Mealy
Inputs Machine
Combinational
logic circuit Output
{Input decoder} decoder
Outputs
State signals
9
• Asynchronous Sequential Circuits
In steady-state
condition, the y's
and the Y's are the
same, but during
transition they are
not.
10
According to how input variables are to be
considered, there are 2 types of asynchronous
circuits:
Fundamental mode circuits
Pulse mode circuits
It assumes that:
Input changes should be spaced by at least t,
the time needed for the circuit to settle into a
stable state following an input change. That is, the
input variables should change only when the
circuit is stable.
Only 1 input variable can change at a given
instant of time. 11
Inputs are levels and not pulses.
Delay lines are used as memory elements.
It assumes that
The input variables are pulses instead of levels.
The width of the pulse is long enough for the
circuit to respond to the input.
The pulse width must not be so long that it is
still present after the new state is reached.
pulses should not occur simultaneously on 2 or
more input lines.
12
Derivation of primitive flow table:
14
TRANSITION TABLE
18
Transition Table
19
Transition Table
The Unstable states,
Y≠y
20
Transition Table
Consider the square for x = 0 and
y = 00. It is stable.
x changes from 0 to 1.
The circuit changes the value of Y
to 01. The state is unstable.
The feedback causes a
change in y to 01. The circuit
reaches stable. 21
Transition Table
In general, if a change in the input
takes the circuit to an unstable
state, y will change until it
reaches a stable state.
22
Flow Table Flow Table
23
FLOW TABLE
24
It is called primitive flow table
Flow Table because it has only one stable
state in each row.
26
27
Prob 2: Design a circuit with inputs A and B to give an
output Z=1 when AB=11 but only if A=1 before B, by
drawing total state diagram, primitive flow table and
output map in which transient state is included
28
29
30
31
32
prob 3: Develop the state diagram and primitive flow
table for a logic system that has two inputs X and Y and
a single output Z, which is to behave in the following
manner.
1.Initially both inputs and outputs are equal to 0.
2.Whenever X=1 and Y=0, the Z becomes 1.
3.Whenever X=0 and Y=1, the Z becomes 0.
4.When X=Y=0 or X=Y=1, the output Z does not
change; it remains in the previous state.
The logic system has edge triggered inputs and the
system change state on the rising edges of the two
inputs. 33
State diagram Inputs
A State
0 Output
B C
0 0
D
E F
0
1 1
34
Primitive Flow Table
Present Next state, output Z for XY inputs
state 00 00 00 00
A A,0 B,0 _,_ C,_
B A,_ B,0 D,_ _,_
C E,_ _,_ F,_ C,1
D _,_ B,_ D,0 C,_
E E, _ B,_ _,_ C,_
F _,_ B,_ F,1 C,_
35
Reduction of Primitive Flow Table
(A ,B,D) S0
(C ,E,F) S1
36
Transition table S0 0 S1 1
F+ = XY’ + FX + FY’
37
0 0 0 X
1 X 1 1
Z = FX + FX’ + XY’
X Y Z
F+ = Z
38
State Diagram
X=1 S0 X=0
S1 S2
X=1 X=0 X=1 X=0
S3 S4 S5 S6
X=1 X=0 X=1 X=0 X=1 X=0 X=1 X=0
39
State Table
Next State
Present State
X=0 X=1
S2 S1
S0
Output O=0 Output O=0
S4 S3
S1 Output O=0 Output O=0
S6 S5
S2
Output O=0 Output O=0
S0 S0
S3
Output O=1 Output O=1
S0 S0
S4
Output O=0 Output O=0
S0 S0
S5
Output O=1 Output O=1
S0 S0 40
S6
Output O=0 Output O=0
Reduced State Table
Next State
Present State
X=0 X=1
S2 S1
S0
Output O=0 Output O=0
S46 S35
S1 Output O=0 Output O=0
S46 S35
S2
Output O=0 Output O=0
S0 S0
S35
Output O=1 Output O=1
S0 S0
S46
Output O=0 Output O=0
41
Minimal State Table
Next State
Present State
X=0 X=1
S12 S12
S0
Output O=0 Output O=0
S46 S35
S12 Output O=0 Output O=0
S0 S0
S35
Output O=1 Output O=1
S0 S0
S46
Output O=0 Output O=0
42
Reduced State Diagram
AB
00
S0
O=0
X=0 X=0
X=0 X=1
X=1
X=1
S12
O=0
X=1 X=0
AB
S35 01 S46
AB AB
11 O=1 O=0 10
43
Revised State Table of State Diagram
44
3 Variable K-Map D1 = A’B
AB
X A’B’ (00) A’B (01) AB (11) AB’ (10)
X’ (0) 0 1 0 0
X (1) 0 1 0 0
45
3 Variable K-Map D0 = A’B’ + XA’
AB
A’B’ (00) A’B (01) AB (11) AB’ (10)
X
X’ (0)
1 0 0 0
X (1)
1 1 0 0
46
Implementation of sequential circuit
using logic gates and D flip-flops
A B
D0 Q0
D Q
D1 Q1
D Q Q’
Q’
Q = AB Clock
47
Problem: Analyze the given fundamental mode
asynchronous sequential circuit given.
48
Solution: The given circuit has 2 input variables I1
and I0 and 1 output variable Z. The circuit has 2
feedback paths which provide inputs to the gates,
creating latching operation necessary to produce a
sequential circuit. The feedback path also
generates the state variables X0 and X1. The next
state for the circuit is determined by both, the
state of the input variables and the state variables.
00 0 0 0 0
01 - - 0 -
11 0 - 1 -
10 - - - -
51
Design Example
Problem: Design a gated latch circuit with two inputs
G (gate) and D (data), and one output Q. Binary
information present at the D input is transferred to
the Q output when G is equal to 1. The Q output will
follow the D input as long as G=1. When G goes to 0,
the information that was present at the D input at
the time the transition occurred is retained at the Q
output. The gated latch is a memory element that
accepts the value after G goes to 0. Once G=0, a
change the value of the output Q. 52
Primitive flow table
A primitive flow table is a flow table with
only one stable state in each row.
Inputs Output
State D G Q comments
a 0 1 0 D =Q because G = 1
b 1 1 1 D =Q because G = 1
c 0 0 0 After state a or d
d 1 0 0 After state c
e 1 0 1 After state b or f
f 0 0 1 After state e 53
The primitive flow table shown has one row for each
state and one column for each input combination.
For eg, state a is stable and the output is 0 when the
input is 01.
This information is entered in the flow table in the
first row and second column.
Similarly, the other 5 stable states together with
their output are entered in the corresponding input
columns.
Since both the inputs are not allowed to change
simultaneously, we can enter dash marks in each row
that differs in 2 or more variables from the input
variables associated with the stable state.
Next it is necessary to find the values for 2 or more
squares in each row.
The unstable state values for the other squares are
determined in a similar manner.
All the outputs associated with unstable states are54
Design Example
Inputs Output
State D G Q
a 0 1 0
b 1 1 1
c 0 0 0
d 1 0 0
e 1 0 1
f 0 0 1
55
Two of more rows in the primitive flow table can be
merged into one row if there are non-conflicting states
Reduction of the
and outputs in each of the columns.
56
Reduction of the
Primitive Flow Table
57
Transition Table and Logic Diagram
58
Circuit With SR Latch
59
Assigning Output to Unstable States
60
Equivalent States
61
Implication table
62
Implication Table
Two states are equivalent if for each possible input,
they give exactly the same output and go to the
same next states or to equivalent next states.
The characteristic of equivalent states is that if
(a,b) imply (c,d) and (c,d) imply (a,b), then both
pairs of states are equivalent.
63
Implication Table Without the
first
Example
B
X1X2
Sn 00 01 11 10 C AF Without the
A D/0 D/0 F/0 A/0 last
D BD
B C/1 D/0 E/1 F/0 AF
C DF
C/1 D/0 E/1 A/0 E DF
D AF
D/0 B/0 A/0 F/0
E C/1 F/0 E/1 A/0 F BD
F D/0 D/0 A/0 F/0
G G DG BG DG
G/0 G/0 A/0 A/0 AF AF AF
H B/1 D/0 E/1 A/0 H BC BC BC
AF DF
S n+1/Zn A B C D E F G
64
Implied Pairs
example B
X1X2
00 01 11 10 C AF
Sn
A D/0 D/0 F/0 A/0 D BD
AF
B C/1 D/0 E/1 F/0 DF
C E DF
C/1 D/0 E/1 A/0 AF
D D/0 B/0 A/0 F/0 F BD
E C/1 F/0 E/1 A/0
F D/0 D/0 A/0 F/0 G DG BG DG
G AF AF AF
G/0 G/0 A/0 A/0
H B/1 D/0 E/1 A/0 H BC BC BC
AF DF
S n+1/Zn A B C D E F G
65
The equivalent states:[A,F]、[B,H]、[B,C]、[C,H]。
Denoted by A Denoted by B
The largest group of equivalent states B
Combined into
C AF [B,C,H]
[A,F], [B,C,H],
[D], [E], [G]
D BD
AF
X1X2 DF
00 01 11 10 E DF
Sn AF
A D/0 D/0 A/0 A/0 F BD
B C/1 D/0 E/1 A/0
G DG BG DG
D D/0 B/0 A/0 A/0 AF AF AF
E B/1 A/0 E/1 A/0 H BC BC BC
AF DF
G G/0 G/0 A/0 A/0
A B C D E F G
S n+1/Zn 66
Reduction of Primitive Flow Table
Reduction of the Flow Table to a Minimum
Number of Rows
Reduce the number of state variables
Reduce the amount of logic required
Reduction Method :
1.Equivalent states can be combined by using
implication table method for completely specified
state tables
2.Compatible rows can be merged for incompletely
specified tables
67
Equivalent States
If c and d are equivalent, then
a and b are equivalent
(a,b) -> (c,d)
68
State Table To Be Reduced
69
Reduced State Table
70
Problem: Obtain the primitive flow table for an
asynchronous circuit that has 2 inputs x, y and 1 output
z. An output z=1 occur only during the input state
xy=01 and then if the input state xy=01 is preceded by
the input sequence xy=01, 00, 10, 00, 10, 00.
State diagram:
71
Primitive flow table:
72
States Machine Design
• Other topics on state machine design
– Equivalent sequential machines
– Incompletely specified machines
– One Hot State Machines
73
Equivalent State Machines
• So far have seen that equivalent states in
the state table of a sequential machine are
equivalent and can be removed.
• How about the equivalence between two
sequential circuits?
– Two sequential circuits are equivalent is they
are capable of doing the same work.
74
Formally
76
Proving equivalence
• Again will use an implication table.
– Only this time it is the full square.
– Along bottom are the state of one machine
– Along the side are the states of the second.
• Start by removing output incompatible
states.
77
Step 2
• Go back through and remove
the implied equivalence pairs
that were Xed on the first
pass. Continue until no
further Xs are entered.
• If there is one square not
Xed in each row and each
column, the state machines
are equivalent.
• Consider problem 15-17
9/2/2012 – ECE 3561 Lect Copyright 2012 - Joanne DeGroat, ECE, OSU 78
10 78
The equivalence implication
table
• X squares where the outputs are
incompatible
• Enter implied equivalence pairs for
remaining states.
79
Incompletely Specified
• Incompletely Specified State Tables
– State tables that contain don’t cares.
– Results in reduced logic
Noncritical Race:
State variables change from 00
to 11. The possible transition
could be
00 11
00 01 11
00 10 11
84
The following diagram illustrates critical
race.
Consider a circuit is in a stable state y1
y2 x=000 and there is a change in input from
0 to 1.
If state variable change simultaneously,
the final stable state is y1 y2 x=111.
If Y2 changes to 1 before Y1 because of
unequal propagation delay, the circuit goes
to stable state 011 and remain there.
On the other hand, if Y1 changes faster
than Y2, then the circuit goes to the stable
state 101 and remain there. Hence the race
is critical because the circuit goes to
85
different stable states depending on the
Race Conditions
Critical Race:
State variables change from 00
to 11. The possible transition
could be
88
The primary objective in choosing a proper binary
state assignment is the prevention of critical races.
89
SHARED ROW METHOD
91
Three-Row Flow-Table Example
00
01
11
00
01
11
10
Note that a2 is
adjacent to d2, c1,
b2.
96
The expanded table is formed by replacing each
row of the original table with 2 rows.
For eg, row b is replaced by rows b1 and b2 and
stable state b is entered in columns 00 and 11 in
both the rows b1 and b2.
After all the stable states have been entered, the
unstable states are filled in by reference to the
assignment specified in the map.
When choosing the next state for a given present
state, a state that is adjacent to the present state is
selected from the map.
In the original table, the next states of b are a and
d for the inputs 10 and 01, respectively.
In the expanded table, the next states for b2 are
a2 and d1 because they are adjacent to b2. 97
Multiple-Row Method
99
Flow table:
State variables State Inputs X1 X2
F4 F3 F2 F1 00 01 11 10
0 0 0 1 A A B C C
0 0 1 0 B A B C D
0 1 0 0 C A B C C
1 0 0 0 D D B C D
4 state variables are used to represent the 4 rows in
the table.
Each row is represented by a case where only one
of the 4 state variables is a 1.
A transition from state A to state B requires 2 state
variable changes; F1 from 1 to 0 and F2 from 0 to 1.
By directing the transition from A to B through a
new row E which contains 1s where both states A and
100
B have 1s.
We require only one state variable change from
transition A to E and then from transition E to B.
This permits the race free transition between A
and B.
In general, we can say that, in row I of the table,
state variable Fi is 1 and all other state variables are
0.
When a transition between row i and j is
required, first state variable Fj is set to 1 and Fi is
set to 0.
Thus each transition between 2 rows in the flow
table goes through one intermediate row.
This permits the race free transition but requires
2 state transitions.
The following table is the complete one hot state
assignment flow table. 101
State variables State Inputs X1 X2
F4 F3 F2 F1 00 01 11 10
0 0 0 1 A A B C C
0 0 1 0 B A B C D
0 1 0 0 C A B C C
1 0 0 0 D D B C D
0 0 1 1 E A B - -
0 1 0 1 F A - C C
0 1 1 0 G - B C -
1 0 1 0 H - B - D
1 1 0 0 I - - C -
103
Hazards
Hazards definition.
Hazards in combinational circuit.
static hazard
dynamic hazard
Hazard free circuit.
Hazards in sequential circuit
Essential hazards
104
Hazards
F1
F2
106
-> Assume that all the three inputs are initially equal to
1.
This causes the output of the gate 1 to be 1, that of
gate 2 to be 0, and the output of the circuit to be equal
to 1.
109
Hazards in Combinational Circuits
110
In the above K-map, the change in x2
from 1 to 0 moves the circuit from minterm
111 to minterm 101. The hazard exists
because the change of input results in a
different product term covering the two min
terms.
Min term 111 is covered by the product
term implemented in gate 2.
whenever the circuit must move from
one product term to another, there is a
possibility of a momentary interval when
neither term is equal to 1, giving rise to an
undesirable 0 output.
111
Eliminating hazards
112
Hazards in Combinational Circuits
113
HAZARD FREE CIRCUIT
114
Hazards in Combinational Circuits
115
Prob: Give hazard-free realization for the
following Boolean function.
f(A,B,C,D)=m(0,2,6,7,8,10,12)
Soln: The given function can be
implemented using K-map.
00 01 11 10 00 01 11 10
00 1 1 00 1 1
01 01
1 1 1 1
11 11
10 1 1
10
1 1 1 1
f= B’D’+A’BC+AC’D’ f= B’D’+A’BC+AC’D’+A’CD’
116
A A’ B B’ C C’ D D’
117
HAZARDS IN SEQUENTIAL
CIRCUITS
118
ESSENTIAL HAZARDS
120
Essential hazards
• A critical race between an input signal
change and a feedback signal change –
may cause an incorrect state transition
• Incorrect behaviour depends upon
specific delays in gates/interconnections
• “If from any stable state, the final state
reached after one change in an input is
different to that reached after three
changes in that input, then an essential
hazard exists”
121
Essential hazards
Starting from PRY1Y2 = 1010
The final state can be 00 or 01
for one or three changes in P
But, depending upon circuit
delays, a single change in P
may cause an incorrect
transition to state 01
122
Essential hazards
123
We can avoid essential hazards in
asynchronous circuits by implementing them using
SR latches.
A momentary 0 signal applied to the S or R
inputs of a NOR latch will have no effect on the
state of the circuit.
Similarly, a momentary 1 signal is applied to the
S and R inputs of a NAND latch will have no effect
on the state of the latch.
Let us consider a NAND SR latch with the
following Boolean function:
S= AB+CD
R= A’C
124
A
B
Q
C
D
A’
C Q’
Y2 D2 y2
x
127
Hardware Description Language -
Introduction
• HDL is a language that describes the hardware of
digital systems in a textual form.
• It resembles a programming language, but is
specifically oriented to describing hardware structures
and behaviors.
• The main difference with the traditional programming
languages is HDL’s representation of extensive
parallel operations whereas traditional ones represents
mostly serial operations.
• The most common use of a HDL is to provide an
alternative to schematics.
128
HDL – Introduction (2)
130
Verilog - Module
• A module is the building block in Verilog.
• It is declared by the keyword module and is always
terminated by the keyword endmodule.
• Each statement is terminated with a semicolon, but
there is no semi-colon after endmodule.
131
Verilog – Module (2)
HDL Example
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y,C);
or g3(x,e,y);
endmodule
132
Verilog – Module (4)
133
Verilog – Module (5)
134
Verilog – Module (7)
Bitwise operators
– Bitwise NOT : ~
– Bitwise AND: &
– Bitwise OR: |
– Bitwise XOR: ^
– Bitwise XNOR: ~^ or ^~
135
Verilog – Module (8)
Boolean Expressions:
• These are specified in Verilog HDL with a
continuous assignment statement consisting of
the keyword assign followed by a Boolean
Expression.
• The earlier circuit can be specified using the
statement:
assign x = (A&B)|~C)
E.g. x = A + BC + B’D
y = B’C + BC’D’
136
Verilog – Module (9)
137
Verilog – Module (10)
138
Verilog – Module (14)
140
4-bit Full Adder
141
4-bit Full Adder
//Gate-level hierarchical description of 4-bit adder
module halfadder (S,C,x,y);
input x,y;
output S,C;
//Instantiate primitive gates
xor (S,x,y);
and (C,x,y);
endmodule
142
4-bit Full Adder
143
2 to 4 Decoder
144
2 to 4 Decoder
145
2-to-4 Line Decoder
146
2-to-4 Line Decoder
147
Three-State Gates
148
Three-State Gates
• Three-state gates have a control input that can place
the gate into a high-impedance state. (symbolized by
z in HDL).
• The bufif1 gate behaves like a normal buffer if
control=1. The output goes to a high-impedance
state z when control=0.
• bufif0 gate behaves in a similar way except that
the high-impedance state occurs when control=1
• Two not gates operate in a similar manner except
that the o/p is the complement of the input when the
gate is not in a high impedance state.
• The gates are instantiated with the statement
– gate name (output, input, control);
149
Three-State Gates
151
Writing a Test Bench (2)
initial begin
A=0; B=0; #10 A=1; #20 A=0; B=1;
end
• The block is enclosed between begin and
end. At time=0, A and B are set to 0. 10
time units later, A is changed to 1. 20 time
units later (at t=30) a is changed to 0 and B
to 1.
152
Writing a Test Bench (2)
153
2-to-4 Line Decoder – Data flow
description
//2-to-4 Line Decoder: Dataflow
module dec_2_to_4_df(E_n,A0,A1,D0_n,D1_n,D2_n,D3_n);
input E_n, A0, A1;
output D0_n,D1_n,D2_n,D3_n;
assign D0_n=~(~E_n&~A1&~A0);
assign D1_n=~(~E_n&~A1& A0);
assign D2_n=~(~E_n& A1&~A0);
assign D3_n=~(~E_n& A1& A0);
endmodule
154
4-to-1 Multiplexer
155
4-to-1 Multiplexer
//4-to-1 Mux: Structural Verilog
module mux_4_to_1_st_v(S,D,Y);
input [1:0]S;
input [3:0]D;
output Y;
wire [1:0]not_s;
wire [0:3]N;
not g0(not_s[0],S[0]),g1(not_s[1],S[1]);
and g2(N[0],not_s[0],not_s[1],D[0]),
g3(N[1],S[0],not_s[1],D[0]),
g4(N[2],not_s[0],S[1],D[0]),
g5(N[3],S[0],S[1],D[0]);
or g5(Y,N[0],N[1],N[2],N[3]);
endmodule
156
4-to-1 Multiplexer – Data Flow
//4-to-1 Mux: Dataflow description
module mux_4_to_1(S,D,Y);
input [1:0]S;
input [3:0]D;
output Y;
assign Y = (~S[1]&~S[0]&D[0])|(~S[1]&S[0]&D[1])
|(S[1]&~S[0]&D[2])|(S[1]&S[0]&D[3]);
endmodule
158
HDL for Sequential Circuits
159
Lecture Outline
• Latches and Flip-flops
• Counters and Registers
160
Gated D Latch
161
D Flip-flop
module D_FF (Q,D,CLK);
output Q;
input D,CLK;
reg Q;
always @ (posedge CLK)
Q = D;
endmodule
162
Testing Flip-flops
• Need to have flip-flop in known state at
start of test
– Add reset input
module DFF (Q,D,CLK,RST);
output Q;
input D,CLK,RST;
reg Q;
always @(posedge CLK or negedge RST)
if (~RST) Q = 1'b0; // Same as: if (RST = 0)
else Q = D;
endmodule
163
T Flip-flop from D type
• Characteristic
Equation
Q( n 1) Q( n ) T
module TFF (Q,T,CLK,RST);
output Q;
input T,CLK,RST;
wire DT;
assign DT = Q ^ T ;
//Instantiate the D flip-flop
DFF TF1 (Q,DT,CLK,RST);
endmodule
164
JK Flip-flop from D type
• Characteristic Q( n1) J .Q( n ) K .Q( n )
Equation
module JKFF (Q,J,K,CLK,RST);
output Q;
input J,K,CLK,RST;
wire JK;
assign JK = (J & ~Q) | (~K & Q);
//Instantiate D flipflop
DFF JK1 (Q,JK,CLK,RST);
endmodule
165
Ripple Counter
module ripplecounter(count, reset, A0, A1, A2, A3
input count;
input reset;
output A0, A1, A2, A3;
166
T Flip-flop
module TFF (T,RST,Q);
input T, RST;
output Q;
reg Q;
always @(negedge T or posedge RST) begin
if (RST) begin
Q = 1'b0;
end
else begin
#2 Q = ~Q;
end
end
endmodule
167
Binary Counter
module counter (Count,Load,IN,CLK,Clr,A,CO);
input Count,Load,CLK,Clr;
input [3:0] IN; //Data input
output CO; //Output carry
output [3:0] A; //Data output
reg [3:0] A;
assign CO = Count & ~Load & (A == 4'b1111);
always @ (posedge CLK or negedge Clr)
if (~Clr) A = 4'b0000;
else if (Load) A = IN;
else if (Count) A = A + 1'b1;
else A = A; // no change
endmodule
168