Data Representation and Computer

Arithmetic
 Data Representation
Binary

Fixed Point Octal

Instructions

Numeric Decimal
Information

Floating Point

Data
Hexa Decimal

Non Numeric
 Integer /Fixed point representations
• There are 4 commonly known (1 uncommon) integer representations.
• All have been used at various times for various reasons.
• unsigned
• sign magnitude
• one's complement
• two's complement
• biased (not commonly known)

• Question: virtually all modern computers operate based on 2's complement

representation. why?
• hardware is faster
• hardware is simpler (which makes it faster)
 Unsigned Representation
• In general, if an n-bit sequence of binary digits an-1an-2 . . . a1a0 is interpreted as
an unsigned integer A, its value is

• Range: 0 to 2n – 1 for n bits

• Ex: 0 to 15 for 4 bits
(n=4, 24 -1 is 15)
 Sign magnitude Representation
• The simplest form of representation that employs a sign bit is the sign-
magnitude representation.
• In an n-bit word, the rightmost bits hold the magnitude of the integer.
• The most significant (leftmost) bit in the word as a sign bit.
• Sign bit = 0 => positive
• Sign bit = 1 => negative.
• Ex: + 18 = 00010010; - 18 = 10010010
• Range: -2n-1 + 1 to 2n-1 – 1
• To get the additive inverse of a number, just flip (not, invert, complement,
negate) the sign bit.
 Sign magnitude representation
• The general case can be expressed as follows:

• Drawbacks
• Addition and subtraction require a consideration of both the signs of the
numbers and their relative magnitudes to carry out the required operation.
• There are two representations of 0
 1’s Complement Representation
• Historically important, and we use this representation to get 2's complement integers
• In the past, early computers built by Semour Cray (while at CDC) were based on 1's
comp. integers.
• Positive integers use the same representation as unsigned; 00000 is 0; 00111 is 7;
• Negation (finding an additive inverse) is done by taking a bit wise complement of the
positive representation.
• EXAMPLES: 11100 (This must be a negative number)
• 00011 is +3, so 11100 must be -3
• Things to notice:
• Any negative number will have a 1 in the MSB.
• There are 2 representations for 0; 00000 and 11111.
 2’s Complement
• The most significant bit represents a sign of the number
• Range: -2n-1 through 2n-1 - 1
• Number of Representations of Zero: One
• Negation: Take the Boolean complement of each bit of the corresponding
positive number, then add 1 to the resulting bit pattern viewed as an unsigned
integer.
• Expansion of Bit Length: Add additional bit positions to the left and fill in with
the value of the original sign bit.
• Overflow Rule: If two numbers with the same sign (both positive or both
negative) are added, then overflow occurs if and only if the result has the
opposite sign.
 Pros and cons of integer representation
• Signed magnitude representation:
• 2 representations for 0
• Simple
• 255 different numbers can be represented.
• Need to consider both sign and magnitude in arithmetic
• Different logic for addition and subtraction
• 1’s complement representation:
• 2 representations for 0
• Complexity in performing addition and subtraction
• 255 different numbers can be represented.
• 2’s complement representation:
• Only one representation for 0
• 256 different numbers can be represented.
• Arithmetic works easily
 2’s Complement Subtraction
• Represent negative numbers in 2’s complement form
• Subtract the given two numbers
• Take 2’s complement of subtrahend (second number) and add to the
minuend (first number)
• If carry
• Discard it
• Answer is positive
• Else
• Answer is negative
• So, answer is in 2’s complement form
 Overflow
• Overflow in unsigned addition – result occupies more number of bits.
• Overflow in signed-magnitude / 2’s complement addition
• result occupies more number of bits
• addition of two positive number resulting negative number
• sum of two negative numbers resulting in positive number.
• There will no overflow during unsigned subtraction / signed – magnitude
subtraction.
• Overflow bit in 2’s complement subtraction is ignored
 Overflow / Underflow Problem
• Overflow – when the addition of two binary numbers yields a result that is
greater than the maximum possible value
• Underflow – when the addition/subtraction of two binary numbers yields a
result that is less than the minimum possible value
Overflow Underflow
• Assume 4-bit restriction and 2’s complement • Assume 4-bit restriction and 2’s complement
• Maximum possible value: 24-1 – 1 = 7 • Minimum possible value: -(24-1) = -8

610 + 310 = 910 -510 + -510 = -1010

01102 610 10112 -510

+00112 +310 +10112 +-510
10012 -710  not good! 01102 610  not good!
Overflow of Signed Numbers

carry generated, carry and

but no overflow overflow

no carry and no carry and

no overflow overflow

Cin Cout = 1 => Overflow

2’s Complement Addition and Subtraction
Hardware Flowchart
 Problem
• Perform the arithmetic operations below with binary
numbers and with negative numbers in signed 2’s
complement representation. Use seven bits to accommodate
each number together with its sign. In each case, determine if
there is an overflow by checking the carries into and out of
the sign bit position
(+35) + (+40)
(-35) + (-40)
(-35) – (+40)
 Multiplication - Unsigned
• Using paper – pencil method

• Inferences
• Multiplication involves the generation of partial products, one for each digit in the
multiplier. These partial products are then summed to produce the final product.
• The partial products are easily defined. When the multiplier bit is 0, the partial
product is 0. When the multiplier is 1, the partial product is the multiplicand.
• The total product is produced by summing the partial products. For this
operation, each successive partial product is shifted one position to the left
relative to the preceding partial product.
• The multiplication of two n-bit binary integers results in a product of up to bits in
length (e.g., ).
Comparison of Multiplication of Unsigned and Twos
Complement Integers
• We have seen that addition and subtraction can be performed on numbers in
twos complement notation by treating them as unsigned integers.
• Unfortunately, this simple scheme will not work for multiplication.
• Ex: Multiply 11 (1011) by 13 (1101) to get 143 (10001111).
• If we interpret these as twos complement numbers, we have -5 (1011) times -3
(1101) equals -113 (10001111).
• This example demonstrates that straightforward multiplication will not work if
both the multiplicand and multiplier are negative.
• In fact, it will not work if either the multiplicand or the multiplier is negative
Comparison of Multiplication of Unsigned and Twos
Complement Integers

Unsigned integers Twos complement integers

 Booth’s Multiplication Algorithm
M X (00011110) = M X (24 + 23 +22 + 21)
= M X (16 + 8 + 4 + 2)
= M X 30
The number of operations can be reduced to two if we observe that:
2n + 2n-1 + …. + 2n-k = 2n+1 – 2n-k
M X (00011110) = M X (25 - 21)
= M X (32 - 2)
= M X 30

14 = 01110 = 24 – 21 25 = 011001 = -20 + 21 – 23 + 25 = -1 + 2 – 8 + 32

= 16 – 2 = 1 – 8 + 32 = -7 + 32
Booth’s Multiplication Advantage
Serial addition Booth algorithm
00010100 20 00010100 20
×00011110 30 ×00011110 30
00000000
00010100 111111111101100
00010100
00010100
00010100
00000000 00000010100
00000000
00000000________ __________________
000001001011000 600 0000001001011000 600
Four partial product additions Two partial product additions
Hardware for Booth’s Multiplication
 Description and Algorithm for Booth Multiplication
Description Algorithm

Q - multiplier Do Count times

Q0 - least significant bit of QR Q0Q-1 = 10
Q-1 - previous least significant bit of A←A+M+1
QR Q0Q-1 = 01
M - multiplicand A←A+M
A-0 Arithmetic shift right A, Q, Q-1
Count - number of bits in multiplier Count ← Count – 1
Booth Multiplier Recording Table

Multiplier Version of Multiplicand

Bit i Bit i - 1 selected by bit i
0 0 0xM
0 1 +1 x M
1 0 -1 x M
1 1 0xM
Booth’s Multiplication Algorithm – Flow Chart
Example: -9 × -13 = 117
M = 10111, M + 1 = 01001

Comment A Q Q -1 SC
00000 10011 0 5
Subtract M 01001
01001
Ashr 00100 11001 1 4
Ashr 00010 01100 1 3
Add M 10111
11001
Ashr 11100 10110 0 2
Ashr 11110 01011 0 1
Subtract M 01001
00111
Ashr 00011 10101 1 0
 Exercise
• Show the step by step multiplication process using Booth
algorithm when the following binary numbers are multiplied.
Assume 5-bit registers that hold signed numbers. The
multiplicand in both cases is +15.
(+15) × (+13)
(+15) × (-13)
 Modified Booth’s Algorithm
• Guarantees that the maximum number of summands that must be added is
n/2 for n-bit operands.
• Bit pair recording technique
• Observe the following:
• The pair (+1, -1) is equivalent to the pair (0, +1)
• (+1, 0) is equivalent to (0, +2)
• (-1, +1) is equivalent to (0, -1)
• Examines 3 bits at a time.
 Modified Booth’s Algorithm

101101 101101 101101 101101

× -1 1 × -1 × 1 -1 × 1
1101101 010011 0010011 101101
010011 101101
10010011 0010011 1101101 1101101
 Modified Booth’s Algorithm

101101 101101 101101 101101

× 1 0 × +2 × -1 0 × -2
0000000 1011010 0000000 0100110
101101 010011
1011010 1011010 0100110 0100110
Table of Multiplicand and Selection decisions
Multiplier Bit-Pair Multiplier Booths Represenation Multiplicand selected at
i+1 i bit on the position i
right i –
1
0 0 0 0 0 0xM
0 0 1 0 1 +1xM
0 1 0 1 -1 +1 x M
0 1 1 1 0 +2xM
1 0 0 -1 0 -2xM
1 0 1 -1 1 -1xM
1 1 0 0 -1 -1 x M
1 1 1 0 0 0xM
Multiplication requiring only n/2 summands
Modified Booth’s Multiplication - Example
Example: -9 × -13 = 117
M = 110111, M + 1 = 001001

Comment A Q Q -1 SC
000000 110011 0 3
Subtract M 001001
001001
Ashr 000100 111001 1
Ashr 000010 011100 1 2
Add M 110111
111001
Ashr 111100 101110 0
Ashr 111110 010111 0 1
Subtract M 001001
000111
Ashr 000011 101011 1
Ashr 000001 110101 1 0
The EBCDIC character code, shown with hexadecimal
indices
The EBCDIC control character representation
 References
Text Book
• William Stallings “Computer Organization and architecture”
Prentice Hall, 7th edition, 2006
• Carl Hamacher, Zvonko Vranesic, Sofwat Zaky, “Computer
Organization”, 5th edition, Mc Graw Hill.
• http://courses.cs.tamu.edu/rabi/cpsc321/lectures/lec06.ppt