Lectures On Computer Arithmetic: Unit 7

Lectures on
Computer Arithmetic
UNIT 7
Addition and Subtraction of Signed
Magnitude Numbers
Addition and Subtraction :
Hardware Algorithm
 The two signs A, and B are compared by an exclusive-  The magnitudes are subtracted by adding A to the 2's
OR gate. If the output of the gate is 0, the signs are complement of B. No overflow can occur if the
identical; if it is I, the signs are different numbers are subtracted so AVF is cleared to 0.
 The magnitudes are added with a micro operation EA  A 1 in E indicates that A > B and the number in A is the
A + B. correct result. If this number is zero, the sign A, must
 where EA is a register that combines E: and A. The be made positive to avoid a negative zero.
carry in E: after the addition constitutes an overflow if  A 0 in E: indicates that A < B. For this case it is
it is equal to 1. necessary to take the 2's complement of the value in A.
 The value of E: is transferred into the add-overflow This operation can be done with one micro operation A
flip-flop AVF. A’+ 1 .
Flow Chart
Addition &
Subtraction with
signed
magnitude data
Multiplication Algorithms
 The multiplier is stored in the Q register and its sign in

Qs
 The sequence counter SC is initially set to a number
equal to the number of bits in the multiplier.
 The counter is decremented by 1 after forming each
partial product. When the content of the counter
reaches zero, the product is formed and the process
stops.
 Initially, the multiplicand is in register B and the Multiplication Hardware
multiplier in Q.
The sum of A and B forms a partial product which is transferred to the EA register. both partial
product and multiplier are shifted to the right. This shift will be denoted by the statement shr EAQ to
designate the right shift depicted in Figure
Hardware Multiplication
Algorithm
 Figure is a flowchart of the hardware multiply
algorithm. Initially, the multiplicand is in B and the
multiplier in Q.
 Their corresponding signs are in Bs and Qs,
respectively. The signs are compared, and both A and Q
are set to correspond to the sign of the product since a
double-length product will be stored in registers A and
Q.
 Registers A and E are cleared and the sequence counter
SC is set to a number equal to the number of bits of the
multiplier.
Booth Multiplication Algorithm for Signed 2's
complement Numbers
 Booth algorithm gives a procedure for multiplying binary  As in all multiplication schemes, Booth algorithm requires
integers in signed-2's complement representation. examination of the multiplier bits and shifting of the partial
 It operates on the fact that strings of 0's in the multiplier product. Prior to the shifting, the multiplicand may be added
require no addition but just shifting, and a string of 1's in the to the partial product, subtracted from the partial product, or
left unchanged according to the following rules:
multiplier from bit weight 2k to weight 2m can be treated as
(2k+1 – 2m ) 1. The multiplicand is subtracted from the partial product
 For example, the binary number 001110 ( + 14) has a string upon encountering the first least significant 1 in a string of
of 1's from 23 to 21(k = 3, m = 1). The number can be 1's in the multiplier.
represented as 2k+1 - 2m = 24 - 21 = 16 – 2 = 14. 2. The multiplicand is added to the partial product upon
 Therefore, the multiplication M x 14, where M is the encountering the first 0 (provided that there was a previous
multiplicand and 14 the multiplier, can be done as M x 24 - M 1) in a string of 0's in the multiplier.
X 21 . 3. The partial product does not change when the multiplier bit
 Thus the product can be obtained by shifting the binary is identical to the previous multiplier bit.
multiplicand M four times to the left and subtracting M
shifted left once.
Booth Multiplication Algorithm for Signed 2's
complement Numbers
 The algorithm works for positive or negative

multipliers in 2's complement representation.
 This is because a negative multiplier ends with a
string of 1's and the last operation will be a
subtraction of the appropriate weight.
 For example, a multiplier equal to -14 is
represented in 2's complement as 110010 and is
treated as - 24 + 22 - 21 = -14.
 The hardware implementation of Booth algorithm
requires the register configuration shown in
Figure.
Booth Multiplication
Algorithm for Signed 2's
complement Numbers
 The flowchart for Booth algorithm is shown in Figure. AC and the appended bit Qn+1 are
initially cleared to 0 and the sequence counter SC is set to a number n equal to the
number of bits in the multiplier.
 The two bits of the multiplier in Qn and Qn+1 1 are inspected.
 If the two bits are equal to 10, it means that the first 1 in a string of 1' s has been
encountered. This requires a subtraction of the multiplicand from the partial product in
AC .
 If the two bits are equal to 01, it means that the first 0 in a string of 0' s has been
encountered. This requires the addition of the multiplicand to the partial product in AC .
 When the two bits are equal, the partial product does not change. An overflow cannot
occur because the addition and subtraction of the multiplicand follow each other.
 As a consequence, the two numbers that are added always have opposite signs, a
condition that excludes an overflow. The next step is to shift right the partial product and
the multiplier (including bit Qn+1). This is an arithmetic shift right (ashr) operation which
shifts AC and QR to the right and leaves the sign bit in AC unchanged
 The sequence counter is decremented and the computational loop is repeated n times.
Example :
 A numerical example of Booth algorithm is shown

in Table for n = 5.
 It shows the step-by-step multiplication of ( - 9) x
( - 13) = + 117.
 Note that the multiplier in QR is negative and that
the multiplicand in BR is also negative.
 The 10-bit product appears in AC and QR and is
positive.
 The final value of Qn+1 is the original sign bit of the
multiplier and should not be taken as part of the
product.
2 bit by 2 bit Array Multiplier
 The multiplication of two binary

numbers can be done with one micro
operation by means of a combinational
circuit that forms the product bits all at
once.
 This is a fast way of multiplying two
numbers since all it takes is the time for
the signals to propagate through the
gates that form the multiplication array
Division Flowchart
 The hardware divide algorithm is shown in the flowchart

of Figure.
 The dividend is in A and Q and the divisor in B . The
sign of the result is transferred into Q, to be part of the
quotient. A constant is set into the sequence counter SC to
specify the number of bits in the quotient.
 A divide-overflow condition is tested by subtracting the
divisor in B from half of the bits of the dividend stored in
A . If A>B, the divide-overflow flip-flop DVF is set and
the operation is terminated prematurely.
 If A < B, no divide overflow occurs so the value of the
dividend is restored by adding B to A .
Division Flowchart
Cont..
 The division of the magnitudes starts by shifting the dividend
in AQ to the left with the high-order bit shifted into E.
 If the bit shifted into E is 1, we know that EA > B because
EA consists of a 1 followed by n - 1 bits while B consists of
only n -1 bits. In this case, B must be subtracted from EA
and 1 inserted into Q, for the quotient bit.
 If E = 0, it signifies that A < B and the original number is
restored by adding B to A .
 Since register A is missing the high-order bit of the dividend
(which is in E), its value is EA - 2n-1. Adding to this value the
2' s complement of B results in EA-B.
 The carry from this addition is not transferred to E if we want
E to remain a l .
Example:
 Divisor (B) = 17 & Dividend (AQ)= 448

 Quotient (Q) = 26 & Remainder = 6
 SC=5 (5-bit)
Floating Point Basic
 A floating point number in computer registers consists  Arithmetic operations with floating-point
of two parts: a mantissa m and an exponent e. numbers are more complicated than with fixed-
 The two parts represent a number obtained from point numbers and their execution takes longer
multiplying m times a radix r raised to the value of e; and requires more complex hardware.
thus m x re.  Adding or subtracting two numbers requires first
 The mantissa may be a fraction or an integer. The an alignment of the radix point since the
location of the radix point and the value of the radix exponent parts must be made equal before
r are assumed and are not included in the registers. adding or subtracting the mantissas.
 For example, assume a fraction representation and a  The alignment is done by shifting one mantissa
radix 10. The decimal number 537.25 is represented in
a register with m = 53725 and e = 3 and is interpreted while its exponent is adjusted until it is equal to
to represent the floating-point number .53725 X 103 the other exponent.
Multiplication Algorithm
for 2 Floating
Point Numbers
 The flowchart for floating-point multiplication is shown in Figure.
 The two operands are checked to determine if they contain a zero. If either
operand is equal to zero, the product in the AC is set to zero and the
operation is terminated.
 If neither of the operands is equal to zero, the process continues with the
exponent addition. The exponent of the multiplier is in q and the adder is
between exponents a and b.
 It is necessary to transfer the exponents from q to a, add the two
exponents, and transfer the sum into a . Since both exponents are biased
by the addition of a constant, the exponent sum will have double this bias.
The correct biased exponent for the product is obtained by subtracting
the bias number from the sum.
 The multiplication of the mantissas is done as in the fixed-point case with
the product residing in A and Q . Overflow cannot occur during
multiplication, so there is no need to check for it.
BCD adder Revisited
O/p:
S8,S4,S2,S1 & Carry Out
Decimal Arithmetic Operations
Questions can be asked
 Draw and explain flowchart for addition and subtraction operations with sign-magnitude data.
 Draw flowchart hardware multiplication algorithm and explain it.
 Explain Booth multiplication algorithm for multiplying binary integers in signed 2’s
complement representation.
 Draw flow chart for multiplication of two floating point numbers.
 Explain BCD Adder with its block diagram
 Draw the block diagram of 4-bit arithmetic circuit and explain it in detail.
 Assume A = (+8) and B = (+5). Multiply these two numbers using Booth algorithm. Show the
step-by-step multiplication process.
THANK you
 Read Chapter 10 from

Questions?
“Computer System
Architecture” 3rd Edition By M.
Morris Mano

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Lectures on

 The multiplier is stored in the Q register and its sign in

 The algorithm works for positive or negative

 A numerical example of Booth algorithm is shown

 The multiplication of two binary

 The hardware divide algorithm is shown in the flowchart

 Divisor (B) = 17 & Dividend (AQ)= 448

 Read Chapter 10 from

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