Introduction: Introduction to IC

Technology
Unit I
G.L.SumaLata
Assistant Professor,GRIET
 CMOS Background
• CMOS: high noise immunity
low static power
high density
smaller feature size
Can be fabricated with few defects and low cost.
3D Perspective

Polysilicon Aluminum

3
 Process steps:
• Silicon crystal growth
• Wafer cleaning
• Oxidation
• Photolithography
• Diffusion
• Ion implantation
• Dry etching, Wet etching , plasma etching
• Thermal treatments
• Chemical vapour deposition , Physical vapour deposition
• Molecular beam epitaxy
• Electrochemical deposition
• Metallization
• Planarization
• Wafer testing , mounting
• Die cutting
• Encapsulation
Semiconductor Fabrication
Processes
• Front-End Processing (Wafer fabrication)
• Back-End Processing (Assembly and
Testing)
 Basic MOS Fabrication Process
• Semiconductor technology is based on certain well established
process steps:
• Silicon crystal growth: Czochralski method
 Oxidation – oxide growth or oxidation.
 Diffusion – movement of impurity from surface into bulk.
 Ion Implantation – ions of a dopant are accelerated by electric
field and physically lodged within semiconductor.
 Etching – removing exposed, unprotected material.
 Photolithography – selection of specific parts of the silicon
wafer for fabrication processes is photolithography.
 Metallization to make contact
 Packaging
Fabrication starts with a single crystalline silicon wafer.
 Wafer manufacture
• Silicon: most abundant element
• Silica (impure SiO2)
• Wafer: circular base, ultrapure , defect free slices of single
crystalline silicon.
• Ingot : cylindrical single crystal semiconductor from the
Czochralski crystal growth process.
• Process: Silicon refinement
Crystal growth
Wafer formation
Growing the Silicon Ingot
• Most common technique is
the Czochralski (CZ)
– Length: up to 2 m
– Diameter: 200 mm (8”) to
300 mm (12”)
– Weight: Over 225 kg.
– Pulling takes up to hundred
hours

From Smithsonian, 2000

9
 Czochralski (CZ) Method : crystal puller
1420 C

Develop by Mitsubishi in the 50’s

• Crystal orientation is determined by seed orientation

• Ingot diameter is determined by temperature, orientation,
and extraction speed.
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 Crystal Growth : Czochralski Method
• 98% pure polycrystalline metallurgical grade Si subjected to
high temperature chemical in electrode-arc furnace.
• Apparatus – crystal puller
• Polycrystalline silicon is placed in crucible.
• Furnace is heated above melting temp. of si.
• Dopant impurity— may be added to molten intrinsic silicon
• A seed crystal mounted on a rod is dipped in molten silicon,
and pulled upwards and rotated at the same time.
• temperature, rate of pulling , speed of rotation are under
control.
• The cylindrical ingot can be extracted from the melt.
• Process is done in an inert atmosphere(argon) in inert
material(quartz)
Wafer Shaping
Ingot is cut around and ground down
into a uniform diameter (8”-12”), then
sliced into wafers of about 1 mm thick.

Wire Saw Machine

Qu i c k T i m e ™ a n d a T IF F ( Un c o m p re s s e d ) d e c o m p r e s s o r a re n e e d e d t o s e e th i s p ic t u r e .

The sliced wafers are mechanically

lapped by the use of alumina abrasive
material to remove surface roughness
and damages caused by the saw cut
and to improve the flatness of the wafer.
Qu i c k T i m e ™ a n d a T IF F ( Un c o m p re s s e d ) d e c o m p r e s s o r a re n e e d e d t o s e e th i s p ic t u r e .

Lapping Machine

12
Wafer Shaping (2)
Mechanical damages induced during
the previous processes are removed
by chemical etching.

The mechano-chemical polishing

process improves the flatness of the
wafer, making highly flat surface by
the use of colloidal silica.

Wafer Polishers
Qu i c k T i m e ™ a n d a T IF F ( Un c o m p re s s e d ) d e c o m p r e s s o r a re n e e d e d t o s e e th i s p ic t u r e .

13
Planarization: Polishing the Wafers

liquid carrier with a

suspended abrasive
component such as
aluminum oxide or
silica

From Smithsonian, 2000

CMP (Chemical-Mechanical Planarization) - Essential to keep the

surface of the wafer approximately flat between processing steps.
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 Wafer Fabrication
• A high-purity, single-crystal silicon called
"99.999999999% (eleven-nine)" is grown from a
seed to an ingot.
• The wafers are generally available in diameters of
150 mm, 200 mm, or 300 mm, and are mirror-
polished and rinsed before shipment from the
wafer manufacturer.
Crystal and wafer

A polished wafer
 Preparation of Silicon Wafers
Polysilicon Seed crystal
6. Edge Rounding
Crucible
1. Crystal Growth

Heater

7. Lapping

2. Single Crystal Ingot

8. Wafer Etching

3. Crystal Trimming and

Diameter Grind
Polishing
Slurry head

9. Polishong
4. Flat Grinding
Polishing table

5. Wafer Slicing 10. Wafer Inspection

 Growing and deposition of dielectric films

• Necessity of dielectric films:

• Physical protection of the sample and underlying
devices : SiO2 layer protect semiconductor devices and
surface from contamination ,scratches during fabrication
process .
• Avoid contamination from electrically active
contaminants (mobile ionic contaminants) of the
electrically active surface.
• SiO2 on Si wafer block the dopants from reaching Si
surface. All dopants have slower rate of movement in
SiO2 compared to Si.
 Process Step - Oxidation
• Oxidation: A layer of Silicon-di-Oxide is grown on Silicon wafer
surface.
• Typically about 56% of the oxide thickness tOX is above the
original surface and 44% below it.
• Growth by dry or wet technique, dry growth has lower defect
densities.
• Oxide thickness varies from < 150 Ao for Gate oxides to >10000
Ao for field oxides.
• Oxidation temperature varies between 700 to 1100 oC.

tOX SiO2 0.44 tOX

Si Substrate
The simplest method of producing an oxide layer consists of heating a silicon wafer
in an oxidizing atmosphere.
 Oxidation : comparison
Dry oxidation Wet oxidation
• Dry atmosphere. • Water steam.
• Oxide layers are very • Si (s) + 2H20 (l) SiO2 (s)
uniform. +2H2 (g)
• Si (s) + O2 (g) SiO2 (s) • Wet oxide grows fast.
• Relatively few defects exist • Useful to grow a thick layer
at the oxide-silicon. of field oxide
• Dry oxide grows very slowly.
• It is required to form thin
oxide layer.
 Oxide Growth/Oxide Deposition
• Oxidation of the silicon surface
creates a SiO2 layer that acts as
an insulator.
• Oxide layers are also used to
isolate metal interconnections.

An annealing step is required to

restore the crystal structure after
thermal oxidation.

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 Chemical vapour deposition
• Where thermal process not possible.
• High purity
• Performance lower than thermal.
• Source of silicon dioxide 
silane
Dichloro silane
nitrous oxide
Lithography area in clean room
 Photolithography
• An IC consists of
several layers of
material that are
manufactured in
successive steps.

 Photolithography is used to selectively process the

layers, where the 2-D mask geometry is copied on the
surface.

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 Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2 (d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2

(b) After oxidation and deposition Hardened resist

of negative photoresist SiO
2
Si-substrate
UV-light
Patterned (e) After etching
optical mask

Exposed resist
SiO
2

Si-substrate Si-substrate

(f) Final result after removal of resist

(c) Stepper exposure

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 Basic Steps of Photolithography

1. Surface Preparation
2. Photoresist Application
3. Soft Bake
4. Align & Expose*
5. Develop
6. Hard Bake
7. Inspection
8. Etch
9. Resist Strip
10. Final Inspection
* Some processes may include a Post-exposure Bake
• Positive photoresist: The UV light • Negative photoresist: Exposure to the UV
changes the chemical structure of light causes the negative resist to become
the resist so that it becomes more polymerized, and more difficult to
soluble in the developer. dissolve.
Basic
lithography
process flow-
chapter-5

29
30
 Wafer Exposure Systems

• Contact printing is capable of high resolution but has unacceptable defect densities.
Inexpensive.
• Proximity printing cannot easily print features below a few m . Poor resolution due to
diffraction.
• Projection printing provides high resolution and low defect densities and dominates
today.

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 Wafer Exposure Systems

electronic
computer
interface

Stepper E-Beam Lithography 32

Etching
 Pattern Transfer–Etching
Isotropic etching Anisotropic etching

photoresist photoresist

SiO 2 SiO 2

(1) (1)

photoresist photoresist

SiO 2 SiO 2

(2) (2)

SiO 2 SiO 2

(3) (3)

(a) Isotropic wet etching (b) Anisotropic dry etching.

Diffusion Process, Ion Implantation
Methods :
• Diffusion • Ion Implantation
• A uniformly doped ingot is
sliced into wafers. • A particle accelerator is used to
accelerate a doping atom so
• An oxide film is then grown on
the wafers. that it can penetrate a silicon
crystal to a depth of several
• The film is patterned and
etched using photolithography microns
exposing specific sections of • Lattice damage to the crystal is
the silicon. then repaired by heating the
• The wafers are then spun with wafer at a moderate
an opposite polarity doping temperature for a few minutes.
source adhering only to the
exposed areas. This process is called
annealing.
• The wafers are then heated in
a furnace (800-1250 deg.C) to
drive the doping atoms into
the silicon.
 Comparison of Diffusion and Ion Implantation

• Diffusion is a cheaper and more simplistic method, but can

only be performed from the surface of the wafers. Dopants
also diffuse unevenly, and interact with each other altering
the diffusion rate.

• Ion implantation is more expensive and complex. It does not

require high temperatures and also allows for greater
control of dopant concentration and profile. It is an
anisotropic process and therefore does not spread the
dopant implant as much as diffusion. This aids in the
manufacture of self-aligned structures which greatly
improve the performance of MOS transistors.
 Heat treatment
• Operations in which the wafer is heated
and cooled to obtain two specific
outcomes, “annealing” and “alloying”.
• Annealing is the repair of a wafer’s crystal
structure after ion implant has disrupted it.
• Alloying is heat treating the wafer after
metal deposition to ensure good electrical
conduction.
 Metallization
• Important metals
• Aluminum
• Copper
• Tungsten
• Silver, Gold
 Issues in VLSI Metallization
 Speed: switching speed, RC delay
 Intensity: electromigration (I), electric breakdown (V)
 Stability: contact interface, stable I-V characteristics
 Voltage drop: IR drop reduces voltage on transistor
 Area: connection wires have to be narrow as device
density increases
Multilevel interconnections
 Metallization : some problems.

• Early ICs used pure Al as the interconnect material

• Low resistivity
• Strong adhesion with Si

• Problems with pure Al

• Junction spiking
• Electro migration:Transfer of momentum from electrons to
the positive metal ions.It happens in short channels devices.

Later ICs used Al alloyed with Cu

 Electro migration Effects
Metal wires have limited current handling capability.

Void Pile-up
Junction spiking
 Encapsulation (Package Types)

45
 Packaging
• Housing of a semiconductor chip.
• Protects and preserves the performance of
semiconductor from electrical mechanical
chemical corruption.
• Package : plastic, ceramic, laminate
• PCB: printed circuit board.
• PTH(pin through hole)
• SMT(surface mount technology)
Structure of a typical package
• Steps:
• Die/chip attaching on PCB
• Bonding
• Encapsulation.
• Testing : wafer level testing
(burn in)
 Package structure

• Package body is physical/thermal support for

chip.
• Cavity holds chip.
• Leads in package connect to pads, provide
substrate connection to chip.
• Some packages: DIP: dual in-line package
PLCC: plastic leadless chip carrier,
PGA: pin grid array
 Some packages

DIP
PGA

PLCC
 Probe testing
• Wafer sort or probe test:
• Performed before wafer is scribed (cut into
chips).
• Test site characterization is also performed
during probe testing.
• Test structures are tested to characterize the
technology including gate threshold, poly,
sheet resistance, etc.
Probe Testing Equipment
Nmos fabrication
Nmos fabrication contd
Fabrication steps for NMOS
 CMOS
Fabrication
 Objectives
• To discussed the fundamentals of
CMOS fabrication steps.
• To examined the major steps of the
process flow.
• To overview the cross section view of
a circuit
 Introduction
MOSFET

NMOS PMOS CMOS

 MOSFET

Gate

Drain Source

Metal Oxide Semiconductor Field Effect Transistor

Source (Arsenic, Phosphorous, Boron)

Drain (Arsenic, Phosphorous, Boron)

Gate (Aluminum, Polysilicon)

 NMOS

P-type substrate

N-type dopant for Source & Drain

Inversion layer is formed to conduct electricity

 NMOS

P-type substrate

N-type dopant for Source & Drain

Inversion layer is formed to conduct electricity

 PMOS

N-type substrate

P-type dopant for Source & Drain

Inversion layer is formed to conduct electricity

 PMOS

N-type substrate

P-type dopant for Source & Drain

Inversion layer is formed to conduct electricity

 CMOS

A combination of both NMOS & PMOS technology

Most basic example: inverter

PROCESS FLOW
WELL FORMATION

ISOLATION FORMATION

TRANSISTOR MAKING

INTERCONNECTION

PASSIVATION
CMOS FABRICATION PROCESS
interconnection

• Photo and etching processes to

pattern interconnection
 Latchup
 Latchup: positive feedback leading to VDD – GND short
– Major problem for 1970’s CMOS processes before
it was well understood
 Avoid by minimizing resistance of body to GND / VDD
– Use plenty ofAsubstrate and well taps
GND VDD
Y

Rwell Vwell
p+ n+ n+ p+ p+ n+

n well Rwell
p substrate n well
Rsub Vwell
Vsub Rsub

substrate tap Vsub

well tap

CMOS VLSI Design

 Latch-Up and its Prevention

• Latch is the generation of a low-

impedance path in CMOS chips
between the power supply and the
ground rails due to interaction of
parasitic pnp and npn bipolar
transistors. These BJTs for a
silicon-controlled rectifier with
positive feedback and virtually
short circuit the power and the
ground rail.
• This causes excessive current flows
and potential permanent damage to
the devices.
• Analysis of the a CMOS Inverter
CMOS depicting the parasitics.
 Guard Rings
 Latchup risk greatest when diffusion-to-substrate
diodes could become forward-biased
 Surround sensitive region with guard ring to collect
injected charge

CMOS VLSI Design

 A’
A

Metal 1
oxide
n+ n+ p+ p+
N-well

p-substrate
 GLOSSARY
• Photolithography (photo)
– Process of transferring pattern on mask to photoresist layer on wafer
surface (pre-pattern the chip)
• Etching
– Process of permanently removed the unwanted part of design on wafer
surface to get the desired pattern
• Diffusion
– Process of introducing dophant layer by movement of dophant atoms
from high concentration to low concentration area at high temperature
• Ion implantation
– Process of introducing dophant layer by bombardment of high energy
dophant ion in high electric field chamber
• Oxidation
– Process of growing thick or thin SiO2 layer depend on oxide application
• CMP
– Process to physically grind flat to have a planar surface for better
exposure at photo process.
 Advantages of n well process

• n-well CMOS are superior to p-well because of

lower substrate bias effects on transistor threshold
voltage.
Lower parasitic capacitances associated with source
and drain region.
Latch- up problems can be considerably reduced by
using a low resistivity epitaxial p-type substrate.
However n-well process degrades the performance of
poorly performing p-type transistor.
 P well process
• The fabrication of p-well CMOS process is similar to
n-well process except that p-wells acts as substrate
for the n-devices within the parent n-substrate.
• P-well processes are preferred in circumstances
where the characteristics of the n- and p-transistors
are required to be more balanced than that
achievable in an n-well process. Because the
transistor that resides in the native substrate tends
to have better characteristic, the p-well process has
better p-devices than an n-well process.
• CMOS p well process is a high temperature diffusion
process(1100C – 1250C). In that respect NMOS
technology is still in current use.
 Latchup
 Latchup: positive feedback leading to VDD – GND short
– Major problem for 1970’s CMOS processes before
it was well understood
 Avoid by minimizing resistance of body to GND / VDD
– Use plenty ofAsubstrate and well taps
GND VDD
Y

Rwell Vwell
p+ n+ n+ p+ p+ n+

n well Rwell
p substrate n well
Rsub Vwell
Vsub Rsub

substrate tap Vsub

well tap

CMOS VLSI Design Slide 78

 Guard Rings
 Latchup risk greatest when diffusion-to-substrate
diodes could become forward-biased
 Surround sensitive region with guard ring to collect
injected charge

CMOS VLSI Design

Twin well process
The starting material is
either an n+ or p+ substrate
with a lightly doped
epitaxial layer, which is
used for protection against
latch up .
 Silicon on Insulator(SOI)
• A thin film(7 – 8micro meter)of very lightly
doped ntype silicon is grown over
insulator(sapphire or sio2).
 Advantages of SOI
• Due to absence of wells,transistor structures denser than bulk silicon are
feasible.
• Lower substrate capacitances provide the possibility for faster circuits.
• No field inversion problems exist(insulating substrate).
• No latchup because of isolation of n and p transistors by the insulating
substrate.
• No body effect problems as there is no conducting substrate.
• Enhanced radiation tolerance.
Disadvantages:
• Kink effect(absence of backside substrate contact due to which drain
current raises)
• Cost more as single crystal sapphire expensive than si substrate.
• Processing techniques complex
 Fabrication of passive components.

• Resistors
• Diffused Resistor : (50- 10kΩ). This can be formed during base
or emitter diffusion of a BJT.
• Pinched resistors: variation to the diffused resistor that is used
to increase the sheet resistivity of the base region.
• Epitaxial resistors: around 5kΩm sheet resistance. This layer
has higher resistivity than other layers.
• MOS resistors: MOSFET can be biased to provide a non linear
resistor. Better than diffused resistor, occupies less area.
Resistance depends on aspect ratio.
• Thin film resistor: A resistive thin film can be deposited
(sputtering) on the substrate.
Capacitors :

• Junction capacitors: It is formed when a pn junction is

reversed biased. Capacitance depends on the reverse
voltage.
base –emitter junction (highest capacitance per
unit) around 1000pf/mm2.
base –collector junction – 100pf/mm2
• MOS capacitors: across thin oxide.(around
1000pf/mm2), voltage independent. At Breakdown
siO2 fails permanently.
BiCMOS fabrication steps
BICMOS STRUCTURE

NMOS PMOS NPN-BJT

S G D S G D C B E

N-Diff N-Diff P-Diff P-Diff N-Plus

Emitter

N-Well (Collector)
P-EPITAXY
N Plus Buried Layer
P-SUBSTRATE
P-SUBSTRATE IS TAKEN

P-SUBSTRATE

P-TYPE SUBSTRATE IS COVERED WITH OXIDE LAYER

P-SUBSTRATE
A WINDOW IS OPENED THROUGH OXIDE LAYER

P-SUBSTRATE

THROUGH THE WINDOW N TYPE IMPURITIES IS HEAVILY DOPED

N Plus Buried Layer

P-SUBSTRATE
P-EPITAXY LAYER IS GROWN ON THE ENTIRE SURFACE

P-EPITAXY

N Plus Buried Layer

P-SUBSTRATE
THE ENTIRE SURFACE IS COVERED WITH OXIDE LAYER AND TWO WINDOWS
ARE OPENED THROUGH THE OXIDE LAYER

P-EPITAXY

N Plus Buried Layer

P-SUBSTRATE
THROUGH THE TWO WINDOWS N-TYPE IMPURITIES ARE DIFFUSED TO
FORM N-WELLS

N-Well
N-Well (Collector)
P-EPITAXY
N Plus Buried Layer
P-SUBSTRATE
THREE WINDOWS ARE OPENED THROUGH THE OXIDE LAYER , IN THESE
THREE WINDOWS THREE ACTIVE DEVICES NMOS,PMOS AND NPN BJT
ARE FORMED

N-Well
N-Well (Collector)
P-EPITAXY
N Plus Buried Layer
P-SUBSTRATE
THE ENTIRE SURFACE IS COVERED WITH THINOX AND POLYSILICON
AND ARE PATTERNED TO FORM THE GATE TERMINALS OF THE NMOS
AND PMOS

N-Well
N-Well (Collector)
P-EPITAXY
N Plus Buried Layer
P-SUBSTRATE
THROUGH THE 3RD WINDOW THE P-IMPURITIES ARE MODERATELY
DOPED TO FORM THE BASE TERMINAL OF BJT
N-WELL ACTS LIKE THE COLLECTOR TERMINAL

N-Well P-Base
N-Well (Collector)
P-EPITAXY
N Plus Buried Layer
P-SUBSTRATE
THE N-TYPE IMPURITES ARE HEAVILY DOPED TO FORM

1.SOURCE AND DRAIN REGION OF NMOS

2.EMITTER TERMINAL OF BJT
3.AND INTO NWELL COLLECTOR REGION FOR CONTACT PURPOSE

N-Diff N-Diff N-Plus

Emitter

N-Well P-Base
N-Well (Collector)
P-EPITAXY
N Plus Buried Layer
P-SUBSTRATE
THE P-TYPE IMPURITES ARE HEAVILY DOPED TO FORM

1.SOURCE AND DRAIN REGION OF PMOS

2.AND INTO P-BASE REGION FOR CONTACT PURPOSE

N-Diff N-Diff P-Diff P-Diff N-Plus

Emitter

N-Well P-Base
N-Well (Collector)
P-EPITAXY
N Plus Buried Layer
P-SUBSTRATE
THE ENTIRE SURFACE IS COVERED WITH THICK OXIDE LAYER

N-Diff N-Diff P-Diff P-Diff N-Plus

Emitter

N-Well P-Base
N-Well (Collector)
P-EPITAXY
N Plus Buried Layer
P-SUBSTRATE
THE ENTIRE SURFACE IS COVERED WITH THICK OXIDE LAYER AND IS
PATTERNED FOR CONTACT CUTS

N-Diff N-Diff P-Diff P-Diff N-Plus

Emitter

N-Well P-Base
N-Well (Collector)
P-EPITAXY
N Plus Buried Layer
P-SUBSTRATE
METAL CONTACTS ARE FORMED

NMOS PMOS NPN-BJT

S G D S G D C B E

N-Diff N-Diff P-Diff P-Diff N-Plus

Emitter

N-Well (Collector)
P-EPITAXY
N Plus Buried Layer
P-SUBSTRATE