Chapter 2 - Silicon Wafer Manufacturing

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EMT 357/3

FUNDAMENTAL OF
MICROELECTRONIC FABRICATION

Chapter 2
Single Crystal Silicon
Wafer
Manufacturing

INEE 2
Objectives

1. Give two reasons why silicon dominate


2. List at least two wafer orientations
3. List the basic steps from sand to wafer
4. Describe the CZ and FZ methods
5. Explain the purpose of epitaxial silicon
6. Describe the epi-silicon deposition process

INEE 3
Why Single Crystal Material?

 Single crystal Si wafers the most commonly used


semiconductor material in IC manufacturing.

 In the original form, most solid materials exist in the


form of amorphous or polycrystalline structures.

 To make an industrial standard transistor, a single


crystal semi-conductor substrate is required.

This is due to the scattering of electron from the grain


boundary can seriously affect the p-n junction
characteristics.
INEE 4
Why Silicon?

 Abundant, 26% earth crust’s is silicon.


One of the most abundant element on
earth.

 Can form a very stable and strong


oxide and easy to grow.

 Larger band gap (compared to Ge),


can tolerate a higher operation
temperature, wider impurity range and
higher breakdown voltage.

INEE 5
`
Crystal Structure
 Atomic structure of a single crystal Si unit cell
 Crystal orientations are defined in Miller Indexes.
<100> plane has a
square shape

MOS IC

<111> plane is
triangular

Bipolar IC
The subcell of the single-crystal silicon and IC Chips
lattice structure.
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ORIENTATION ETCH PITS
CRYSTAL ORIENTATION
PLANE i.E KOH

<100>

<111>

<110>
Crystal Defects

 Vacancy – missing atom from crystal lattice


 Interstitial defect – extra atom in between normal lattice
 Frenkel defect – vacancy and interstitial in pair
 Dislocation – geometric fault
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Dislocation Defects

Defects on the silicon surface can scatter electrons,


which increases resistivity and affects the device performance.
Defects on the wafer surface can reduce production yield of IC chips.

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From Sand to Wafer
From Sand to Wafer (Crude Silicon)

 1st step: Crude Silicon or MGS


(metallurgical grade silicon)
(~ 99% poly-crystal silicon)

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From Sand to Wafer (Silicon Purification)

2nd step: High Purity TCS Formation (Trichlorosilane, SiHCl3)


 MGS grinded into powder
 MGS powder react with HCL to form TCS
 TCS is purified up to 99.9999999%

Heat (300°C)
Si + 3 HCL ---------> SiHCL3 + H2
MGS Hydrochloride TCS Hydrogen

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From Sand to Wafer (Silicon Purification)

 3rd step: EGS (Electronic Grade Silicon) Formation – polycrystal form

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From Sand to Wafer (Crystal Pulling)

 4th Step: Crystal Pulling

 EGS to be heated at high temperature and pulled using


single-Crystal silicon seed.

 2 methods;
 Czochralski (CZ) Method – larger diameter, lower cost, in
situ doping.

 Floating Zone (FZ) Method

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From Sand to Wafer

 CZ (Czochralski) Method

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CZ Crystal Pullers

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From Sand to Wafer
 CZ Method

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From Sand to Wafer
 FZ Method

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FZ and CZ comparison

CZ method is more popular


Cheaper
Larger wafer size (300 mm in production)
Reusable materials

Floating Zone
Pure silicon crystal (no crucible)
More expensive, smaller wafer size (150 mm)
Mainly for power devices
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From Sand to Wafer
 5th Step: Ingot Polishing and Wafer Sawing

 Ingot polishing to remove the grooves created during pulling


 Wafer slicing

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From Sand to Wafer

Typical Wafer Parameters

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From Sand to Wafer
 6th Step: Wafer Finishing

•Edge Polished
•Lapping
•Polished
•Process Control

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From Sand to Wafer

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From Sand to Wafer

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From Sand to Wafer

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From Sand to Wafer

Follow with post-CMP processes with a mixture of acid-oxidizer solutions to


remove organic and inorganic contaminants and particles.

Commonly used clean solution  mixture of hydrochloride acid (HCL) and


hydrogen peroxide (H2O2), and a mixture of sulfuric acid (H2SO4) and H2O2

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Epitaxy: Definition

Epitaxy
Greek origin
epi : upon
Taxy: orderly, arranged

Epitaxial layer is a single crystal layer on a single


crystal substrate.

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Epitaxy: Purpose

Barrier layer for bipolar transistor


 Reduce collector resistance while keep high
breakdown voltage.
 Only available with epitaxy layer.

Improve device performance for CMOS and DRAM


because much lower oxygen, carbon concentration
than the wafer crystal.

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Types of Epi-layer

Homoepitaxy is a kind of epitaxy performed with only one material, in


which a crystalline film is grown on a substrate or film of the same
material. This technology is used to grow a film which is more pure than
the substrate and to fabricate layers having different doping levels. In
academic literature, homoepitaxy is often abbreviated to "homoepi".

Heteroepitaxy is a kind of epitaxy performed with materials that are


different from each other. In heteroepitaxy, a crystalline film grows on
a crystalline substrate or film of a different material. This technology is
often used to grow crystalline films of materials for which crystals
cannot otherwise be obtained and to fabricate integrated crystalline
layers of different materials. Examples include silicon on
sapphire, gallium nitride (GaN) on sapphire, aluminium gallium indium
phosphide (AlGaInP) on gallium arsenide (GaAs) ordiamond or iridium.

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Types of Epi-layer
Heterotopotaxy is a process similar to heteroepitaxy except that thin
film growth is not limited to two-dimensional growth; the substrate is
similar only in structure to the thin-film material.

Pendeo-epitaxy is a process in which the heteroepitaxial film is growing


vertically and laterally at the same time.
Epitaxy is used in silicon-based manufacturing processes for bipolar
junction transistors (BJTs) and modern complementary metal–oxide–
semiconductors (CMOS), but it is particularly important for compound
semiconductors such as gallium arsenide. Manufacturing issues include
control of the amount and uniformity of the deposition's resistivity and
thickness, the cleanliness and purity of the surface and the chamber
atmosphere, the prevention of the typically much more highly doped
substrate wafer's diffusion of dopant to the new layers, imperfections of
the growth process, and protecting the surfaces during the manufacture
and handling.

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Epitaxial Wafer (Bipolar)

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Epitaxial Wafer (CMOS)

Epitaxial:
• The most expensive process step, ~ USD 20 -100 per step
compared to USD 1 per step for other process.
• Two methods i.e. CVD epitaxy and Molecular Beam
Epitaxy Process
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Summary
• Silicon is an inexpensive semiconductor material and silicon
dioxide is easy to grow and strong, stable dielectric.
• The most commonly used silicon crystal orientations are <1 0 0>
and <1 1 1>
• The wafer fabrication process converts sand (silicon dioxide) to
MGS, MGS to TCS, TCS to EGS, EGS to single-crystal silicon
ingot, and ingot to wafer.
• Both CZ and Floating Zone methods are used for wafer
manufacturing, with the CZ method being the more widely used.
• The CZ method is cheaper and can produce larger wafer size.
• The FZ method can produce wafers with higher purity.
• The epitaxial silicon layer is needed for bipolar devices and can
improve performance for CMOS and DRAM.

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References
References:
1. Hong Xiao (2001). Introduction to Semiconductor Manufacturing Technology.
Prentice Hall.
2. Previous Semester’s Lecture Slide

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