Chapter 2 - Silicon Wafer Manufacturing
Chapter 2 - Silicon Wafer Manufacturing
Chapter 2 - Silicon Wafer Manufacturing
FUNDAMENTAL OF
MICROELECTRONIC FABRICATION
Chapter 2
Single Crystal Silicon
Wafer
Manufacturing
INEE 2
Objectives
INEE 3
Why Single Crystal Material?
INEE 5
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Crystal Structure
Atomic structure of a single crystal Si unit cell
Crystal orientations are defined in Miller Indexes.
<100> plane has a
square shape
MOS IC
<111> plane is
triangular
Bipolar IC
The subcell of the single-crystal silicon and IC Chips
lattice structure.
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ORIENTATION ETCH PITS
CRYSTAL ORIENTATION
PLANE i.E KOH
<100>
<111>
<110>
Crystal Defects
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From Sand to Wafer
From Sand to Wafer (Crude Silicon)
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From Sand to Wafer (Silicon Purification)
Heat (300°C)
Si + 3 HCL ---------> SiHCL3 + H2
MGS Hydrochloride TCS Hydrogen
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From Sand to Wafer (Silicon Purification)
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From Sand to Wafer (Crystal Pulling)
2 methods;
Czochralski (CZ) Method – larger diameter, lower cost, in
situ doping.
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From Sand to Wafer
CZ (Czochralski) Method
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CZ Crystal Pullers
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From Sand to Wafer
CZ Method
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From Sand to Wafer
FZ Method
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FZ and CZ comparison
Floating Zone
Pure silicon crystal (no crucible)
More expensive, smaller wafer size (150 mm)
Mainly for power devices
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From Sand to Wafer
5th Step: Ingot Polishing and Wafer Sawing
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From Sand to Wafer
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From Sand to Wafer
6th Step: Wafer Finishing
•Edge Polished
•Lapping
•Polished
•Process Control
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From Sand to Wafer
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From Sand to Wafer
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From Sand to Wafer
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From Sand to Wafer
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Epitaxy: Definition
Epitaxy
Greek origin
epi : upon
Taxy: orderly, arranged
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Epitaxy: Purpose
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Types of Epi-layer
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Types of Epi-layer
Heterotopotaxy is a process similar to heteroepitaxy except that thin
film growth is not limited to two-dimensional growth; the substrate is
similar only in structure to the thin-film material.
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Epitaxial Wafer (Bipolar)
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Epitaxial Wafer (CMOS)
Epitaxial:
• The most expensive process step, ~ USD 20 -100 per step
compared to USD 1 per step for other process.
• Two methods i.e. CVD epitaxy and Molecular Beam
Epitaxy Process
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Summary
• Silicon is an inexpensive semiconductor material and silicon
dioxide is easy to grow and strong, stable dielectric.
• The most commonly used silicon crystal orientations are <1 0 0>
and <1 1 1>
• The wafer fabrication process converts sand (silicon dioxide) to
MGS, MGS to TCS, TCS to EGS, EGS to single-crystal silicon
ingot, and ingot to wafer.
• Both CZ and Floating Zone methods are used for wafer
manufacturing, with the CZ method being the more widely used.
• The CZ method is cheaper and can produce larger wafer size.
• The FZ method can produce wafers with higher purity.
• The epitaxial silicon layer is needed for bipolar devices and can
improve performance for CMOS and DRAM.
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References
References:
1. Hong Xiao (2001). Introduction to Semiconductor Manufacturing Technology.
Prentice Hall.
2. Previous Semester’s Lecture Slide
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