23 Canlas Melson Ziolo P

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Multilevel Memories

Cache & Virtual Memory


Locality of Reference
Cost and Performance
Canlas, Melson Ziolo P.
Multilevel Memories
• A memory system containing at least two memory
subsystem with different capacity and access time.
• Consider a general n-level system of n memory types.
Examples of n = 2, 3, and 4 are shown.
• To achieve a good trade-off between cost, storage
capacity, and performance for the memory system.
The Memory Hierarchy

Register • Higher Storage Capacity


Cache
Level • Increase Access Time
Main Memory
• Lower Cost per Bit
Magnetic Disk
Optical Disk or Magnetic Tape
Two-Level Hierarchy
I: Instruction Flow
D: Data Flow
I
I

CPU Main Secondary


memory D
memory
D

𝑀1
𝑀2

Fig. 6.21 (a)


Three-Level Hierarchy
I: Instruction Flow
D: Data Flow

I I I
I-cache Main Secondary
CPU memory memory
D-cache D
D
D

𝑀1 𝑀2 𝑀3

Fig. 6.21 (b)


Four-Level Hierarchy
I: Instruction Flow
D: Data Flow

I I I I
Level 1 Level 2
Main Secondary
CPU Cache Cache memory
memory
D D D D
𝑀1 𝑀2

𝑀3 𝑀4

Fig. 6.21 (c)


Virtual Memory
• It increases the available memory of your computer by enlarging the
address space using hard disk space for additional memory allocation

Image Source: https://www.webopedia.com/TERM/V/virtual_memory.html


Virtual Memory
• It takes the program addresses and maps them to RAM addresses
32-bit program address space (4GB) 30-bit RAM address space (1GB)
0 Program 0 Program 1 0
1 Program 1 Program 0 1
2 Program 2 Program 2 ….
MAP
3 Program 3
….

DISK
Virtual Memory
• It takes the program addresses and maps them to RAM addresses
32-bit program address space (4GB) 30-bit RAM address space (1GB)
0 Program 0 Program 1 0
1 Program 1 Program 3 1
2 Program 2 Program 2 ….
MAP
3 Program 3
….

DISK
Program 0
Reasons for using Virtual Memory
• To free user programs from the need to carry out storage
allocation
• To make programs independent of the configuration and
capacity of physical memory.
• To achieve low access time and cost per bit
Locality of Reference
• Refers to a phenomenon in which a computer program
tends to access the same set of memory locations for a
particular time period
• The predictability of memory addresses depends on a
characteristic program called locality of reference.
Temporal Locality
Recently referenced items are likely to be referenced again in
the near future

D/I
sum =0;
for (i = 0; i < n; i++)
sum += a[i];
return sum;
Spatial Locality
• Items with nearby addresses tend to be referenced close
together in time

D/I D/I +1

sum =0;
for (i = 0; i < n; i++)
sum += a[i];
return sum;
Locality of Reference
Machine Language Assembly Language
Location Instruction ;680X0 program for vector addition
0100 2078 07D1 MOVE.L A+1000,A0 ;Set pointer beyond end
of A
0104 2278 0BB9 MOVE.L B+1000,A1 ;Set pointer beyond end
of B
0108 2478 0FA1 MOVE.L C+1000,A2 ;Set pointer beyond end
of C
010C C308 START ABCD -(A0),-(A1) ;Decrement pointers
and Add
010E 1511 MOVE.B (A1),-(A2) ;Store Result in C

0110 B0F8 03E9 CMPA A,A0 ;Test for termination

0114 66F6 BNE START Branch to START if Z


not equal to 1
Figure 6.22 Code Fragment illustrating locality of reference
Cost and Performance
• The main goal is to achieve a performance close
to that of the fastest device M1 and cost per bit
of cheapest device Mn
Cost: Two-level Hierarchy

𝒄𝟏 𝑺𝟏 +𝒄𝟐 𝑺𝟐
𝒄= (eq. 6.4)
𝑺𝟏 +𝑺𝟐

Wherein
c: avg. cost per bit
𝑐𝑖 : cost per bit of 𝑀𝑖
𝑆𝑖 : Storage capacity (bits) of 𝑀𝑖
Performance: Two-level Hierarchy
• Hit Ratio
• Access Time
• Efficiency
Performance: Two-level Hierarchy
𝑵𝟏
𝑯= (eq. 6.5) 𝒕𝑨 = 𝒕𝑨𝟏 + 𝟏 − 𝑯 𝒕𝑩 (eq 6.7)
𝑵𝟏 +𝑵𝟐

H - Hit ratio 𝒕𝑨 : Average access time


𝑵𝒊 − Address reference satisfied my 𝑴𝒊 H: Hit ratio
𝒕𝑨𝟏 : Access time of memory 𝑀1

𝒕𝑩 :Block Transfer in case of miss scenario


Performance: Two-level Hierarchy
𝒕𝑨𝟐
𝒓= ; 𝒕𝑨𝟐 ≈ 𝒕𝑩
𝒕𝑨𝟏

𝟏
𝒆= eq 6.7
𝒓+ 𝟏 −𝑯 𝑯

H: Hit ratio
e: Efficiency
𝒓: access time ratio of the 2 memories (𝑡𝐵 / 𝑡𝐴 )
Performance: Two-level Hierarchy

Fig. 6.23 : Access efficiency e = 𝑡𝐴1 / 𝑡𝐴 of a 2-level memory as a function of


hit ratio H for various values of r = 𝑡𝐴2 /𝑡𝐴1

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