Scribd Logo
Upload

Welcome to Scribd!

  • 19 views

    Unit - 4 - 1 Introduction To Sequential Circuits and Latches

    Uploaded by

    Vamsipriya G
    The document discusses sequential circuits including latches and flip-flops. It covers the basics of synchronous and asynchronous sequential circuits. Specific topics covered include SR latches using NAND and NOR gates, D latches, and the use of enable signals with latches.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    Unit - 4 - 1 Introduction To Sequential Circuits and Latches

    Uploaded by

    Vamsipriya G
    19 views16 pages
    The document discusses sequential circuits including latches and flip-flops. It covers the basics of synchronous and asynchronous sequential circuits. Specific topics covered include SR latches using NAND and NOR gates, D latches, and the use of enable signals with latches.

    Original Title

    Unit_4_1 Introduction to Sequential Circuits and Latches

    Copyright

    © © All Rights Reserved

    Available Formats

    PPTX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document discusses sequential circuits including latches and flip-flops. It covers the basics of synchronous and asynchronous sequential circuits. Specific topics covered include SR latches using NAND and NOR gates, D latches, and the use of enable signals with latches.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    19 views16 pages

    Unit - 4 - 1 Introduction To Sequential Circuits and Latches

    Uploaded by

    Vamsipriya G
    The document discusses sequential circuits including latches and flip-flops. It covers the basics of synchronous and asynchronous sequential circuits. Specific topics covered include SR latches using NAND and NOR gates, D latches, and the use of enable signals with latches.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 16

    Unit-4

    Sequential Circuits
    Contents
     Introduction to Sequential Circuits
     Latches, Flip‐Flops
     RS- Latch Using NAND and NOR Gates
     Truth Tables
     RS, JK, T and D Flip Flops
     Truth and Excitation Tables
     Conversion of Flip Flops
    Introduction to Sequential circuits
    A sequential circuit is specified by a time sequence of inputs,
    outputs, and internal states
     Contain memory elements.
     The outputs are a function of the current inputs and the state of
    the memory elements.
     The outputs also depend on past outputs.

    Figure 3.2 Block diagram of Sequential Circuit


    Types of Sequential Circuits

    • There are two types of sequential circuits are available. They


    are
    Synchronous Sequential Circuits.

    Asynchronous Sequential Circuits.


    Synchronous Sequential Circuits

    • The outputs of a sequential circuit


    depend on not only the inputs, but
    also the state, or the current contents
    of some memory.
    • The memory contents can also
    change as the circuit runs, so the
    order in which things occur makes a
    difference.
    • The clock signal allows inputs, to
    process and generates outputs.
    Latches

    • SR Latch using NOR gates

    • SR Latch using NAND gates

    • D Latch
    SR Latch
    • The SR Latch, can be considered as one of the
    most basic sequential logic circuit possible.
    • This simple circuit is basically a one-bit
    memory bistable device. Q
    • It has two inputs,
    – S: will “SET” the device (meaning the output Q = “1”)
    – R: will “RESET” the device (meaning the output Q = “0”)
    • Output Q is always complement of Q. Q’
    SR Latch using NOR gates
    S R Qt+1 Qt+1’
    0 0 Qt Qt’ Previous output
    0 1 0 1 Reset
    1 0 1 0 Set
    1 1 0 0 Forbidden
    Truth Tables

    A B Y
    0 0 1
    0 1 0
    1 0 0
    1 1 0
    NOR
    SR Latch using NAND gates
    S R Qt+1 Qt+1’
    0 0 1 1 Forbidden
    0 1 1 0 Set
    1 0 0 1 Reset
    1 1 Qt Qt’ Previous output

    A B Y
    0 0 1
    0 1 1
    1 0 1
    1 1 0
    NOR
    SR Latch with Control Input
    E S R Qt+1 Qt+1’
    0 X X - - -
    1 0 0 Qt Qt’ Previous output
    1 0 1 0 1 Reset
    1 1 0 1 0 Set
    1 1 1 0 0 Forbidden

    A B Y
    0 0 1
    0 1 1
    1 0 1
    1 1 0
    NAND
    D Latch with Enable
    Block Symbols for Latches
    Enable Signal
    Logic ‘0’ – 0 Volts

    0 1 Logic ‘ 1’ – 5 Volts or 10 Volts

    Example 1
    1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

    Example 2

    Example 3
    Clock Signals
    Level Triggered Clock Signal

    1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

    Positive – Edge Triggered Clock Signal (Logic 0 to 1)

    0 1
    2 Negative – Edge Triggered Clock Signal (Logic 1 to 0)

    1 0

    You might also like