Lecture 1
Lecture 1
Lecture 1
Moore’s Law
Design Cost/Yield
Power Overview
Logic Properties
1
© Digital
EE141 Integrated Circuits 2nd Introduction
The First Integrated Circuits
Bipolar logic
1960’s
2
© Digital
EE141 Integrated Circuits 2nd Introduction
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
3
© Digital
EE141 Integrated Circuits 2nd Introduction
Intel Pentium (IV) microprocessor
4
© Digital
EE141 Integrated Circuits 2nd Introduction
Moore’s Law
In 1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months
Became industry maxim
Physical constraints limit future growth
5
© Digital
EE141 Integrated Circuits 2nd Introduction
Evolution in Complexity
6
© Digital
EE141 Integrated Circuits 2nd Introduction
Transistor Counts
1 Billion
K
1,000,000
Transistors
100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
7
© Digital
EE141 Integrated Circuits 2nd Courtesy, Intel Introduction
Moore’s law in Microprocessors
1000
10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
8
© Digital
EE141 Integrated Circuits 2nd Courtesy, Intel Introduction
Die Size Growth
100
Die size (mm)
P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years
1
1970 1980 1990 2000 2010
Year
9
© Digital
EE141 Integrated Circuits 2nd Courtesy, Intel Introduction
Frequency
10000
P4 Extreme
1000
Frequency (Mhz)
100 P6
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
10
© Digital
EE141 Integrated Circuits 2nd Courtesy, Intel Introduction
Power Dissipation
100
P6
Power (Watts)
10
486
8086 286
386
8085
1 8080
8008
4004
0.1
1971 1974 1978 1985 1992 2000
Year
11
© Digital
EE141 Integrated Circuits 2nd Courtesy, Intel Introduction
Power density
1000
Power Density (W/cm2)
Nuclear
Reactor P4 Extreme
100
Toaster
Oven
10 8086 Hot Plate P6
8085 Pentium® proc
40048080 286 486
386
1
1970 1980 1990 2000 2010
Year
12
© Digital
EE141 Integrated Circuits 2nd Courtesy, Intel Introduction
Challenges in Digital Design
DSM 1/DSM
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Reliability, Manufacturability • Reuse & IP: Portability
• Power Dissipation • Predictability
• Clock distribution. • etc.
Productivity
10 58%/Yr. compounded 100
10,000 Complexity growth rate 100,000
1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100
0.001
1 0.01
10
2001
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2003
2005
2007
2009
Source: Sematech
14
© Digital
EE141 Integrated Circuits 2nd Courtesy, ITRS Roadmap Introduction
Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But …
How to design chips with more and more functions?
Design engineering population does not double every
two years…
Physical design constraints more and more difficult to
surmount
Diminishing Returns for Design Dollars
15
© Digital
EE141 Integrated Circuits 2nd Introduction
Design Metrics
How to evaluate performance of a
circuit (gate, block, subsystem)?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
16
© Digital
EE141 Integrated Circuits 2nd Introduction
Cost of Integrated Circuits
NRE (non-recurrent engineering) costs
design time and effort
mask generation
validation and debug
Recurrent costs
silicon processing (cheap/unit!)
packaging, test (not cheap!!)
17
© Digital
EE141 Integrated Circuits 2nd Introduction
NRE Cost is Increasing
18
© Digital
EE141 Integrated Circuits 2nd Introduction
Die Cost
Single die
Wafer
From http://www.amd.com 19
© Digital
EE141 Integrated Circuits 2nd Introduction
Yield
No. of good chips per wafer
Y 100 %
Total number of chips per wafer
Wafer cost
Die cost
Dies per wafer Die yield
wafer diameter/2 2 wafer diameter
Dies per wafer
die area 2 die area
20
© Digital
EE141 Integrated Circuits 2nd Introduction
Defects
defects per unit area die area
die yield 1
is approximately 3
v(t) V DD
i(t)
22
© Digital
EE141 Integrated Circuits 2nd Introduction
DC Operation
Voltage Transfer Characteristic
V(y)
VOH = f(VOL)
V f
OH
V(y)=V(x)
VOL = f(VOH)
VM = f(VM)
VM Switching Threshold
V OL
V OL V V(x)
OH
23
© Digital
EE141 Integrated Circuits 2nd Introduction
Mapping between analog and digital signals
V
V
out
“ 1” OH
V Slope = -1
V OH
IH
Undefined
Region
V
IL
Slope = -1
V
“ 0” V OL
OL
V V V
IL IH in
24
© Digital
EE141 Integrated Circuits 2nd Introduction
Definition of Noise Margins
"1"
V
OH
NM H Noise margin high
V
IH
Undefined
Region
NM L V
V IL Noise margin low
OL
"0"
25
© Digital
EE141 Integrated Circuits 2nd Introduction
Noise Budget
Allocates gross noise margin to
expected sources of noise
Sources: supply noise, cross talk,
interference, offset
Differentiate between fixed and
proportional noise sources
26
© Digital
EE141 Integrated Circuits 2nd Introduction
Key Reliability Properties
Absolute noise margin values are deceptive
a floating node is more easily disturbed than a
node driven by a low impedance (in terms of
voltage)
Noise immunity is the more important metric –
the capability to suppress noise sources
Key metrics: Noise transfer functions, Output
impedance of the driver and input impedance of the
receiver;
27
© Digital
EE141 Integrated Circuits 2nd Introduction
Signal Regeneration
out out
v3 v3
f (v) fin v(v)
v1 v1
v3
fin v(v) f (v)
v2 v v0 v
Regenerative Non-Regenerative
28
© Digital
EE141 Integrated Circuits 2nd Introduction
Fan-in and Fan-out
M
N
Fan-out N Fan-in M
29
© Digital
EE141 Integrated Circuits 2nd Introduction
The Ideal Gate
V out
Ri =
Ro = 0
Fanout =
g=
NMH = NML = VDD/2
V in
30
© Digital
EE141 Integrated Circuits 2nd Introduction
An NMOS Inverter
5.0
4.0 NM L
3.0
Vout (V)
2.0
VM
NM H
1.0
R
vout
vin C
tp = ln (2) = 0.69 RC
32
© Digital
EE141 Integrated Circuits 2nd Introduction
Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
1 t T Vsupply t T
Pave p ( t ) dt isupply t dt
T t T t
33
© Digital
EE141 Integrated Circuits 2nd Introduction
Energy and Energy-Delay
Power-Delay Product (PDP) =
E = Energy per operation = Pav tp
34
© Digital
EE141 Integrated Circuits 2nd Introduction
A First-Order RC Network
R
vout
vin CL
T T Vdd
E01 P(t )dt Vdd i (t )dt Vdd C L dVout C LVdd2
0 0 0
T T Vdd 1
Ecap Pcap (t )dt Vout (t )i (t )dt Vout C L dVout C LVdd2
0 0 0 2
35
© Digital
EE141 Integrated Circuits 2nd Introduction
Summary
Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
Some interesting challenges ahead
Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
Understanding the design metrics that govern
digital design is crucial
Cost, reliability, speed, power and energy
dissipation
36
© Digital
EE141 Integrated Circuits 2nd Introduction
Lecture Problems 1
1. If 4” wafers cost $400, 6” cost $800 and 10” cost $1300 estimate the cost of a
5x5mm die in each case, given a point defect rate 0.3/sq cm. How does that
compare to a 7x7mm and 10x10mm die?
2. Go to the ITRS website: http://www.itrs.net and download the 2004 overview
update document. Note the update changes and summarize the few significant
issues (e.g. chip power dissipation)
3. Analog circuits can easily be fabricated in finer scale technologies – yet lag by
orders of magnitude in size from digital designs. Why is this so? (Hint: consider
the effects of composing two working analog sub-circuits into a larger circuit.)
4. Please explain the difference between energy dissipation in a gate model and
that stored in a capacitor. Where does the ½ come from?
5. FPGA (field programmable Logic arrays) are growing into many designs
replacing ASICS. Explain why such designs can compete given a typical 30-50x
performance reduction compared to native custom circuits in the same
technology.
6. An alternative to full custom ASICS are gate array devices– where the lower
level masks are fixed and the upper level metal masks are not. Thus NRE is
substantially lower. Compare to FPGA solutions in cost and performance. (Feel
free to peruse marketing literature..)
37
© Digital
EE141 Integrated Circuits 2nd Introduction