Department of Electronics and Communication Engineering

National Institute of Technology, Tiruchirappali – 620 015

MICROPROCESSORS AND MICROCONTROLLERS

ECPE12

Dr. R.Thilagavathy
Assistant Professor
No. of Credits : 3

Course Type : Program Elective course

Course Teaching and Learning Activities:

Third week of January to First week of February – Unit 1

Second week of February to Fourth week of February - Unit 2

First week of March to Third week of March -Unit 3

Fourth week of March to Second week of April - Unit 4

Third week of April to Fourth week of April - Unit 5

 Course Content

Pre-Requisite: ECPC14 (Digital Circuits and Systems)

Microprocessor based personal computer system. Software model of 8086.

Segmented memory operation. Instruction set. Addressing modes. Assembly
language programming. Interrupts. Programming with DOS and BIOS function
calls.

Hardware detail of 8086. . Bus timing. Minimum vs Maximum mode of

operation. Memory interface. Parallel and serial data transfer methods. 8255
PPI chip. 8259 Interrupt controller. 8237 DMA controller.
 
Microcontroller. Von-Neumann Vs Harvard architecture. Programming model.
Instruction set of 8051 Microcontroller. Addressing modes. Programming.
Timer operation.
Mixed Signal Microcontroller: MSP430 series. Block diagram. Address
space. On-chip peripherals -analog and digital. Register sets. Addressing
Modes. Instruction set. Programming. FRAM vs flash for low power and
reliability.

Peripheral Interfacing using 8051 and Mixed signal microcontroller. Serial

data transfer - UART, SPI and I2C. Interrupts. I/O ports and port expansion.
DAC, ADC, PWM, DC motor, Stepper motor and LCD interfacing.

Objective:
This subject deals about the basics of 16-bit Microprocessor, 8-bit and 16-
bit Micro controllers, their architectures, internal organization and their
functions, peripherals, and interfacing.

Course Outcomes:
Students are able to
CO1: recall and apply a basic concept of digital fundamentals to
CO2: illustrate how the different peripherals are interfaced with
Microprocessor.

CO3: distinguish and analyze the properties of Microprocessors &

Microcontrollers.

CO4: understand a low power and reliability concept of mixed signal

Microcontrollers.

CO5: analyze the data transfer information through serial & parallel ports.

Books
Text Books:

 James L. Antonakos, An Introduction to the Intel Family of

Microprocessors”, Pearson, 1999
 M.A.Mazidi&J.C.Mazidi “ Microcontroller and Embedded systems using
Assembly & C. (2/e)”, Pearson Education, 2007.

 John H. Davies, “MSP430 Microcontroller Basics”, Elsevier Ltd., 2008

Reference Books:

 Barry B. Brey, The Intel Microprocessors, (7/e), Eastern Economy Edition ,

2006.

 K.J. Ayala, “The 8051 Microcontroller “, (3/e), Thomson Delmar Learning,

2004.

 I. S. MacKenzie and R.C.W.Phan., “ The 8051 Microcontroller.(4/e)”,

Pearson education, 2008.
 Microprocessor based computer system

Bus Bus

Microprocessor-based systems are electrical systems consisting of

Microprocessors, memories, I/O units, and other peripherals.

Microprocessors are the brains of the systems.

Microprocessors access memories and other units through buses.

The operations of microprocessors are controlled by instructions stored in

memories.
A microprocessor is a processor (or Central Processing Unit, CPU)
fabricated on a single integrated circuit.

A simple microprocessor architecture.

Address bus
MAR

PC

IR

Control
Control bus
unit

Y ACC
Data bus ALU
 Evolution of Intel Microprocessors
Number of transistors Minimum transistor sizes (µm)
100,000,000
7
P III 8080
10,000,000
Pentium P4 6
1,000,000 80386 P II 5
100,000 8088 80486
4
80286
10,000 8088
3
1,000 8080
2 80386
100
Pentium
10 1 80286 P II P III P 4
1 0
80486
1974 1979 1982 1985 1989 1993 1997 1999 2000 1974 1979 1982 1985 1989 1993 1997 1999 2000

Clock frequencies (MHz) MIPS

10000 10000
P4
1000 P III
1000 P4
P II Pentium
Pentium P III 100 P II
100
80386 10 80386
80486
10 8088 80486
8080 1 8080 8088
80286 80286
1 0.1
1974 1979 1982 1985 1989 1993 1997 1999 2000 1974 1979 1982 1985 1989 1993 1997 1999 2000
Moore’s Law, which states that the number of transistors per integrated
circuit will double approximately every 18-24 months, has become the
defining metaphor of the modern technological age.
Applications of Microprocessor-Based Systems

Other

... ...
Keyboard Monitor Disk
peripherals
Bus

Micro- Timing & Interrupt

Memory
processor control control

Block diagram of a computer

 20 bit address bus allow accessing 220
(1MB) memory locations. VDD (5V)
(1048576)

16 bit Data bus allow accessing 216 20-bit

16-bit data
(65,536) numbers address

control
Byte addressable and byte-swapping signals
8086 control
signals


Word: 5A2F


To 8086 from 8086

18001 5A High byte of word CLK

18000 2F Low byte of word
GND

8086 signal classification

Memory locations
 Organization of 8086
Address bus (20 bits)
AH AL General purpose
BH BL register 

CH CL
Execution Unit
DH DL
(EU) Data bus
SP CS (16 bits)
Segment
BP register DS
SI SS
DI ALU Data bus ES
(16 bits)
IP

Bus
control
ALU Instruction Queue External bus
EU
control
Flag register
Bus Interface Unit (BIU)
 General Purpose Registers
15 8 7 0
AX AH AL Accumulator

BX BH BL Base
Data Group
CX CH CL Counter

DX DH DL Data

SP Stack Pointer

BP Base Pointer
Pointer and
Index Group
SI Source Index

DI Destination Index

IP Instruction pointer

Flag Register
 Arithmetic Logic Unit (ALU)
A B F Y
n bits n bits
0 0 0 A+B
0 0 1 A -B
Carry
0 1 0 A -1
Y= 0 ? F 0 1 1 A and B
1 0 0 A or B
A>B?
1 0 1 not A
     
Y
 Signal F control which function will be conducted by ALU.
 Signal F is generated according to the current instruction.

 Basic arithmetic operations: addition, subtraction, 

 Basic logic operations: and, or, xor, shifting,
 Flag Register
Flag register contains information reflecting the current status of a
microprocessor. It also contains information which controls the operation of
the microprocessor.
15 0
   OF DF IF TF SF ZF  AF  PF  CF

 Control Flags  Status Flags

IF: Interrupt enable flag CF: Carry flag

DF: Direction flag PF: Parity flag
TF:Trap flag AF: Auxiliary carry flag
ZF:Zero flag
SF: Sign flag
OF: Overflow flag
Carry Parity
unsigned arithmetic out of sum of 1 bits is an even number
range Direction
Overflow Increment & decrement the SI and
signed arithmetic out of range
Sign DI registers
result is negative Interrupt
Zero controls operation of the INTR
result is zero (interrupt request) input pin
Auxiliary Carry Trap
trapping through an on-chip
carry from bit 3 to bit 4
debugging feature
 Instruction Machine Codes
Instruction machine codes are binary numbers
 For Example:

1000100011000011
MOV AL, BL
MOV Register
mode

Machine code structure

Opcode Mode Operand1 Operand2

• Some instructions do not have operands, or have only one operand.

• Opcode tells what operation is to be performed. (EU control logic
generates ALU control signals according to Opcode)
• Mode indicates the type of a instruction: Register type, or Memory type
• Operands tell what data should be used in the operation.
• Operands can be addresses telling where to get data (or where to store
results)
 EU Operation
1. Fetch an instruction from instruction
AH AL
queue BH BL
General purpose
register
2. According to the instruction, EU CH CL
control logic generates control signals. DH DL
SP
BP
(This process is also referred to as SI
instruction decoding) DI ALU Data bus
(16 bits)
3. Depending on the control signal, EU
performs one of the following
operations:
An arithmetic operation ALU
EU
A logic operation control instruction
1011000101001010
Flag register
Storing a datum into a register
Moving a datum from a register
Changing flag register
 Memory Segmentation
• A segment is a 64KB block of memory starting from any 16-byte
boundary
• For example: 00000, 00010, 00020, 20000, 8CE90, and E0840 are all
valid segment addresses
• The requirement of starting from 16-byte boundary is due to the 4-bit left
shifting
Segment registers in BIU
15 0
CS Code Segment

DS Data Segment

SS Stack Segment

ES Extra Segment
 Generating Memory Addresses
How can a 16-bit microprocessor generate 20-bit memory addresses?

Left shift 4 bits

FFFFF

16-bit register 0000 Addr1 + 0FFFF

Segment
+ 16-bit register Offset
Addr1
Offset
(64K)

20-bit memory address Segment

address
00000

Intel 80x86 memory address generation 1M memory space

 Memory Address Calculation

 Segment addresses must be stored 0000

Segment address
in segment registers
 Offset is derived from the combination + Offset

of pointer registers, the Instruction Memory address

Pointer (IP), and immediate values

 Examples

CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction address 3 8 A B 4 Stack address 5 F F E 0

DS 1 2 3 4 0
DI + 0 0 2 2
Data address 1 2 3 6 2
 Fetching Instructions
 Where to fetch the next instruction?
8088 Memory

CS 1234
IP 0012 12352 MOV AL, 0

12352

 Update IP
— After an instruction is fetched, Register IP is updated as follows:

IP = IP + Length of the fetched instruction

— For Example: the length of MOV AL, 0 is 2 bytes. After fetching this instruction,
the IP is updated to 0014
 Defaults
Convention Example: EA = CS:[IP]
• Default segment numbers in:
• CS for program (code) Segment number Offset: Literal
• SS for stack in Segment register or in a CPU register
• DS for data
• ES for string (destination) data
• Default offset addresses that go with them:

Segment Offset (16-bit) Purpose

8080, 8086, 80286

CS IP Program

SS SP, BP Stack

DS BX, DI, SI, 8-bit or 16-bit # Data

ES DI, with string instructions String

destination
 Accessing Data Memory
 There is a number of methods to generate the memory address when
accessing data memory. These methods are referred to as
Addressing Modes
 Examples:
— Direct addressing: MOV AL, [0300H]

DS 1 2 3 4 0 (assume DS=1234H)
0 3 0 0
Memory address 1 2 6 4 0

— Register indirect addressing: MOV AL, [SI]

DS 1 2 3 4 0 (assume DS=1234H)
0 3 1 0 (assume SI=0310H)
Memory address 1 2 6 5 0
 INSTRUCTION SET OF 8086

Classified into 7 categories:

1] Data Transfer
2] Arithmetic ADD AX, BX
3] Logical
AND AX, BX
4] Branch
5] Processor Control Instructions JMP Target address

6] String Manipulation
7] Interrupt Control
Generate memory addresses when combined with other registers in the
Microprocessor.
CS (code) segment holds code (programs and procedures) used by the
Microprocessor.

DS (data) contains most data used by a program.

Data are accessed by an offset address or contents of other
registers that hold the offset address

ES (extra) an additional data segment used by some instructions to hold

destination data.

SS (stack) defines the area of memory used for the stack.

stack entry point is determined by the stack segment and stack
pointer registers the BP register also addresses data within
the stack segment
Segmentation
Addressing Modes Summary
 Addressing Modes
Register Addressing
MOV BX, CX
Immediate Addressing
MOV AX, 3456H
Direct Addressing
MOV AL,[1234H]
Register Indirect Addressing
MOV AX,[BX]
Base-Plus-Index Addressing
MOV DX,[BX + DI]
Register Relative Addressing
MOV AX,[BX+1000H]
Base Relative-Plus-Index Addressing
MOV AX,[BX + SI + 100H]
MOV AX, BX - correct instruction MOV AL, BL - correct instruction
MOV AX, BL - incorrect instruction MOV AL, BX - incorrect instruction

[ ] – indicate the base address in segment registers.

Default register is DS MOV AX, [BX]

MOV AX, [BP]

Base address in SS not in DS.

We can change the base address like this MOV AX, DS : [BP]

MOV AL, 16h AL = 16

MOV AL, 16 AL = 10
MOV AL, 0010 1000B AL = 28
MOV AL, ’A’ AL = 41
MOV AL, -1 AL = FF
MOV AX, 1000H
MOV BX, 0200H
MOV DS, AX
MOV DX, BX
MOV [0100H], AX
MOV AX, [BX]