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    Counter Design

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    Amoga Lekshmi

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    © All Rights Reserved
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    Counter Design

    Uploaded by

    Amoga Lekshmi
    56 views14 pages

    Original Title

    9. Counter Design

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    Download as ppt, pdf, or txt
    56 views14 pages

    Counter Design

    Uploaded by

    Amoga Lekshmi

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    You are on page 1of 14

    Advanced Digital System Design

    Jawahar .A
    SSN College of Engineering
    Objectives

    At the end of this lecture every should know,

    • Excitation table
    • Design/Synthesis using D flip flop
    • Design/Synthesis JK flip flop
    • Design/Synthesis using T flip flop
    • Unused states
    • Other counters
    • Design example problems
    Design Procedure:

     the word description of the circuit behavior (a state diagram)


     state reduction if necessary
     assign binary values to the states
     obtain the binary-coded state table
     choose the type of flip-flops
     derive the simplified flip-flop input equations and output
    equations
     draw the logic diagram
    Excitation tables

    • A state diagram  flip-flop input functions


    – straightforward for D flip-flops
    – we need excitation tables for JK and T flip-flops

    JK Flip-flop T Flip-flop
    Q Q (t + 1) J K Q Q (t + 1) T
    0 0 0 X 0 0 0
    0 1 1 X 0 1 1
    1 0 X 1 1 0 1
    1 1 X 0 1 1 0
    Flip-Flop Excitation Tables

    Q Q+ J K S R T D

    0 0 0 X 0 X 0 0
    0 1 1 X 1 0 1 1
    1 0 X 1 0 1 1 0
    1 1 X 0 X 0 0 1

    You can use any FF type for your implementation

    FF types can be mixed; I.e. in vending machine


    you could use a JK FF for Q1 and a T FF for Q0
    Design of 3-bit counter (Synthesis using T flip-flops)
    • A n-bit binary counter
    – the state diagram

    – no inputs (except for the clock input)


    • The state table and the flip-flop inputs

    Present State Next State Flip-flop Inputs


    A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
    0 0 0 0 0 1 0 0 1
    0 0 1 0 1 0 0 1 1
    0 1 0 0 1 1 0 0 1
    0 1 1 1 0 0 1 1 1
    1 0 0 1 0 1 0 0 1
    1 0 1 1 1 0 0 1 1
    1 1 0 1 1 1 0 0 1
    1 1 1 0 0 0 1 1 1
    Other counters:

    • Divide-by-N counter (modulo-N counter)


     a counter that goes through a repeated sequence of N states.
     The sequence may follow the binary count or may be any
    other arbitrary sequence.
    • n flip-flops  2n binary states
    • Unused states
     states that are not used in specifying the sequential circuit.
     may be treated as don’t-care conditions or may be assigned
    specific next states
    • Self-correcting counter
     Ensure that when a circuit enter one of its unused states, it
    eventually goes into one of the valid states after one or more
    clock pulses so it can resume normal operation.
     Analyze the circuit to determine the next state from an
    unused state after it is designed.
    Ex: Design a counter to have the sequence as follows: 000, 001, 010, 100,
    101, 110, 000… using JK flip-flop.
    Here the given sequence has 3 bits in each state so the counter
    requires 3 flip-flops. The state table is written for the given sequence
    and the flip-flop inputs are found using the excitation table.
    JA = B KA = B

    JB = C KB = 1

    JC = B’ KC = 1
    In the given sequence there are two unused states: 011 & 111.
    The simplified flip-flop input equations are:
    JA = B, KA = B ;
    JB = C, KB = 1 ;
    JC = B, KC = 1

    Figure. Logic diagram Figure. State diagram


    Here the counter is a self-correcting one. Even if goes to some unused
    states it returns back to an used state and goes through the sequence.
    Design Examples for practice:

    (1)Design a mod-6 counter using T-FFs. (Hint: Count seq- 000 to 101)

    (2)Design a mod-12 counter using JK-FFs.

    (3)Design a counter which has the sequence as follows: 0000, 1000,


    1100, 1110, 1111, 0111, 0011, 0001, 0000… using T-FFs.

    (4)Design a 3-bit synchronous down counter.

    (5)Design a synchronous BCD counter using JK-FFs & D-FFs. (using


    T-FFs already discussed). Compare the designs to determine which
    one is more efficient.
    Summary

    • Excitation table
    • Design/Synthesis using D flip flop
    • Design/Synthesis JK flip flop
    • Design/Synthesis using T flip flop
    • Unused states
    • Other counters
    • Design example problems

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