Datasheet DSPIC33EP128MC204 70000657H-277982
Datasheet DSPIC33EP128MC204 70000657H-277982
Datasheet DSPIC33EP128MC204 70000657H-277982
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X
16-Bit Microcontrollers and Digital Signal Controllers
with High-Speed PWM, Op Amps and Advanced Analog
Operating Conditions Timers/Output Compare/Input Capture
• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS • 12 General Purpose Timers:
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS - Five 16-bit and up to two 32-bit timers/counters
- Four Output Compare (OC) modules, configurable
Core: 16-Bit dsPIC33E/PIC24E CPU as timers/counters
• Code Efficient (C and Assembly) Architecture - PTG module with two configurable timers/counters
• Two 40-Bit-Wide Accumulators - 32-bit Quadrature Encoder Interface (QEI) module,
• Single Cycle (MAC/MPY) with Dual Data Fetch configurable as a timer/counter
• Single-Cycle, Mixed-Sign MUL plus Hardware Divide • Four Input Capture (IC) modules
• 32-Bit Multiply Support • Peripheral Pin Select (PPS) to allow Function Remap
• Peripheral Trigger Generator (PTG) for Scheduling
Clock Management Complex Sequences
• 1.0% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources Communication Interfaces
• Fail-Safe Clock Monitor (FSCM) • Two UART modules (17.5 Mbps):
• Independent Watchdog Timer (WDT) - With support for LIN/J2602 protocols and IrDA®
• Fast Wake-up and Start-up • Two 4-Wire SPI modules (15 Mbps)
• ECAN™ module (1 Mbaud) CAN 2.0B Support
Power Management • Two I2C™ modules (up to 1 Mbaud) with SMBus
• Low-Power Management modes (Sleep, Idle, Doze) Support
• Integrated Power-on Reset and Brown-out Reset • PPS to allow Function Remap
• 0.6 mA/MHz Dynamic Current (typical) • Programmable Cyclic Redundancy Check (CRC)
• 30 µA IPD Current (typical)
Direct Memory Access (DMA)
High-Speed PWM • 4-Channel DMA with User-Selectable Priority Arbitration
• Up to Three PWM Pairs with Independent Timing • UART, SPI, ADC, ECAN, IC, OC and Timers
• Dead Time for Rising and Falling Edges
• 7.14 ns PWM Resolution Input/Output
• PWM Support for: • Sink/Source 12 mA or 6 mA, Pin-Specific for
- DC/DC, AC/DC, Inverters, PFC, Lighting Standard VOH/VOL, up to 22 or 14 mA, respectively
- BLDC, PMSM, ACIM, SRM for Non-Standard VOH1
• Programmable Fault Inputs • 5V Tolerant Pins
• Flexible Trigger Configurations for ADC Conversions • Peripheral Pin Select (PPS) to allow Digital Function
Remapping
Advanced Analog Features
• Selectable Open-Drain, Pull-ups and Pull-Downs
• ADC module: • Up to 5 mA Overvoltage Clamp Current
- Configurable as 10-bit, 1.1 Msps with four S&H or
• Change Notification Interrupts on All I/O Pins
12-bit, 500 ksps with one S&H
- Six analog inputs on 28-pin devices and up to Qualification and Class B Support
16 analog inputs on 64-pin devices • AEC-Q100 REVG (Grade 1, -40°C to +125°C) Planned
• Flexible and Independent ADC Trigger Sources • AEC-Q100 REVG (Grade 0, -40°C to +150°C) Planned
• Up to Three Op Amp/Comparators with • Class B Safety Library, IEC 60730
Direct Connection to the ADC module:
- Additional dedicated comparator Debugger Development Support
- Programmable references with 32 voltage points • In-Circuit and In-Application Programming
• Charge Time Measurement Unit (CTMU): • Two Program and Two Complex Data Breakpoints
- Supports mTouch™ capacitive touch sensing • IEEE 1149.2 Compatible (JTAG) Boundary Scan
- Provides high-resolution time measurement (1 ns) • Trace and Run-Time Watch
- On-chip temperature measurement
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X AND
PIC24EPXXXGP/MC20X PRODUCT
FAMILIES
The device names, pin counts, memory sizes and
peripheral availability of each device are listed in
Table 1 (General Purpose Families) and Table 2 (Motor
Control Families). Their pinout diagrams appear on the
following pages.
Remappable Peripherals
Page Erase Size (Instructions)
Op Amps/Comparators
External Interrupts(3)
ECAN™ Technology
16-Bit/32-Bit Timers
CRC Generator
Output Compare
RAM (Kbyte)
Input Capture
Packages
I/O Pins
CTMU
I2C™
Pins
PTG
UART
SPI(2)
Device
PIC24EP32GP202 512 32 4
PIC24EP64GP202 1024 64 8 SPDIP,
SOIC,
PIC24EP128GP202 1024 128 16 5 4 4 2 2 — 3 2 1 6 2/3(1) Yes Yes 21 28
SSOP(4),
PIC24EP256GP202 1024 256 32 QFN-S
PIC24EP512GP202 1024 512 48
PIC24EP32GP203 512 32 4
5 4 4 2 2 — 3 2 1 8 3/4 Yes Yes 25 36 VTLA
PIC24EP64GP203 1024 64 8
PIC24EP32GP204 512 32 4
PIC24EP64GP204 1024 64 8 VTLA(4),
44/ TQFP,
PIC24EP128GP204 1024 128 16 5 4 4 2 2 — 3 2 1 9 3/4 Yes Yes 35
48 QFN,
PIC24EP256GP204 1024 256 32 UQFN
PIC24EP512GP204 1024 512 48
PIC24EP64GP206 1024 64 8
PIC24EP128GP206 1024 128 16 TQFP,
5 4 4 2 2 — 3 2 1 16 3/4 Yes Yes 53 64
PIC24EP256GP206 1024 256 32 QFN
PIC24EP512GP206 1024 512 48
dsPIC33EP32GP502 512 32 4
dsPIC33EP64GP502 1024 64 8 SPDIP,
SOIC,
dsPIC33EP128GP502 1024 128 16 5 4 4 2 2 1 3 2 1 6 2/3(1) Yes Yes 21 28
SSOP(4),
dsPIC33EP256GP502 1024 256 32 QFN-S
dsPIC33EP512GP502 1024 512 48
dsPIC33EP32GP503 512 32 4
5 4 4 2 2 1 3 2 1 8 3/4 Yes Yes 25 36 VTLA
dsPIC33EP64GP503 1024 64 8
dsPIC33EP32GP504 512 32 4
dsPIC33EP64GP504 1024 64 8 VTLA(4),
44/ TQFP,
dsPIC33EP128GP504 1024 128 16 5 4 4 2 2 1 3 2 1 9 3/4 Yes Yes 35
48 QFN,
dsPIC33EP256GP504 1024 256 32 UQFN
dsPIC33EP512GP504 1024 512 48
dsPIC33EP64GP506 1024 64 8
dsPIC33EP128GP506 1024 128 16 TQFP,
5 4 4 2 2 1 3 2 1 16 3/4 Yes Yes 53 64
dsPIC33EP256GP506 1024 256 32 QFN
dsPIC33EP512GP506 1024 512 48
Note 1: On 28-pin devices, Comparator 4 does not have external connections. Refer to Section 25.0 “Op Amp/Comparator Module” for details.
2: Only SPI2 is remappable.
3: INT0 is not remappable.
4: The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.
Op Amps/Comparators
Motor Control PWM(4)
External Interrupts(3)
ECAN™ Technology
16-Bit/32-Bit Timers
CRC Generator
RAM (Kbytes)
Output Compare
Input Capture
Packages
I/O Pins
(Channels)
CTMU
I2C™
Pins
PTG
UART
SPI(2)
Device
PIC24EP32MC202 512 32 4
PIC24EP64MC202 1024 64 8 SPDIP,
SOIC,
PIC24EP128MC202 1024 128 16 5 4 4 6 1 2 2 — 3 2 1 6 2/3(1) Yes Yes 21 28
SSOP(5),
PIC24EP256MC202 1024 256 32 QFN-S
PIC24EP512MC202 1024 512 48
PIC24EP32MC203 512 32 4
5 4 4 6 1 2 2 — 3 2 1 8 3/4 Yes Yes 25 36 VTLA
PIC24EP64MC203 1024 64 8
PIC24EP32MC204 512 32 4
PIC24EP64MC204 1024 64 8 VTLA(5),
44/ TQFP,
PIC24EP128MC204 1024 128 16 5 4 4 6 1 2 2 — 3 2 1 9 3/4 Yes Yes 35
48 QFN,
PIC24EP256MC204 1024 256 32 UQFN
PIC24EP512MC204 1024 512 48
PIC24EP64MC206 1024 64 8
PIC24EP128MC206 1024 128 16 TQFP,
5 4 4 6 1 2 2 — 3 2 1 16 3/4 Yes Yes 53 64
PIC24EP256MC206 1024 256 32 QFN
PIC24EP512MC206 1024 512 48
dsPIC33EP32MC202 512 32 4
dsPIC33EP64MC202 1024 64 8 SPDIP,
SOIC,
dsPIC33EP128MC202 1024 128 16 5 4 4 6 1 2 2 — 3 2 1 6 2/3(1) Yes Yes 21 28
SSOP(5),
dsPIC33EP256MC202 1024 256 32 QFN-S
dsPIC33EP512MC202 1024 512 48
dsPIC33EP32MC203 512 32 4
5 4 4 6 1 2 2 — 3 2 1 8 3/4 Yes Yes 25 36 VTLA
dsPIC33EP64MC203 1024 64 8
dsPIC33EP32MC204 512 32 4
dsPIC33EP64MC204 1024 64 8 VTLA(5),
44/ TQFP,
dsPIC33EP128MC204 1024 128 16 5 4 4 6 1 2 2 — 3 2 1 9 3/4 Yes Yes 35
48 QFN,
dsPIC33EP256MC204 1024 256 32 UQFN
dsPIC33EP512MC204 1024 512 48
dsPIC33EP64MC206 1024 64 8
dsPIC33EP128MC206 1024 128 16 TQFP,
5 4 4 6 1 2 2 — 3 2 1 16 3/4 Yes Yes 53 64
dsPIC33EP256MC206 1024 256 32 QFN
dsPIC33EP512MC206 1024 512 48
dsPIC33EP32MC502 512 32 4
dsPIC33EP64MC502 1024 64 8 SPDIP,
SOIC,
dsPIC33EP128MC502 1024 128 16 5 4 4 6 1 2 2 1 3 2 1 6 2/3(1) Yes Yes 21 28
SSOP(5),
dsPIC33EP256MC502 1024 256 32 QFN-S
dsPIC33EP512MC502 1024 512 48
dsPIC33EP32MC503 512 32 4
5 4 4 6 1 2 2 1 3 2 1 8 3/4 Yes Yes 25 36 VTLA
dsPIC33EP64MC503 1024 64 8
Note 1: On 28-pin devices, Comparator 4 does not have external connections. Refer to Section 25.0 “Op Amp/Comparator Module” for details.
2: Only SPI2 is remappable.
3: INT0 is not remappable.
4: Only the PWM Faults are remappable.
5: The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.
Op Amps/Comparators
Motor Control PWM(4)
External Interrupts(3)
ECAN™ Technology
16-Bit/32-Bit Timers
CRC Generator
RAM (Kbytes)
Output Compare
Input Capture
Packages
I/O Pins
(Channels)
CTMU
I2C™
Pins
PTG
UART
SPI(2)
Device
dsPIC33EP32MC504 512 32 4
dsPIC33EP64MC504 1024 64 8 VTLA(5),
44/ TQFP,
dsPIC33EP128MC504 1024 128 16 5 4 4 6 1 2 2 1 3 2 1 9 3/4 Yes Yes 35
48 QFN,
dsPIC33EP256MC504 1024 256 32 UQFN
dsPIC33EP512MC504 1024 512 48
dsPIC33EP64MC506 1024 64 8
dsPIC33EP128MC506 1024 128 16 TQFP,
5 4 4 6 1 2 2 1 3 2 1 16 3/4 Yes Yes 53 64
dsPIC33EP256MC506 1024 256 32 QFN
dsPIC33EP512MC506 1024 512 48
Note 1: On 28-pin devices, Comparator 4 does not have external connections. Refer to Section 25.0 “Op Amp/Comparator Module” for details.
2: Only SPI2 is remappable.
3: INT0 is not remappable.
4: Only the PWM Faults are remappable.
5: The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.
Pin Diagrams
MCLR 1 28 AVDD
AN0/OA2OUT/RA0 2 27 AVSS
AN1/C2IN1+/RA1 3 26 RPI47/T5CK/RB15
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 4 25 RPI46/T3CK/RB14
dsPIC33EPXXXGP502
PIC24EPXXXGP202
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 5 24 RPI45/CTPLS/RB13
PGEC1/AN4/C1IN1+/RPI34/RB2 6 23 RPI44/RB12
PGED1/AN5/C1IN1-/RP35/RB3 7 22 TDI/RP43/RB11
VSS 8 21 TDO/RP42/RB10
OSC1/CLKI/RA2 9 20 VCAP
OSC2/CLKO/RA3 10 19 VSS
RP36/RB4 11 18 TMS/ASDA1/SDI1/RP41/RB9(3)
CVREF2O/RP20/T1CK/RA4 12 17 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
VDD 13 16 SCK1/RP39/INT0/RB7
PGED2/ASDA2/RP37/RB5 14 15 PGEC2/ASCL2/RP38/RB6
MCLR 1 28 AVDD
AN0/OA2OUT/RA0 2 27 AVSS
AN1/C2IN1+/RA1 3 26 RPI47/PWM1L/T5CK/RB15
dsPIC33EPXXXMC202/502
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 4 25 RPI46/PWM1H/T3CK/RB14
PIC24EPXXXMC202
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 5 24 RPI45/PWM2L/CTPLS/RB13
PGEC1/AN4/C1IN1+/RPI34/RB2 6 23 RPI44/PWM2H/RB12
PGED1/AN5/C1IN1-/RP35/RB3 7 22 TDI/RP43/PWM3L/RB11
VSS 8 21 TDO/RP42/PWM3H/RB10
OSC1/CLKI/RA2 9 20 VCAP
OSC2/CLKO/RA3 10 19 VSS
FLT32/RP36/RB4 11 18 TMS/ASDA1/SDI1/RP41/RB9(3)
CVREF2O/RP20/T1CK/RA4 12 17 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
VDD 13 16 SCK1/RP39/INT0/RB7
PGED2/ASDA2/RP37/RB5 14 15 PGEC2/ASCL2/RP38/RB6
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
AN0/OA2OUT/RA0
RPI47/T5CK/RB15
RPI46/T3CK/RB14
AN1/C2IN1+/RA1
MCLR
AVDD
AVSS
28 27 26 25 24 23 22
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 1 21 RPI45/CTPLS/RB13
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 2 20 RPI44/RB12
PGEC1/AN4/C1IN1+/RPI34/RB2 3 19 TDI/RP43/RB11
dsPIC33EPXXXGP502
PGED1/AN5/C1IN1-/RP35/RB3 4 18 TDO/RP42/RB10
PIC24EPXXXGP202
VSS 5 17 VCAP
OSC1/CLKI/RA2 6 16 VSS
OSC2/CLKO/RA3 7 15 TMS/ASDA1/SDI1/RP41/RB9(4)
8 9 10 11 12 13 14
RP36/RB4
PGED2/ASDA2/RP37/RB5
TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
CVREF2O/RP20/T1CK/RA4
PGEC2/ASCL2/RP38/RB6
SCK1/RP39/INT0/RB7
VDD
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
MCLR
AVDD
AVSS
28 27 26 25 24 23 22
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 1 21 RPI45/PWM2L/CTPLS/RB13
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 2 20 RPI44/PWM2H/RB12
PGEC1/AN4/C1IN1+/RPI34/RB2 3 19 TDI/RP43/PWM3L/RB11
dsPIC33EPXXXMC202/502
PGED1/AN5/C1IN1-/RP35/RB3 4 PIC24EPXXXMC202 18 TDO/RP42/PWM3H/RB10
VSS 5 17 VCAP
OSC1/CLKI/RA2 6 16 VSS
OSC2/CLKO/RA3 7 15 TMS/ASDA1/SDI1/RP41/RB9(4)
8 9 10 11 12 13 14
CVREF2O/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
FLT32/RP36/RB4
PGEC2/ASCL2/RP38/RB6
SCK1/RP39/INT0/RB7
TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
VDD
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
AN0/OA2OUT/RA0
RPI47/T5CK/RB15
RPI46/T3CK/RB14
AN1/C2IN1+/RA1
MCLR
AVDD
AVSS
36 35 34 33 32 31 30 29 28 27 RPI45/CTPLS/RB13
PGEC1/AN4/C1IN1+/RPI34/RB2 1 26 RPI44/RB12
PGED1/AN5/C1IN1-/RP35/RB3 2 25 TDI/RP43/RB11
AN6/OA3OUT/C4IN1+/OCFB/RC0 3 24 TDO/RP42/RB10
AN7/C3IN1-/C4IN1-/RC1
dsPIC33EP32GP503
4 23 VDD
dsPIC33EP64GP503
VDD 5 PIC24EP32GP203 22 VCAP
PIC24EP64GP203
VSS 6 21 VSS
OSC1/CLKI/RA2 7 20 RP56/RC8
OSC2/CLKO/RA3 8 19 TMS/ASDA1/SDI1/RP41/RB9(4)
SDA2/RPI24/RA8 9 10 11 12 13 14 15 16 17
17 18
SCL2/RP36/RB4
CVREF2O/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
VDD
VDD
SCK1/RP39/INT0/RB7
TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
VSS
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
MCLR
AVDD
AVSS
36 35 34 33 32 31 30 29 28 27 RPI45/PWM2L/CTPLS/RB13
PGEC1/AN4/C1IN1+/RPI34/RB2 1 26 RPI44/PWM2H/RB12
PGED1/AN5/C1IN1-/RP35/RB3 2 25 TDI/RP43/PWM3L/RB11
AN6/OA3OUT/C4IN1+/OCFB/RC0 3 24 TDO/RP42/PWM3H/RB10
AN7/C3IN1-/C4IN1-/RC1 4 dsPIC33EP32MC203/503 23 VDD
dsPIC33EP64MC203/503
VDD 5 PIC24EP32MC203 22 VCAP
PIC24EP64MC203
VSS 6 21 VSS
OSC1/CLKI/RA2 7 20 RP56/RC8
OSC2/CLKO/RA3 8 19 TMS/ASDA1/SDI1/RP41/RB9(4)
SDA2/RPI24/RA8 9 10 11 12 13 14 15 16 17 18
CVREF2O/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
SCK1/RP39/INT0/RB7
FLT32/SCL2/RP36/RB4
TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
VSS
VDD
VDD
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
CVREF2O/SDO1/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SCL1/RPI53/RC5
SDI1/RPI25/RA9
RP39/INT0/RB7
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
TMS/ASDA1/RP41/RB9(3) 1 33 SCL2/RP36/RB4
RP54/RC6 2 32 SDA2/RPI24/RA8
RP55/RC7 3 31 OSC2/CLKO/RA3
RP56/RC8 4 30 OSC1/CLKI/RA2
RP57/RC9 5 29 VSS
VSS
dsPIC33EPXXXGP504
6 28 VDD
PIC24EPXXXGP204
VCAP 7 27 AN8/C3IN1+/U1RTS/BCLK1/RC2
RP42/RB10 8 26 AN7/C3IN1-/C4IN1-/RC1
RP43/RB11 9 25 AN6/OA3OUT/C4IN1+/OCFB/RC0
RPI44/RB12 10 24 PGED1/AN5/C1IN1-/RP35/RB3
RPI45/CTPLS/RB13 11 23 PGEC1/AN4/C1IN1+/RPI34/RB2
12
13
14
15
16
17
18
19
20
21
22
MCLR
AVSS
TDO/RA10
TDI/RA7
RPI46/T3CK/RB14
RPI47/T5CK/RB15
AVDD
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
CVREF2O/SDO1/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SCL1/RPI53/RC5
SDI1/RPI25/RA9
RP39/INT0/RB7
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
TMS/ASDA1/RP41/RB9(3) 1 33 FLT32/SCL2/RP36/RB4
RP54/RC6 2 32 SDA2/RPI24/RA8
RP55/RC7 3 31 OSC2/CLKO/RA3
RP56/RC8 4 30 OSC1/CLKI/RA2
RP57/RC9 5 29 VSS
dsPIC33EPXXXMC204/504
VSS 6 28 VDD
PIC24EPXXXMC204
VCAP 7 27 AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
RP42/PWM3H/RB10 8 26 AN7/C3IN1-/C4IN1-/RC1
RP43/PWM3L/RB11 9 25 AN6/OA3OUT/C4IN1+/OCFB/RC0
RPI44/PWM2H/RB12 10 24 PGED1/AN5/C1IN1-/RP35/RB3
RPI45/PWM2L/CTPLS/RB13 11 23 PGEC1/AN4/C1IN1+/RPI34/RB2
12
13
14
15
16
17
18
19
20
21
22
TDO/RA10
TDI/RA7
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
MCLR
AVSS
AVDD
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
CVREF2O/SDO1/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SCL1/RPI53/RC5
SDI1/RPI25/RA9
RP39/INT0/RB7
VDD
VSS
44 43 42 41 40 39 38 37 36 35 34 33 SCL2/RP36/RB4
TMS/ASDA1/RP41/RB9(4) 1 32 SDA2/RPI24/RA8
RP54/RC6 2 31 OSC2/CLKO/RA3
RP55/RC7 3 30 OSC1/CLKI/RA2
RP56/RC8 4 29 VSS
RP57/RC9 5 dsPIC33EPXXXGP504 28 VDD
VSS 6 PIC24EPXXXGP204 27 AN8/C3IN1+/U1RTS/BCLK1/RC2
VCAP 7 26 AN7/C3IN1-/C4IN1-/RC1
RP42/RB10 8 25 AN6/OA3OUT/C4IN1+/OCFB/RC0
RP43/RB11 9 24 PGED1/AN5/C1IN1-/RP35/RB3
RPI44/RB12 10 23 PGEC1/AN4/C1IN1+/RPI34/RB2
RPI45/CTPLS/RB13 11 12 13 14 15 16 17 18 19 20 21 22
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
TDO/RA10
TDI/RA7
AN0/OA2OUT/RA0
RPI46/T3CK/RB14
RPI47/T5CK/RB15
AVDD
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
MCLR
AVSS
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
CVREF2O/SDO1/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SCL1/RPI53/RC5
SDI1/RPI25/RA9
RP39/INT0/RB7
VDD
44 43 42 41 40 39 38 37 36 35 34 33 VSS FLT32/SCL2/RP36/RB4
TMS/ASDA1/RP41/RB9(4) 1 32 SDA2/RPI24/RA8
RP54/RC6 2 31 OSC2/CLKO/RA3
RP55/RC7 3 30 OSC1/CLKI/RA2
RP56/RC8 4 29 VSS
RP57/RC9 5 dsPIC33EPXXXMC204/504 28 VDD
VSS 6 PIC24EPXXXMC204 27 AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
VCAP 7 26 AN7/C3IN1-/C4IN1-/RC1
RP42/PWM3H/RB10 8 25 AN6/OA3OUT/C4IN1+/OCFB/RC0
RP43/PWM3L/RB11 9 24 PGED1/AN5/C1IN1-/RP35/RB3
RPI44/PWM2H/RB12 10 23 PGEC1/AN4/C1IN1+/RPI34/RB2
RPI45/PWM2L/CTPLS/RB13 11 12 13 14 15 16 17 18 19 20 21 22
TDO/RA10
TDI/RA7
RPI46/PWM1H/T3CK/RB14
AN0/OA2OUT/RA0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
RPI47/PWM1L/T5CK/RB15
AVDD
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
MCLR
AVSS
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
CVREF2O/SDO1/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SCL1/RPI53/RC5
SDI1/RPI25/RA9
RP39/INT0/RB7
VDD
44 43 42 41 40 39 38 37 36 35 34 VSS
TMS/ASDA1/RP41/RB9(4) 1 33 SCL2/RP36/RB4
RP54/RC6 2 32 SDA2/RPI24/RA8
RP55/RC7 3 31 OSC2/CLKO/RA3
RP56/RC8 4 30 OSC1/CLKI/RA2
RP57/RC9 5 29 VSS
VSS 6 dsPIC33EPXXXGP504 28 VDD
PIC24EPXXXGP204
VCAP 7 27 AN8/C3IN1+/U1RTS/BCLK1/RC2
RP42/RB10 8 26 AN7/C3IN1-/C4IN1-/RC1
RP43/RB11 9 25 AN6/OA3OUT/C4IN1+/OCFB/RC0
RPI44/RB12 10 24 PGED1/AN5/C1IN1-/RP35/RB3
RPI45/CTPLS/RB13 11 23 PGEC1/AN4/C1IN1+/RPI34/RB2
12 13 14 15 16 17 18 19 20 21 22
TDO/RA10
TDI/RA7
AN0/OA2OUT/RA0
RPI46/T3CK/RB14
RPI47/T5CK/RB15
AVDD
AN1/C2IN1+/RA1
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
MCLR
AVSS
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
CVREF2O/SDO1/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SCL1/RPI53/RC5
SDI1/RPI25/RA9
RP39/INT0/RB7
VDD
VSS
44 43 42 41 40 39 38 37 36 35 34
TMS/ASDA1/RP41/RB9(4) 1 33 FLT32/SCL2/RP36/RB4
RP54/RC6 2 32 SDA2/RPI24/RA8
RP55/RC7 3 31 OSC2/CLKO/RA3
RP56/RC8 4 30 OSC1/CLKI/RA2
RP57/RC9 5 29 VSS
dsPIC33EPXXXMC204/504
VSS 6 28 VDD
PIC24EPXXXMC204
VCAP 7 27 AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
RP42/PWM3H/RB10 8 26 AN7/C3IN1-/C4IN1-/RC1
RP43/PWM3L/RB11 9 25 AN6/OA3OUT/C4IN1+/OCFB/RC0
RPI44/PWM2H/RB12 10 24 PGED1/AN5/C1IN1-/RP35/RB3
RPI45/PWM2L/CTPLS/RB13 11 23 PGEC1/AN4/C1IN1+/RPI34/RB2
12 13 14 15 16 17 18 19 20 21 22
MCLR
AVSS
RPI47/PWM1L/T5CK/RB15
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
TDO/RA10
TDI/RA7
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
RPI46/PWM1H/T3CK/RB14
AVDD
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
CVREF2O/SDO1/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SCL1/RPI53/RC5
SDI1/RPI25/RA9
RP39/INT0/RB7
VDD
VSS
N/C
48 47 46 45 44 43 42 41 40 39 38 37
TMS/ASDA1/RP41/RB9(4) 1 36 SCL2/RP36/RB4
RP54/RC6 2 35 SDA2/RPI24/RA8
RP55/RC7 3 34 OSC2/CLKO/RA3
RP56/RC8 4 33 OSC1/CLKI/RA2
RP57/RC9 5 32 N/C
N/C 8 29 AN8/C3IN1+/U1RTS/BCLK1/RC2
RP42/RB10 9 28 AN7/C3IN1-/C4IN1-/RC1
RP43/RB11 10 27 AN6/OA3OUT/C4IN1+/OCFB/RC0
RPI44/RB12 11 26 PGED1/AN5/C1IN1-/RP35/RB3
RPI45/CTPLS/RB13 12 25 PGEC1/AN4/C1IN1+/RPI34/RB2
13 14 15 16 17 18 19 20 21 22 23 24
TDO/RA10
TDI/RA7
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
AVDD
AN0/OA2OUT/RA0
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
AN1/C2IN1+/RA1
RPI46/T3CK/RB14
RPI47/T5CK/RB15
MCLR
N/C
AVSS
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
CVREF2O/SDO1/RP20/T1CK/RA4
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SCL1/RPI53/RC5
SDI1/RPI25/RA9
RP39/INT0/RB7
VDD
VSS
N/C
48 47 46 45 44 43 42 41 40 39 38 37
TMS/ASDA1/RP41/RB9(4) 1 36 FLT32/SCL2/RP36/RB4
RP54/RC6 2 35 SDA2/RPI24/RA8
RP55/RC7 3 34 OSC2/CLKO/RA3
RP56/RC8 4 33 OSC1/CLKI/RA2
RP57/RC9 5 32 N/C
N/C 8 29 AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
RP42/PWM3H/RB10 9 28 AN7/C3IN1-/C4IN1-/RC1
RP43/PWM3L/RB11 10 27 AN6/OA3OUT/C4IN1+/OCFB/RC0
RPI44/PWM2H/RB12 11 26 PGED1/AN5/C1IN1-/RP35/RB3
RPI45/PWM2L/CTPLS/RB13 12 25 PGEC1/AN4/C1IN1+/RPI34/RB2
13 14 15 16 17 18 19 20 21 22 23 24
AN0/OA2OUT/RA0
TDO/RA10
TDI/RA7
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
RPI47/PWM1L/T5CK/RB15
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
RPI46/PWM1H/T3CK/RB14
AN1/C2IN1+/RA1
MCLR
N/C
AVSS
AVDD
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
TMS/ASDA1/RP41/RB9(4)
RPI45/CTPLS/RB13
RPI44/RB12
RP42/RB10
RP43/RB11
RPI96/RF0
TDO/RA10
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
RP97/RF1
VCAP
RD6
RD5
VDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
TDI/RA7 1 48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
RPI46/T3CK/RB14 2 47 RC13
RPI47/T5CK/RB15 3 46 RP39/INT0/RB7
RP118/RG6 4 45 RPI58/RC10
RPI119/RG7 5 44 PGEC2/ASCL2/RP38/RB6
dsPIC33EP64GP506
RP120/RG8 6 43 PGED2/ASDA2/RP37/RB5
dsPIC33EP128GP506
MCLR 7 dsPIC33EP256GP506 42 RD8
RPI121/RG9 8 dsPIC33EP512GP506 41 VSS
VSS 9 PIC24EP64GP206 40 OSC2/CLKO/RC15
VDD 10 PIC24EP128GP206 39 OSC1/CLKI/RC12
AN10/RPI28/RA12 11 PIC24EP256GP206 38 VDD
AN9/RPI27/RA11 12 PIC24EP512GP206 37 SCL1/RPI53/RC5
AN0/OA2OUT/RA0 13 36 SDA1/RPI52/RC4
AN1/C2IN1+/RA1 14 35 SCK1/RPI51/RC3
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 34 SDI1/RPI25/RA9
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16 33 CVREF2O/SDO1/RP20/T1CK/RA4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVSS
VSS
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AVDD
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/RC2
AN11/C1IN2-(3)/U1CTS/RC11
VDD
AN12/C2IN2-(3)/U2RTS/BCLK2/RE12
AN13/C3IN2-(3)/U2CTS/RE13
AN14/RPI94/RE14
AN15/RPI95/RE15
SDA2/RPI24/RA8
SCL2/RP36/RB4
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
RPI45/PWM2L/CTPLS/RB13
TMS/ASDA1/RP41/RB9(4)
RPI44/PWM2H/RB12
RP42/PWM3H/RB10
RP43/PWM3L/RB11
RPI96/RF0
TDO/RA10
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
RP97/RF1
VCAP
RD6
RD5
VDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
TDI/RA7 1 48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
RPI46/PWM1H/T3CK/RB14 2 47 RC13
RPI47/PWM1L/T5CK/RB15 3 46 RP39/INT0/RB7
RP118/RG6 4 45 RPI58/RC10
RPI119/RG7 5 dsPIC33EP64MC206/506 44 PGEC2/ASCL2/RP38/RB6
RP120/RG8 6 dsPIC33EP128MC206/506 43 PGED2/ASDA2/RP37/RB5
MCLR 7 dsPIC33EP256MC206/506 42 RD8
RPI121/RG9 8 dsPIC33EP512MC206/506 41 VSS
VSS 9 PIC24EP64MC206 40 OSC2/CLKO/RC15
VDD 10 PIC24EP128MC206 39 OSC1/CLKI/RC12
AN10/RPI28/RA12 11 PIC24EP256MC206 38 VDD
AN9/RPI27/RA11 12 PIC24EP512MC206 37 SCL1/RPI53/RC5
AN0/OA2OUT/RA0 13 36 SDA1/RPI52/RC4
AN1/C2IN1+/RA1 14 35 SCK1/RPI51/RC3
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 34 SDI1/RPI25/RA9
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16 33 CVREF2O/SDO1/RP20/T1CK/RA4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD
VDD
PGEC1/AN4/C1IN1+/RPI34/RB2
AVSS
AN6/OA3OUT/C4IN1+/OCFB/RC0
VSS
PGED1/AN5/C1IN1-/RP35/RB3
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
AN11/C1IN2-(3)/U1CTS/FLT4/RC11
AN12/C2IN2-(3)/U2RTS/BCLK2/RE12
AN13/C3IN2-(3)/U2CTS/RE13
AN14/RPI94/RE14
AN15/RPI95/RE15
FLT32/SCL2/RP36/RB4
SDA2/RPI24/RA8
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
TMS/ASDA1/RP41/RB9(5)
RPI45/CTPLS/RB13
RPI44/RB12
RP42/RB10
RP43/RB11
RPI96/RF0
TDO/RA10
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
RP97/RF1
VCAP
RD6
RD5
VDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
TDI/RA7 1 48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
RPI46/T3CK/RB14 2 47 RC13
RPI47/T5CK/RB15 3 46 RP39/INT0/RB7
RP118/RG6 4 45 RPI58/RC10
RPI119/RG7 5 44 PGEC2/ASCL2/RP38/RB6
dsPIC33EP64GP506
RP120/RG8 6 43 PGED2/ASDA2/RP37/RB5
dsPIC33EP128GP506
MCLR 7 42 RD8
dsPIC33EP256GP506
RPI121/RG9 8 41 VSS
dsPIC33EP512GP506
VSS 9 40 OSC2/CLKO/RC15
PIC24EP64GP206
VDD 10 39 OSC1/CLKI/RC12
PIC24EP128GP206
AN10/RPI28/RA12 11 38 VDD
PIC24EP256GP206
AN9/RPI27/RA11 12 37 SCL1/RPI53/RC5
PIC24EP512GP206
AN0/OA2OUT/RA0 13 36 SDA1/RPI52/RC4
AN1/C2IN1+/RA1 14 35 SCK1/RPI51/RC3
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 34 SDI1/RPI25/RA9
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16 33 CVREF2O/SDO1/RP20/T1CK/RA4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVSS
VSS
AN12/C2IN2-(3)/U2RTS/BCLK2/RE12
SDA2/RPI24/RA8
PGEC1/AN4/C1IN1+/RPI34/RB2
AN6/OA3OUT/C4IN1+/OCFB/RC0
PGED1/AN5/C1IN1-/RP35/RB3
AN7/C3IN1-/C4IN1-/RC1
AN11/C1IN2-(3)/U1CTS/RC11
AN13/C3IN2-(3)/U2CTS/RE13
AN14/RPI94/RE14
AN15/RPI95/RE15
AN8/C3IN1+/U1RTS/BCLK1/RC2
SCL2/RP36/RB4
AVDD
VDD
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: This pin is not available as an input when OPMODE (CMxCON<10>) = 1.
4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
5: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
RPI45/PWM2L/CTPLS/RB13
TMS/ASDA1/RP41/RB9(5)
RPI44/PWM2H/RB12
RP42/PWM3H/RB10
RP43/PWM3L/RB11
RPI96/RF0
TDO/RA10
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
RP97/RF1
VCAP
RD6
RD5
VDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
TDI/RA7 1 48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
RPI46/PWM1H/T3CK/RB14 2 47 RC13
RPI47/PWM1L/T5CK/RB15 3 46 RP39/INT0/RB7
RP118/RG6 4 45 RPI58/RC10
RPI119/RG7 5 dsPIC33EP64MC206/506 44 PGEC2/ASCL2/RP38/RB6
RP120/RG8 6 dsPIC33EP128MC206/506 43 PGED2/ASDA2/RP37/RB5
MCLR 7 dsPIC33EP256MC206/506 42 RD8
RPI121/RG9 8 dsPIC33EP512MC206/506 41 VSS
VSS 9 PIC24EP64MC206 40 OSC2/CLKO/RC15
VDD 10 PIC24EP128MC206 39 OSC1/CLKI/RC12
AN10/RPI28/RA12 11 PIC24EP256MC206 38 VDD
AN9/RPI27/RA11 12 PIC24EP512MC206 37 SCL1/RPI53/RC5
AN0/OA2OUT/RA0 13 36 SDA1/RPI52/RC4
AN1/C2IN1+/RA1 14 35 SCK1/RPI51/RC3
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 34 SDI1/RPI25/RA9
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16 33 CVREF2O/SDO1/RP20/T1CK/RA4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD
VDD
PGEC1/AN4/C1IN1+/RPI34/RB2
AVSS
AN6/OA3OUT/C4IN1+/OCFB/RC0
VSS
PGED1/AN5/C1IN1-/RP35/RB3
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
AN11/C1IN2-(3)/U1CTS/FLT4/RC11
AN12/C2IN2-(3)/U2RTS/BCLK2/RE12
AN13/C3IN2-(3)/U2CTS/RE13
AN14/RPI94/RE14
AN15/RPI95/RE15
SDA2/RPI24/RA8
FLT32/SCL2/RP36/RB4
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: This pin is not available as an input when OPMODE (CMxCON<10>) = 1.
4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
5: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 25
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers and Microcontrollers ......................................................... 29
3.0 CPU ............................................................................................................................................................................................ 35
4.0 Memory Organization ................................................................................................................................................................. 45
5.0 Flash Program Memory ............................................................................................................................................................ 119
6.0 Resets ..................................................................................................................................................................................... 123
7.0 Interrupt Controller ................................................................................................................................................................... 127
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 139
9.0 Oscillator Configuration ............................................................................................................................................................ 153
10.0 Power-Saving Features ............................................................................................................................................................ 163
11.0 I/O Ports ................................................................................................................................................................................... 173
12.0 Timer1 ...................................................................................................................................................................................... 203
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 207
14.0 Input Capture............................................................................................................................................................................ 213
15.0 Output Compare ....................................................................................................................................................................... 219
16.0 High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) ....................................... 225
17.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)........... 249
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 265
19.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 273
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 281
21.0 Enhanced CAN (ECAN™) Module (dsPIC33EPXXXGP/MC50X Devices Only) ..................................................................... 287
22.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 315
23.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 321
24.0 Peripheral Trigger Generator (PTG) Module ............................................................................................................................ 337
25.0 Op Amp/Comparator Module ................................................................................................................................................... 355
26.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 373
27.0 Special Features ...................................................................................................................................................................... 379
28.0 Instruction Set Summary .......................................................................................................................................................... 387
29.0 Development Support............................................................................................................................................................... 397
30.0 Electrical Characteristics .......................................................................................................................................................... 401
31.0 High-Temperature Electrical Characteristics ............................................................................................................................ 467
32.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 475
33.0 Packaging Information.............................................................................................................................................................. 479
Appendix A: Revision History............................................................................................................................................................. 507
Index ................................................................................................................................................................................................. 517
The Microchip Web Site ..................................................................................................................................................................... 525
Customer Change Notification Service .............................................................................................................................................. 525
Customer Support .............................................................................................................................................................................. 525
Product Identification System............................................................................................................................................................. 527
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family Ref-
erence Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of the
dsPIC33EP64MC506 product page of the
Microchip web site (www.microchip.com)
or select a family reference manual section
from the following list.
In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.
• “Introduction” (DS70573)
• “CPU” (DS70359)
• “Data Memory” (DS70595)
• “Program Memory” (DS70613)
• “Flash Programming” (DS70609)
• “Interrupts” (DS70600)
• “Oscillator” (DS70580)
• “Reset” (DS70602)
• “Watchdog Timer and Power-Saving Modes” (DS70615)
• “I/O Ports” (DS70598)
• “Timers” (DS70362)
• “Input Capture” (DS70352)
• “Output Compare” (DS70358)
• “High-Speed PWM” (DS70645)
• “Quadrature Encoder Interface (QEI)” (DS70601)
• “Analog-to-Digital Converter (ADC)” (DS70621)
• “UART” (DS70582)
• “Serial Peripheral Interface (SPI)” (DS70569)
• “Inter-Integrated Circuit (I2C™)” (DS70330)
• “Enhanced Controller Area Network (ECAN™)” (DS70353)
• “Direct Memory Access (DMA)” (DS70348)
• “CodeGuard™ Security” (DS70634)
• “Programming and Diagnostics” (DS70608)
• “Op Amp/Comparator” (DS70357)
• “Programmable Cyclic Redundancy Check (CRC)” (DS70346)
• “Device Configuration” (DS70618)
• “Peripheral Trigger Generator (PTG)” (DS70669)
• “Charge Time Measurement Unit (CTMU)” (DS70661)
PORTA
CPU
16
Refer to Figure 3-1 for CPU diagram details.
PORTB
PORTC
Power-up
Timer
Oscillator PORTD
Timing
Generation Start-up
Timer
OSC1/CLKI
POR/BOR PORTE
MCLR
Watchdog 16
Timer
VDD, VSS
AVDD, AVSS PORTF
PORTG
Op Amp/ Input Output I2C1,
PTG ECAN1(2) ADC
Comparator Capture Compare I2C2
Remappable
Pins
Peripheral Modules
Note 1: This feature or peripheral is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2: This feature or peripheral is only available on dsPIC33EPXXXGP/MC50X devices.
VDD
VCAP
VSS
R
R1 (10 µF is recommended), 16V connected to ground. The
MCLR type can be ceramic or tantalum. See Section 30.0
“Electrical Characteristics” for additional information.
C
The placement of this capacitor should be close to the
dsPIC33E/PIC24E
VCAP pin. It is recommended that the trace length not
VSS VDD exceeds one-quarter inch (6 mm). See Section 27.3
“On-Chip Voltage Regulator” for details.
VDD VSS
0.1 µF 0.1 µF
AVDD
AVSS
VDD
Ceramic Ceramic
IPFC
VINPUT
VOUTPUT
k1 k3
k2 FET
Driver
dsPIC33EP
12V Input
5V Output
I5V
k7 FET k1 k2
Driver
dsPIC33EP
k6
k7 FET FET
Driver Driver
ADC
PWM
PWM
PWM
PWM
PWM FET
Channel Driver
PWM
Op Amp/Comparator k3
dsPIC33EP
Op Amp/Comparator k4
Op Amp/Comparator k5
ADC Channel
VOUT+
|VAC|
k4 VAC k3
k1 k2
VOUT-
FET FET
Driver Driver
dsPIC33EP
ADC Channel
dsPIC33EP/PIC24EP
BLDC
PWM3H
PWM3L
PWM2H 3-Phase
PWM2L Inverter
PWM1H
PWM1L
R49 R41 R34 R36
FLTx Fault
R44
AN2 R52
Demand
AN3
AN4
AN5
Phase Terminal Voltage Feedback
X Address Bus
Y Data Bus(1)
X Data Bus
16 16 16
16
16 16
Y Address Bus
24 PCU PCH PCL X RAGU
Program Counter 16 X WAGU
Stack Loop
Control Control
Address Latch Logic Logic
Y AGU(1)
Program Memory
16 EA MUX
Data Latch
16
ROM Latch
16 24
IR
24
16 Literal Data
16 x 16
W Register Array 16
16 16
Divide
DSP Support
Engine(1)
16-Bit ALU
Peripheral
Modules
3.5 Programmer’s Model MC20X devices contain control registers for Modulo
Addressing (dsPIC33EPXXXMC20X/50X and
The programmer’s model for the dsPIC33EPXXXGP50X devices only), Bit-Reversed
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X Addressing (dsPIC33EPXXXMC20X/50X and
and PIC24EPXXXGP/MC20X is shown in Figure 3-2. dsPIC33EPXXXGP50X devices only) and interrupts.
All registers in the programmer’s model are memory These registers are described in subsequent
mapped and can be manipulated directly by sections of this document.
instructions. Table 3-1 lists a description of each
register. All registers associated with the programmer’s model
are memory mapped, as shown in Table 4-1.
In addition to the registers contained in the
programmer’s model, the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
Nested DO Stack
SPLIM 0 Stack Pointer Limit
PC23 PC0
0 0 Program Counter
7 0
TBLPAG Data Table Page Address
9 0
DSRPAG X Data Space Read Page Address
8 0
DSWPAG X Data Space Write Page Address
15 0
RCOUNT Repeat Loop Counter
15 0
DCOUNT
DO Loop Counter and Stack(1)
23 0
0 DOSTART 0 DO Loop Start Address and Stack(1)
23 0
0 DOEND 0 DO Loop End Address and Stack(1)
15 0
CORCON CPU Core Control Register
SRL
OA(1) OB(1) SA(1) SB(1) OAB(1) SAB(1) DA(1) DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register
Note 1: This feature or bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
Flash Memory
(11K instructions)
0x0057EA
0x0057EC
Flash Configuration
Bytes 0x0057FE
0x005800
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800FF6
0x800FF8
USERID
Configuration Memory Space
0x800FFE
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID 0xFF0002
0xFF0004
Reserved
0xFFFFFE
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800FF6
0x800FF8
USERID
Configuration Memory Space
0x800FFE
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID 0xFF0002
0xFF0004
Reserved
0xFFFFFE
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800FF6
0x800FF8
USERID
Configuration Memory Space
0x800FFE
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID 0xFF0002
0xFF0004
Reserved
0xFFFFFE
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800FF6
0x800FF8
USERID
Configuration Memory Space
0x800FFE
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID 0xFF0002
0xFF0004
Reserved
0xFFFFFE
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800FF6
0x800FF8
USERID
Configuration Memory Space
0x800FFE
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID 0xFF0002
0xFF0004
Reserved
0xFFFFFE
Program Memory
Instruction Width
‘Phantom’ Byte
(read as ‘0’)
4.2 Data Address Space All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ care must be taken when mixing byte and word
50X and PIC24EPXXXGP/MC20X CPU has a separate operations, or translating from 8-bit MCU code. If a
16-bit-wide data memory space. The Data Space is misaligned read or write is attempted, an address error
accessed using separate Address Generation Units trap is generated. If the error occurred on a read, the
(AGUs) for read and write operations. The data instruction underway is completed. If the error occurred
memory maps, which are presented by device family on a write, the instruction is executed but the write does
and memory size, are shown in Figure 4-7 through not occur. In either case, a trap is then executed,
Figure 4-16. allowing the system and/or user application to examine
All Effective Addresses (EAs) in the data memory space the machine state prior to execution of the address
are 16 bits wide and point to bytes within the Data Fault.
Space. This arrangement gives a base Data Space All byte loads into any W register are loaded into the
address range of 64 Kbytes (32K words). LSB. The MSB is not modified.
The base Data Space address is used in conjunction A Sign-Extend (SE) instruction is provided to allow user
with a Read or Write Page register (DSRPAG or applications to translate 8-bit signed data to 16-bit
DSWPAG) to form an Extended Data Space, which has signed values. Alternatively, for 16-bit unsigned data,
a total address range of 16 Mbytes. user applications can clear the MSB of any W register
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X by executing a Zero-Extend (ZE) instruction on the
and PIC24EPXXXGP/MC20X devices implement up to appropriate address.
52 Kbytes of data memory (4 Kbytes of data memory
for Special Function Registers and up to 48 Kbytes of 4.2.3 SFR SPACE
data memory for RAM). If an EA points to a location The first 4 Kbytes of the Near Data Space, from 0x0000
outside of this area, an all-zero word or byte is returned. to 0x0FFF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
4.2.1 DATA SPACE WIDTH dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
The data memory space is organized in byte- and PIC24EPXXXGP/MC20X core and peripheral
addressable, 16-bit-wide blocks. Data is aligned in data modules for controlling the operation of the device.
memory and registers as 16-bit words, but all Data SFRs are distributed among the modules that they
Space EAs resolve to bytes. The Least Significant control and are generally grouped together by module.
Bytes (LSBs) of each word have even addresses, while Much of the SFR space contains unused addresses;
the Most Significant Bytes (MSBs) have odd these are read as ‘0’.
addresses.
Note: The actual set of peripheral features and
4.2.2 DATA MEMORY ORGANIZATION interrupts varies by the device. Refer to
AND ALIGNMENT the corresponding device tables and
pinout diagrams for device-specific
To maintain backward compatibility with PIC ® MCU
information.
devices and improve Data Space memory
usage efficiency, the dsPIC33EPXXXGP50X,
4.2.4 NEAR DATA SPACE
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X instruction set supports both word and byte The 8-Kbyte area, between 0x0000 and 0x1FFF, is
operations. As a consequence of byte accessibility, all referred to as the Near Data Space. Locations in this
Effective Address calculations are internally scaled to space are directly addressable through a 13-bit abso-
step through word-aligned memory. For example, the lute address field within all memory direct instructions.
core recognizes that Post-Modified Register Indirect Additionally, the whole Data Space is addressable
Addressing mode [Ws++] results in a value of Ws + 1 using MOV instructions, which support Memory Direct
for byte operations and Ws + 2 for word operations. Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
A data byte read, reads the complete word that
register as an Address Pointer.
contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSB of the data path. That is, data memory and
registers are organized as two parallel, byte-wide
entities with shared (word) address decode but
separate write lines. Data byte writes only write to the
corresponding side of the array or register that matches
the byte address.
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE
0x0FFF
0x1001 0x1000
0x1FFF 0x1FFE
0x2001 0x2000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory Space
(PSV)
0xFFFF 0xFFFE
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE
0x0FFF
0x1001 0x1000
8-Kbyte
Near
Data Space
X Data RAM (X)
0x2FFF 0x2FFE
0x3001 0x3000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory Space
(PSV)
0xFFFF 0xFFFE
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE 8-Kbyte
0x0FFF
0x1001 0x1000 Near
Data Space
0x1FFF 0x1FFE
0x2001 X Data RAM (X)
0x2000
0x4FFF 0x4FFE
0x5001 0x5000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory Space
(PSV)
0xFFFF 0xFFFE
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE 8-Kbyte
0x0FFF
0x1001 0x1000 Near
Data Space
0x1FFF 0x1FFE
0x2001 X Data RAM (X)
0x2000
0x7FFF 0x7FFE
0x8001 Y Data RAM (Y)
0x8000
0x8FFF 0x8FFE
0x9001 0x9000
Optionally
Mapped
into Program
Memory Space
X Data
(PSV)
Unimplemented (X)
0xFFFF 0xFFFE
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE 8-Kbyte
0x0FFF
0x1001 0x1000 Near
Data Space
0x1FFF 0x1FFE
0x2001 0x2000
X Data RAM (X)
48-Kbyte 0x7FFF 0x7FFE
SRAM Space 0x8001 0x8000
0x8FFF 0x8FFE
0x9001 0x9000
Y Data RAM (Y)
0xEFFF 0xEFFE
0xD001 0xD000
Optionally
Mapped
into Program
Memory Space
(PSV)
X Data
Unimplemented (X)
0xFFFF 0xFFFE
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte SFR Space
SFR Space 0x0FFE
0x0FFF
0x1001 0x1000
8-Kbyte
Near
4-Kbyte X Data RAM (X) Data Space
SRAM Space
0x1FFF 0x1FFE
0x2001 0x2000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory Space
(PSV)
0xFFFF 0xFFFE
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte SFR Space
SFR Space 0x0FFE
0x0FFF
0x1001 0x1000
8-Kbyte
Near
Data Space
X Data RAM (X)
0x2FFF 0x2FFE
0x3001 0x3000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory Space
(PSV)
0xFFFF 0xFFFE
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE 8-Kbyte
0x0FFF
0x1001 0x1000 Near
Data Space
0x1FFF 0x1FFE
0x2001 X Data RAM (X)
0x2000
16-Kbyte
SRAM Space
0x4FFF 0x4FFE
0x5001 0x5000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory Space
(PSV)
0xFFFF 0xFFFE
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE 8-Kbyte
0x0FFF
0x1001 0x1000 Near
Data Space
0x1FFF 0x1FFE
0x2001 X Data RAM (X)
0x2000
32-Kbyte
SRAM Space
0x7FFF 0x7FFE
0x8001 0x8000
0x8FFF 0x8FFE
0x9001 0x9000
Optionally
Mapped
into Program
Memory Space
X Data (PSV)
Unimplemented (X)
0xFFFF 0xFFFE
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE 8-Kbyte
0x0FFF
0x1001 0x1000 Near
Data Space
0x1FFF 0x1FFE
0x2001 X Data RAM (X)
0x2000
48-Kbyte
SRAM Space
0x7FFF 0x7FFE
0x8001 0x8000
0xEFFF 0xEFFE
0xD001 0xD000
Optionally
Mapped
into Program
Memory Space
(PSV)
X Data
Unimplemented (X)
0xFFFF 0xFFFE
0000
DCOUNT 0038 DCOUNT<15:0> 0000
DOSTARTL 003A DOSTARTL<15:1> — 0000
DOSTARTH 003C — — — — — — — — — — DOSTARTH<5:0> 0000
DOENDL 003E DOENDL<15:1> — 0000
DOENDH 0040 — — — — — — — — — — DOENDH<5:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED)
DS70000657H-page 64
TABLE 4-2: CPU CORE REGISTER MAP FOR PIC24EPXXXGP/MC20X DEVICES ONLY
IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF — — SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — — — — — — — — — MI2C2IF SI2C2IF — 0000
IFS4 0808 — — CTMUIF — — — — — — — — — CRCIF U2EIF U1EIF — 0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000
IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF — 0000
IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE — — SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — — — — — — — — — MI2C2IE SI2C2IE — 0000
IEC4 0828 — — CTMUIE — — — — — — — — — CRCIE U2EIE U1EIE — 0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000
IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE — 0000
IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444
IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444
IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444
IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444
IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444
IPC8 0850 — — — — — — — — — SPI2IP<2:0> — SPI2EIP<2:0> 0044
IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444
2011-2013 Microchip Technology Inc.
TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY
IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF — — SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — QEI1IF PSEMIF — — — — — — MI2C2IF SI2C2IF — 0000
IFS4 0808 — — CTMUIF — — — — — — — — — CRCIF U2EIF U1EIF — 0000
IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — — 0000
IFS6 080C — — — — — — — — — — — — — — — PWM3IF 0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000
IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF — 0000
IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE — — SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — QEI1IE PSEMIE — — — — — — MI2C2IE SI2C2IE — 0000
IEC4 0828 — — CTMUIE — — — — — — — — — CRCIE U2EIE U1EIE — 0000
IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — — 0000
IEC6 082C — — — — — — — — — — — — — — — PWM3IE 0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000
IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE — 0000
IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444
IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444
IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444
IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444
IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444
IPC8 0850 — — — — — — — — — SPI2IP<2:0> — SPI2EIP<2:0> 0044
IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444
IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440
DS70000657H-page 67
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY
IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — — — — — — — — — MI2C2IF SI2C2IF — 0000
IFS4 0808 — — CTMUIF — — — — — — C1TXIF — — CRCIF U2EIF U1EIF — 0000
IFS6 080C — — — — — — — — — — — — — — — PWM3IF 0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000
IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF — 0000
IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — — — — — — — — — MI2C2IE SI2C2IE — 0000
IEC4 0828 — — CTMUIE — — — — — — C1TXIE — — CRCIE U2EIE U1EIE — 0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000
IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE — 0000
IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444
IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444
IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444
IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444
IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444
IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444
IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444
IPC11 0856 — — — — — — — — — — — — — — — — 0000
IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440
IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440
IPC17 0862 — — — — — C1TXIP<2:0> — — — — — — — — 0400
DS70000657H-page 69
INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000
INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP 8000
INTCON3 08C4 — — — — — — — — — — DAE DOOVR — — — — 0000
INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000
INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc.
2011-2013 Microchip Technology Inc.
TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY
IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF — — SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — QEI1IF PSEMIF — — — — — — MI2C2IF SI2C2IF — 0000
IFS4 0808 — — CTMUIF — — — — — — — — — CRCIF U2EIF U1EIF — 0000
IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — — 0000
IFS6 080C — — — — — — — — — — — — — — — PWM3IF 0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000
IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF — 0000
IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE — — SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — QEI1IE PSEMIE — — — — — — MI2C2IE SI2C2IE — 0000
IEC4 0828 — — CTMUIE — — — — — — — — — CRCIE U2EIE U1EIE — 0000
IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — — 0000
IEC6 082C — — — — — — — — — — — — — — — PWM3IE 0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000
IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE — 0000
IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444
IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444
IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444
IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444
IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444
IPC8 0850 — — — — — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 0444
IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444
IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440
DS70000657H-page 71
TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY
IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — QEI1IF PSEMIF — — — — — — MI2C2IF SI2C2IF — 0000
IFS4 0808 — — CTMUIF — — — — — — C1TXIF — — CRCIF U2EIF U1EIF — 0000
IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — — 0000
IFS6 080C — — — — — — — — — — — — — — — PWM3IF 0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000
IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF — 0000
IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — QEI1IE PSEMIE — — — — — — MI2C2IE SI2C2IE — 0000
IEC4 0828 — — CTMUIE — — — — — — C1TXIE — — CRCIE U2EIE U1EIE — 0000
IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — — 0000
IEC6 082C — — — — — — — — — — — — — — — PWM3IE 0000
IEC7 082E — — — — — — — — — — — — — — — — 0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000
IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE — 0000
IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444
IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444
IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444
IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444
IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444
IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444
IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444
DS70000657H-page 73
OC1CON1 0900 — — OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000
OC1CON2 0902 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C
OC1RS 0904 Output Compare 1 Secondary Register xxxx
OC1R 0906 Output Compare 1 Register xxxx
OC1TMR 0908 Timer Value 1 Register xxxx
OC2CON1 090A — — OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000
OC2CON2 090C FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C
OC2RS 090E Output Compare 2 Secondary Register xxxx
OC2R 0910 Output Compare 2 Register xxxx
OC2TMR 0912 Timer Value 2 Register xxxx
OC3CON1 0914 — — OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000
OC3CON2 0916 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C
OC3RS 0918 Output Compare 3 Secondary Register xxxx
OC3R 091A Output Compare 3 Register xxxx
OC3TMR 091C Timer Value 3 Register xxxx
OC4CON1 091E — — OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000
OC4CON2 0920 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C
OC4RS 0922 Output Compare 4 Secondary Register xxxx
OC4R 0924 Output Compare 4 Register xxxx
OC4TMR 0926 Timer Value 4 Register xxxx
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000657H-page 77
DS70000657H-page 78
PTGCST 0AC0 PTGEN — PTGSIDL PTGTOGL — PTGSWT PTGSSEN PTGIVIS PTGSTRT PTGWTO — — — — PTGITM<1:0> 0000
PTGCON 0AC2 PTGCLK<2:0> PTGDIV<4:0> PTGPWD<3:0> — PTGWDT<2:0> 0000
PTGBTE 0AC4 ADCTS<4:1> IC4TSS IC3TSS IC2TSS IC1TSS OC4CS OC3CS OC2CS OC1CS OC4TSS OC3TSS OC2TSS OC1TSS 0000
PTGHOLD 0AC6 PTGHOLD<15:0> 0000
PTGT0LIM 0AC8 PTGT0LIM<15:0> 0000
PTGT1LIM 0ACA PTGT1LIM<15:0> 0000
PTGSDLIM 0ACC PTGSDLIM<15:0> 0000
PTGC0LIM 0ACE PTGC0LIM<15:0> 0000
PTGC1LIM 0AD0 PTGC1LIM<15:0> 0000
PTGADJ 0AD2 PTGADJ<15:0> 0000
PTGL0 0AD4 PTGL0<15:0> 0000
PTGQPTR 0AD6 — — — — — — — — — — — PTGQPTR<4:0> 0000
PTGQUE0 0AD8 STEP1<7:0> STEP0<7:0> 0000
PTGQUE1 0ADA STEP3<7:0> STEP2<7:0> 0000
PTGQUE2 0ADC STEP5<7:0> STEP4<7:0> 0000
PTGQUE3 0ADE STEP7<7:0> STEP6<7:0> 0000
PTGQUE4 0AE0 STEP9<7:0> STEP8<7:0> 0000
PTGQUE5 0AE2 STEP11<7:0> STEP10<7:0> 0000
PTGQUE6 0AE4 STEP13<7:0> STEP12<7:0> 0000
PTGQUE7 0AE6 STEP15<7:0> STEP14<7:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc.
2011-2013 Microchip Technology Inc.
TABLE 4-12: PWM REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
PTCON 0C00 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> 0000
PTCON2 0C02 — — — — — — — — — — — — — PCLKDIV<2:0> 0000
PTPER 0C04 PTPER<15:0> 00F8
SEVTCMP 0C06 SEVTCMP<15:0> 0000
MDC 0C0A MDC<15:0> 0000
CHOP 0C1A CHPCLKEN — — — — — CHOPCLK<9:0> 0000
PWMKEY 0C1E PWMKEY<15:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13: PWM GENERATOR 1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
All
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000
IOCON1 0C22 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC C000
FCLCON1 0C24 — CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000
PDC1 0C26 PDC1<15:0> FFF8
PHASE1 0C28 PHASE1<15:0> 0000
DTR1 0C2A — — DTR1<13:0> 0000
ALTDTR1 0C2C — — ALTDTR1<13:0> 0000
TRIG1 0C32 TRGCMP<15:0> 0000
TRGCON1 0C34 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000
LEBCON1 0C3A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000
LEBDLY1 0C3C — — — — LEB<11:0> 0000
AUXCON1 0C3E — — — — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000657H-page 79
DS70000657H-page 80
PWMCON2 0C40 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000
IOCON2 0C42 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC C000
FCLCON2 0C44 — CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 00F8
PDC2 0C46 PDC2<15:0> 0000
PHASE2 0C48 PHASE2<15:0> 0000
DTR2 0C4A — — DTR2<13:0> 0000
ALTDTR2 0C4C — — ALTDTR2<13:0> 0000
TRIG2 0C52 TRGCMP<15:0> 0000
TRGCON2 0C54 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000
LEBCON2 0C5A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000
LEBDLY2 0C5C — — — — LEB<11:0> 0000
AUXCON2 0C5E — — — — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-15: PWM GENERATOR 3 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
All
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
PWMCON3 0C60 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000
IOCON3 0C62 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC C000
FCLCON3 0C64 — CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 00F8
PDC3 0C66 PDC3<15:0> 0000
PHASE3 0C68 PHASE3<15:0> 0000
DTR3 0C6A — — DTR3<13:0> 0000
2011-2013 Microchip Technology Inc.
TABLE 4-16: QEI1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
QEI1CON 01C0 QEIEN — QEISIDL PIMOD<2:0> IMV<1:0> — INTDIV<2:0> CNTPOL GATEN CCM<1:0> 0000
QEI1IOC 01C2 QCAPEN FLTREN QFDIV<2:0> OUTFNC<1:0> SWPAB HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA 000x
QEI1STAT 01C4 — — PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN 0000
POS1CNTL 01C6 POSCNT<15:0> 0000
POS1CNTH 01C8 POSCNT<31:16> 0000
POS1HLD 01CA POSHLD<15:0> 0000
VEL1CNT 01CC VELCNT<15:0> 0000
INT1TMRL 01CE INTTMR<15:0> 0000
INT1TMRH 01D0 INTTMR<31:16> 0000
INT1HLDL 01D2 INTHLD<15:0> 0000
INT1HLDH 01D4 INTHLD<31:16> 0000
INDX1CNTL 01D6 INDXCNT<15:0> 0000
INDX1CNTH 01D8 INDXCNT<31:16> 0000
INDX1HLD 01DA INDXHLD<15:0> 0000
QEI1GECL 01DC QEIGEC<15:0> 0000
QEI1ICL 01DC QEIIC<15:0> 0000
QEI1GECH 01DE QEIGEC<31:16> 0000
QEI1ICH 01DE QEIIC<31:16> 0000
QEI1LECL 01E0 QEILEC<15:0> 0000
QEI1LECH 01E2 QEILEC<31:16> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000657H-page 81
DS70000657H-page 82
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx
U1RXREG 0226 — — — — — — — UART1 Receive Register 0000
U1BRG 0228 Baud Rate Generator Prescaler
2011-2013 Microchip Technology Inc.
0000
U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000
U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
U2TXREG 0234 — — — — — — — UART2 Transmit Register xxxx
U2RXREG 0236 — — — — — — — UART2 Receive Register 0000
U2BRG 0238 Baud Rate Generator Prescaler 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc.
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc.
TABLE 4-21: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 0 OR 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY
C1CTRL1 0400 — — CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — CANCAP — — WIN 0480
C1CTRL2 0402 — — — — — — — — — — — DNCNT<4:0> 0000
C1VEC 0404 — — — FILHIT<4:0> — ICODE<6:0> 0040
C1FCTRL 0406 DMABS<2:0> — — — — — — — — FSA<4:0> 0000
C1FIFO 0408 — — FBP<5:0> — — FNRB<5:0> 0000
C1INTF 040A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000
C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000
C1EC 040E TERRCNT<7:0> RERRCNT<7:0> 0000
C1CFG1 0410 — — — — — — — — SJW<1:0> BRP<5:0> 0000
C1CFG2 0412 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000
C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF
C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000
C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-22: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 0 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY
All
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
xxxx
C1TXD 0442 ECAN1 Transmit Data Word xxxx
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000657H-page 86
xxxx
C1RXF6EID 045A EID<15:8> EID<7:0> xxxx
C1RXF7SID 045C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx
C1RXF7EID 045E EID<15:8> EID<7:0> xxxx
C1RXF8SID 0460 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx
C1RXF8EID 0462 EID<15:8> EID<7:0> xxxx
C1RXF9SID 0464 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx
C1RXF9EID 0466 EID<15:8> EID<7:0> xxxx
C1RXF10SID 0468 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx
C1RXF10EID 046A EID<15:8> EID<7:0> xxxx
C1RXF11SID 046C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY (CONTINUED)
2011-2013 Microchip Technology Inc.
All
CRCCON1 0640 CRCEN — CSIDL VWORD<4:0> CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — 0000
CRCCON2 0642 — — — DWIDTH<4:0> — — — PLEN<4:0> 0000
CRCXORL 0644 X<15:1> — 0000
CRCXORH 0646 X<31:16> 0000
CRCDATL 0648 CRC Data Input Low Word 0000
CRCDATH 064A CRC Data Input High Word 0000
CRCWDATL 064C CRC Result Low Word 0000
CRCWDATH 064E CRC Result High Word 0000
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used in the operation of the programmable CRC module.
TABLE 4-25: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC202/502 AND PIC24EPXXXGP/MC202
DEVICES ONLY
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TABLE 4-26: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC203/503 AND PIC24EPXXXGP/MC203
DEVICES ONLY
2011-2013 Microchip Technology Inc.
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TABLE 4-27: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC204/504 AND PIC24EPXXXGP/MC204
DEVICES ONLY
TABLE 4-28: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC206/506 AND PIC24EPXXXGP/MC206
DEVICES ONLY
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TABLE 4-30: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TABLE 4-31: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY
TABLE 4-32: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY
All
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Resets
RCON 0740 TRAPR IOPUWR — — VREGSF — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1
OSCCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK IOLOCK LOCK — CF — — OSWEN Note 2
CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 0030
PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030
OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on the Configuration Fuses.
PMD1 0760 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — AD1MD 0000
PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — — CMPMD — — CRCMD — — — — — I2C2MD — 0000
PMD4 0766 — — — — — — — — — — — — REFOMD CTMUMD — — 0000
PMD6 076A — — — — — — — — — — — — — — — — 0000
DMA0MD
DMA1MD
PMD7 076C — — — — — — — — — — — PTGMD — — — 0000
DMA2MD
DMA3MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — — AD1MD 0000
PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — — CMPMD — — CRCMD — — — — — I2C2MD — 0000
PMD4 0766 — — — — — — — — — — — — REFOMD CTMUMD — — 0000
PMD6 076A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000
DMA0MD
DMA1MD
PMD7 076C — — — — — — — — — — — PTGMD — — — 0000
DMA2MD
DMA3MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc.
2011-2013 Microchip Technology Inc.
PMD1 0760 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD AD1MD 0000
PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — — CMPMD — — CRCMD — — — — — I2C2MD — 0000
PMD4 0766 — — — — — — — — — — — — REFOMD CTMUMD — — 0000
PMD6 076A — — — — — — — — — — — — — — — — 0000
DMA0MD
DMA1MD
PMD7 076C — — — — — — — — — — — PTGMD — — — 0000
DMA2MD
DMA3MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD AD1MD 0000
PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — — CMPMD — — CRCMD — — — — — I2C2MD — 0000
PMD4 0766 — — — — — — — — — — — — REFOMD CTMUMD — — 0000
PMD6 076A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000
DMA0MD
DMA1MD
PMD7 076C — — — — — — — — — — — PTGMD — — — 0000
DMA2MD
DMA3MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000657H-page 95
DS70000657H-page 96
PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — — AD1MD 0000
PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — — CMPMD — — CRCMD — — — — — I2C2MD — 0000
PMD4 0766 — — — — — — — — — — — — REFOMD CTMUMD — — 0000
PMD6 076A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000
DMA0MD
DMA1MD
PMD7 076C — — — — — — — — — — — PTGMD — — — 0000
DMA2MD
DMA3MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc.
2011-2013 Microchip Technology Inc.
CMSTAT 0A80 PSIDL — — — C4EVT C3EVT C2EVT C1EVT — — — — C4OUT C3OUT C2OUT C1OUT 0000
CVRCON 0A82 — CVR2OE — — — VREFSEL — — CVREN CVR1OE CVRR CVRSS CVR<3:0> 0000
CM1CON 0A84 CON COE CPOL — — OPMODE CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000
CM1MSKSRC 0A86 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM1MSKCON 0A88 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM1FLTR 0A8A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
CM2CON 0A8C CON COE CPOL — — OPMODE CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000
CM2MSKSRC 0A8E — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM2MSKCON 0A90 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM2FLTR 0A92 — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
CM3CON(1) 0A94 CON COE CPOL — — OPMODE CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000
CM3MSKSRC(1) 0A96 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM3MSKCON(1) 0A98 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM3FLTR(1) 0A9A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
CM4CON 0A9C CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000
CM4MSKSRC 0A9E — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM4MSKCON 0AA0 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM4FLTR 0AA2 — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These registers are unavailable on dsPIC33EPXXXGP502/MC502/MC202 and PIC24EP256GP/MC202 (28-pin) devices.
CTMUCON1 033A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000
CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0> — — 0000
CTMUICON 033E ITRIM<5:0> IRNG<1:0> — — — — — — — — 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000657H-page 97
DMA0CON 0B00 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000
DMA0REQ 0B02 FORCE — — — — — — — IRQSEL<7:0> 00FF
DMA0STAL 0B04 STA<15:0> 0000
DMA0STAH 0B06 — — — — — — — — STA<23:16> 0000
DMA0STBL 0B08 STB<15:0> 0000
DMA0STBH 0B0A — — — — — — — — STB<23:16> 0000
DMA0PAD 0B0C PAD<15:0> 0000
DMA0CNT 0B0E — — CNT<13:0> 0000
DMA1CON 0B10 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000
DMA1REQ 0B12 FORCE — — — — — — — IRQSEL<7:0> 00FF
DMA1STAL 0B14 STA<15:0> 0000
DMA1STAH 0B16 — — — — — — — — STA<23:16> 0000
DMA1STBL 0B18 STB<15:0> 0000
DMA1STBH 0B1A — — — — — — — — STB<23:16> 0000
DMA1PAD 0B1C PAD<15:0> 0000
DMA1CNT 0B1E — — CNT<13:0> 0000
DMA2CON 0B20 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000
DMA2REQ 0B22 FORCE — — — — — — — IRQSEL<7:0> 00FF
DMA2STAL 0B24 STA<15:0> 0000
DMA2STAH 0B26 — — — — — — — — STA<23:16> 0000
DMA2STBL 0B28 STB<15:0> 0000
DMA2STBH 0B2A — — — — — — — — STB<23:16> 0000
DMA2PAD 0B2C PAD<15:0> 0000
DMA2CNT 0B2E — — CNT<13:0> 0000
DMA3CON 0B30 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000
DMA3REQ 0B32 FORCE — — — — — — — IRQSEL<7:0> 00FF
DMA3STAL 0B34 STA<15:0> 0000
2011-2013 Microchip Technology Inc.
File All
TRISA 0E00 — — — TRISA12 TRISA11 TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 — — TRISA1 TRISA0 1F93
PORTA 0E02 — — — RA12 RA11 RA10 RA9 RA8 RA7 — — RA4 — — RA1 RA0 0000
LATA 0E04 — — — LATA12 LATA11 LATA10 LATA9 LATA8 LATA7 — — LATA4 — — LA1TA1 LA0TA0 0000
ODCA 0E06 — — — ODCA12 ODCA11 ODCA10 ODCA9 ODCA8 ODCA7 — — ODCA4 — — ODCA1 ODCA0 0000
CNENA 0E08 — — — CNIEA12 CNIEA11 CNIEA10 CNIEA9 CNIEA8 CNIEA7 — — CNIEA4 — — CNIEA1 CNIEA0 0000
CNPUA 0E0A — — — CNPUA12 CNPUA11 CNPUA10 CNPUA9 CNPUA8 CNPUA7 — — CNPUA4 — — CNPUA1 CNPUA0 0000
CNPDA 0E0C — — — CNPDA12 CNPDA11 CNPDA10 CNPDA9 CNPDA8 CNPDA7 — — CNPDA4 — — CNPDA1 CNPDA0 0000
ANSELA 0E0E — — — ANSA12 ANSA11 — — — — — — ANSA4 — — ANSA1 ANSA0 1813
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-47: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000
CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
ANSELB 0E1E — — — — — — — ANSB8 — — — — ANSB3 ANSB2 ANSB1 ANSB0 010F
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-48: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TRISC 0E20 TRISC15 — TRISC13 TRISC12 TRISC11 TRISC10 TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 BFFF
PORTC 0E22 RC15 — RC13 RC12 RC11 RC10 RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx
LATC 0E24 LATC15 — LATC13 LATC12 LATC11 LATC10 LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx
DS70000657H-page 99
ODCC 0E26 ODCC15 — ODCC13 ODCC12 ODCC11 ODCC10 ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0000
CNENC 0E28 CNIEC15 — CNIEC13 CNIEC12 CNIEC11 CNIEC10 CNIEC9 CNIEC8 CNIEC7 CNIEC6 CNIEC5 CNIEC4 CNIEC3 CNIEC2 CNIEC1 CNIEC0 0000
CNPUC 0E2A CNPUC15 — CNPUC13 CNPUC12 CNPUC11 CNPUC10 CNPUC9 CNPUC8 CNPUC7 CNPUC6 CNPUC5 CNPUC4 CNPUC3 CNPUC2 CNPUC1 CNPUC0 0000
CNPDC 0E2C CNPDC15 — CNPDC13 CNPDC12 CNPDC11 CNPDC10 CNPDC9 CNPDC8 CNPDC7 CNPDC6 CNPDC5 CNPDC4 CNPDC3 CNPDC2 CNPDC1 CNPDC0 0000
ANSELC 0E2E — — — — ANSC11 — — — — — — — — ANSC2 ANSC1 ANSC0 0807
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000657H-page 100
TABLE 4-50: PORTE REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TABLE 4-51: PORTF REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File All
2011-2013 Microchip Technology Inc.
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TABLE 4-52: PORTG REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
TRISA 0E00 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F
PORTA 0E02 — — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0 0000
LATA 0E04 — — — — — LATA10 LATA9 LATA8 LATA7 — — LATA4 LATA3 LATA2 LA1TA1 LA0TA0 0000
ODCA 0E06 — — — — — ODCA10 ODCA9 ODCA8 ODCA7 — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000
CNENA 0E08 — — — — — CNIEA10 CNIEA9 CNIEA8 CNIEA7 — — CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000
CNPUA 0E0A — — — — — CNPUA10 CNPUA9 CNPUA8 CNPUA7 — — CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000
CNPDA 0E0C — — — — — CNPDA10 CNPDA9 CNPDA8 CNPDA7 — — CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000
ANSELA 0E0E — — — — — — — — — — — ANSA4 — — ANSA1 ANSA0 0013
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-54: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000
CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
ANSELB 0E1E — — — — — — — ANSB8 — — — — ANSB3 ANSB2 ANSB1 ANSB0 010F
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-55: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY
2011-2013 Microchip Technology Inc.
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TRISC 0E20 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF
PORTC 0E22 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx
LATC 0E24 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx
ODCC 0E26 — — — — — — ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0000
CNENC 0E28 — — — — — — CNIEC9 CNIEC8 CNIEC7 CNIEC6 CNIEC5 CNIEC4 CNIEC3 CNIEC2 CNIEC1 CNIEC0 0000
CNPUC 0E2A — — — — — — CNPUC9 CNPUC8 CNPUC7 CNPUC6 CNPUC5 CNPUC4 CNPUC3 CNPUC2 CNPUC1 CNPUC0 0000
CNPDC 0E2C — — — — — — CNPDC9 CNPDC8 CNPDC7 CNPDC6 CNPDC5 CNPDC4 CNPDC3 CNPDC2 CNPDC1 CNPDC0 0000
ANSELC 0E2E — — — — — — — — — — — — — ANSC2 ANSC1 ANSC0 0007
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-56: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY
2011-2013 Microchip Technology Inc.
File All
TABLE 4-57: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000
CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
ANSELB 0E1E — — — — — — — ANSB8 — — — — ANSB3 ANSB2 ANSB1 ANSB0 010F
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-58: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
xxxx
ODCC 0E26 — — — — — — — ODCC8 — — — — — — ODCC1 ODCC0 0000
CNENC 0E28 — — — — — — — CNIEC8 — — — — — — CNIEC1 CNIEC0 0000
CNPUC 0E2A — — — — — — — CNPUC8 — — — — — — CNPUC1 CNPUC0 0000
CNPDC 0E2C — — — — — — — CNPDC8 — — — — — — CNPDC1 CNPDC0 0000
ANSELC 0E2E — — — — — — — — — — — — — — ANSC1 ANSC0 0003
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000657H-page 104
TABLE 4-60: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC202 AND dsPIC33EPXXXGP/MC202/502 DEVICES ONLY
File All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000
CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
ANSELB 0E1E — — — — — — — ANSB8 — — — — ANSB3 ANSB2 ANSB1 ANSB0 010F
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
4.4.1 PAGED MEMORY SCHEME address or Program Space Visibility (PSV) address.
The Data Space Page registers are located in the
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
SFR space.
50X and PIC24EPXXXGP/MC20X architecture
extends the available Data Space through a paging Construction of the EDS address is shown in
scheme, which allows the available Data Space to Example 4-1. When DSRPAG<9> = 0 and the base
be accessed using MOV instructions in a linear address bit, EA<15> = 1, the DSRPAG<8:0> bits are
fashion for pre-modified and post-modified Effective concatenated onto EA<14:0> to form the 24-bit EDS
Addresses (EA). The upper half of the base Data read address. Similarly, when base address bit,
Space address is used in conjunction with the Data EA<15> = 1, DSWPAG<8:0> are concatenated onto
Space Page registers, the 10-bit Read Page register EA<14:0> to form the 24-bit EDS write address.
(DSRPAG) or the 9-bit Write Page register
(DSWPAG), to form an Extended Data Space (EDS)
Byte
16-Bit DS EA Select
EA<15>
Generate Y
PSV Address DSRPAG<9> 1 EA
= 1?
N
Select
DSRPAG
0 DSRPAG<8:0>
9 Bits 15 Bits
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
Byte
16-Bit DS EA Select
EA<15> = 0
(DSWPAG = don’t care)
1 EA
DSWPAG<8:0>
9 Bits 15 Bits
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
The paged memory scheme provides access to The Program Space (PS) can be accessed with a
multiple 32-Kbyte windows in the EDS and PSV DSRPAG of 0x200 or greater. Only reads from PS are
memory. The Data Space Page registers, DSxPAG, in supported using the DSRPAG. Writes to PS are not
combination with the upper half of the Data Space supported, so DSWPAG is dedicated to DS, including
address, can provide up to 16 Mbytes of additional EDS only. The Data Space and EDS can be read from,
address space in the EDS and 8 Mbytes (DSRPAG and written to, using DSRPAG and DSWPAG,
only) of PSV address space. The paged data memory respectively.
space is shown in Example 4-3.
DS_Addr<15:0> 0x0000
0x0000 EDS Page 0x1FF
SFR Registers (DSRPAG = 0x1FF)
0x0FFF (DSWPAG = 0x1FF)
0x7FFF 0x0000
0x1000 (TBLPAG = 0x7F)
0x0000
EDS Page 0x200 lsw Using
Up to 8-Kbyte (DSRPAG = 0x200) 0x7F_FFFF TBLRDL/TBLWTL
RAM(1) No writes allowed MSB Using
0x7FFF TBLRDH/TBLWTH
0x2FFF PSV 0xFFFF
0x3000 Program
0x7FFF Program Memory
Memory
0x8000 (MSB – <23:16>)
(lsw)
32-Kbyte 0x0000 0x00_0000
EDS Page 0x2FF
EDS Window
(DSRPAG = 0x2FF)
0xFFFF
No writes allowed
0x7FFF
0x0000
EDS Page 0x300
(DSRPAG = 0x300)
No writes allowed
0x7FFF
PSV
DS70000657H-page 107
Program
Memory
0x7F_FFFF
(MSB)
0x0000
EDS Page 0x3FF
(DSRPAG = 0x3FF)
No writes allowed
0x7FFF
Note 1: For 64K Flash devices. RAM size and end location is dependent on device; see Section 4.2 “Data Address Space” for more information.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Allocating different Page registers for read and write In general, when an overflow is detected, the DSxPAG
access allows the architecture to support data register is incremented and the EA<15> bit is set to
movement between different pages in data memory. keep the base address within the EDS or PSV window.
This is accomplished by setting the DSRPAG register When an underflow is detected, the DSxPAG register is
value to the page from which you want to read, and decremented and the EA<15> bit is set to keep the
configuring the DSWPAG register to the page to which base address within the EDS or PSV window. This
it needs to be written. Data can also be moved from creates a linear EDS and PSV address space, but only
different PSV to EDS pages, by configuring the when using Register Indirect Addressing modes.
DSRPAG and DSWPAG registers to address PSV and Exceptions to the operation described above arise
EDS space, respectively. The data can be moved when entering and exiting the boundaries of Page 0,
between pages by a single instruction. EDS and PSV spaces. Table 4-61 lists the effects of
When an EDS or PSV page overflow or underflow overflow and underflow scenarios at different
occurs, EA<15> is cleared as a result of the register boundaries.
indirect EA calculation. An overflow or underflow of the In the following cases, when overflow or underflow
EA in the EDS or PSV pages can occur at the page occurs, the EA<15> bit is set and the DSxPAG is not
boundaries when: modified; therefore, the EA will wrap to the beginning of
• The initial address prior to modification addresses the current page:
an EDS or PSV page • Register Indirect with Register Offset Addressing
• The EA calculation uses Pre-Modified or • Modulo Addressing
Post-Modified Register Indirect Addressing;
• Bit-Reversed Addressing
however, this does not include Register Offset
Addressing
4.4.2 EXTENDED X DATA SPACE The remaining pages, including both EDS and PSV
pages, are only accessible using the DSRPAG or
The lower portion of the base address space range,
DSWPAG registers in combination with the upper
between 0x0000 and 0x7FFF, is always accessible
32 Kbytes, 0x8000 to 0xFFFF, of the base address,
regardless of the contents of the Data Space Page
where base address bit, EA<15> = 1.
registers. It is indirectly addressable through the
register indirect instructions. It can be regarded as For example, when DSRPAG = 0x001 or
being located in the default EDS Page 0 (i.e., EDS DSWPAG = 0x001, accesses to the upper 32 Kbytes,
address range of 0x000000 to 0x007FFF with the base 0x8000 to 0xFFFF, of the Data Space will map to the
address bit, EA<15> = 0, for this address range). EDS address range of 0x008000 to 0x00FFFF. When
However, Page 0 cannot be accessed through the DSRPAG = 0x002 or DSWPAG = 0x002, accesses to
upper 32 Kbytes, 0x8000 to 0xFFFF, of base Data the upper 32 Kbytes of the Data Space will map to the
Space, in combination with DSRPAG = 0x000 or EDS address range of 0x010000 to 0x017FFF and so
DSWPAG = 0x000. Consequently, DSRPAG and on, as shown in the EDS memory map in Figure 4-17.
DSWPAG are initialized to 0x001 at Reset. For more information on the PSV page access using
Note 1: DSxPAG should not be used to access Data Space Page registers, refer to the “Program
Page 0. An EDS access with DSxPAG Space Visibility from Data Space” section in
set to 0x000 will generate an address “Program Memory” (DS70613) of the “dsPIC33/
error trap. PIC24 Family Reference Manual”.
2: Clearing the DSxPAG in software has no
effect.
EA<15:0>
0x0000
SFR/DS (PAGE 0)
Conventional
DS Address 0x8000 0x008000
DS PAGE 1
0xFFFF
0x010000
PAGE 2
0x018000
PAGE 3
DSRPAG<9> = 0
EDS EA Address (24 bits)
(DSRPAG<8:0>, EA<14:0>)
(DSWPAG<8:0>, EA<14:0>)
0xFE8000
PAGE 1FD
0xFF0000
PAGE 1FE
0xFF8000
PAGE 1FF
4.4.3 DATA MEMORY ARBITRATION AND that of the CPU maintain the same priority relationship
BUS MASTER PRIORITY relative to each other. The priority schemes for bus
masters with different MSTRPR values are tabulated in
EDS accesses from bus masters in the system are
Table 4-62.
arbitrated.
This bus master priority control allows the user
The arbiter for data memory (including EDS) arbitrates
application to manipulate the real-time response of the
between the CPU, the DMA and the ICD module. In the
system, either statically during initialization or
event of coincidental access to a bus by the bus
dynamically in response to real-time events.
masters, the arbiter determines which bus master
access has the highest priority. The other bus masters
are suspended and processed after the access of the TABLE 4-62: DATA MEMORY BUS
bus by the bus master with the highest priority. ARBITER PRIORITY
By default, the CPU is Bus Master 0 (M0) with the MSTRPR<15:0> Bit Setting(1)
highest priority and the ICD is Bus Master 4 (M4) with Priority
0x0000 0x0020
the lowest priority. The remaining bus master (DMA
Controller) is allocated to M3 (M1 and M2 are reserved M0 (highest) CPU DMA
and cannot be used). The user application may raise or M1 Reserved CPU
lower the priority of the DMA Controller to be above that
M2 Reserved Reserved
of the CPU by setting the appropriate bits in the EDS
Bus Master Priority Control (MSTRPR) register. All bus M3 DMA Reserved
masters with raised priorities will maintain the same M4 (lowest) ICD ICD
priority relationship relative to each other (i.e., M1 Note 1: All other values of MSTRPR<15:0> are
being highest and M3 being lowest, with M2 in reserved.
between). Also, all the bus masters with priorities below
MSTRPR<15:0>
M0 M1 M2 M3 M4
SRAM
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0
Pivot Point
XBREV<14:0> = 0x0008 for a 16-Word Bit-Reversed Buffer
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 0 0 8
0 0 1 0 2 0 1 0 0 4
0 0 1 1 3 1 1 0 0 12
0 1 0 0 4 0 0 1 0 2
0 1 0 1 5 1 0 1 0 10
0 1 1 0 6 0 1 1 0 6
0 1 1 1 7 1 1 1 0 14
1 0 0 0 8 0 0 0 1 1
1 0 0 1 9 1 0 0 1 9
1 0 1 0 10 0 1 0 1 5
1 0 1 1 11 1 1 0 1 13
1 1 0 0 12 0 0 1 1 3
1 1 0 1 13 1 0 1 1 11
1 1 1 0 14 0 1 1 1 7
1 1 1 1 15 1 1 1 1 15
4.8 Interfacing Program and Data Table instructions allow an application to read or write
Memory Spaces to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ need to be updated periodically. It also allows access
50X and PIC24EPXXXGP/MC20X architecture uses a to all bytes of the program word. The remapping
24-bit-wide Program Space (PS) and a 16-bit-wide method allows an application to access a large block of
Data Space (DS). The architecture is also a modified data on a read-only basis, which is ideal for look-ups
Harvard scheme, meaning that data can also be from a large table of static data. The application can
present in the Program Space. To use this data suc- only access the least significant word of the program
cessfully, it must be accessed in a way that preserves word.
the alignment of information in both spaces.
Aside from normal execution, the architecture of the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices provides two
methods by which Program Space can be accessed
during operation:
• Using table instructions to access individual bytes
or words anywhere in the Program Space
• Remapping a portion of the Program Space into
the Data Space (Program Space Visibility)
23 Bits
EA 1/0
8 Bits 16 Bits
24 Bits
Note 1: The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain
word alignment of data in the Program and Data Spaces.
2: Table operations are not required to be word-aligned. Table Read operations are permitted in the
configuration memory space.
4.8.1 DATA ACCESS FROM PROGRAM - In Byte mode, either the upper or lower byte
MEMORY USING TABLE of the lower program word is mapped to the
INSTRUCTIONS lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
The TBLRDL and TBLWTL instructions offer a direct byte is selected when it is ‘0’.
method of reading or writing the lower word of any
• TBLRDH (Table Read High):
address within the Program Space without going
through Data Space. The TBLRDH and TBLWTH - In Word mode, this instruction maps the entire
instructions are the only method to read or write the upper word of a program address (P<23:16>)
upper 8 bits of a Program Space word as data. to a data address. The ‘phantom’ byte
(D<15:8>) is always ‘0’.
The PC is incremented by two for each successive 24-bit
- In Byte mode, this instruction maps the upper
program word. This allows program memory addresses
or lower byte of the program word to D<7:0>
to directly map to Data Space addresses. Program mem-
of the data address in the TBLRDL instruc-
ory can thus be regarded as two 16-bit-wide word
tion. The data is always ‘0’ when the upper
address spaces, residing side by side, each with the
‘phantom’ byte is selected (Byte Select = 1).
same address range. TBLRDL and TBLWTL access the
space that contains the least significant data word. In a similar fashion, two table instructions, TBLWTH
TBLRDH and TBLWTH access the space that contains the and TBLWTL, are used to write individual bytes or
upper data byte. words to a Program Space address. The details of
their operation are explained in Section 5.0 “Flash
Two table instructions are provided to move byte or
Program Memory”.
word-sized (16-bit) data to and from Program Space.
Both function as either byte or word operations. For all table operations, the area of program memory
space to be accessed is determined by the Table Page
• TBLRDL (Table Read Low):
register (TBLPAG). TBLPAG covers the entire program
- In Word mode, this instruction maps the memory space of the device, including user application
lower word of the Program Space and configuration spaces. When TBLPAG<7> = 0, the
location (P<15:0>) to a data address table page is located in the user memory space. When
(D<15:0>) TBLPAG<7> = 1, the page is located in configuration
space.
Program Space
TBLPAG
02
23 15 0
0x000000 23 16 8 0
00000000
00000000
0x020000 00000000
0x030000 00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
5.0 FLASH PROGRAM MEMORY alternate programming pin pairs: PGECx/PGEDx), and
three other lines for power (VDD), ground (VSS) and
Note 1: This data sheet summarizes the Master Clear (MCLR). This allows customers to
features of the dsPIC33EPXXXGP50X, manufacture boards with unprogrammed devices and
dsPIC33EPXXXMC20X/50X and then program the device just before shipping the
PIC24EPXXXGP/MC20X families of product. This also allows the most recent firmware or a
devices. It is not intended to be a compre- custom firmware to be programmed.
hensive reference source. To complement RTSP is accomplished using TBLRD (Table Read) and
the information in this data sheet, refer to TBLWT (Table Write) instructions. With RTSP, the user
“Flash Programming” (DS70609) in application can write program memory data a single
the “dsPIC33/PIC24 Family Reference program memory word, and erase program memory in
Manual”, which is available from the blocks or ‘pages’ of 1024 instructions (3072 bytes) at a
Microchip web site (www.microchip.com). time.
2: Some registers and associated bits
described in this section may not be 5.1 Table Instructions and Flash
available on all devices. Refer to Programming
Section 4.0 “Memory Organization” in
this data sheet for device-specific register Regardless of the method used, all programming of
and bit information. Flash memory is done with the Table Read and Table
Write instructions. These allow direct read and write
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ access to the program memory space from the data
50X and PIC24EPXXXGP/MC20X devices contain memory while the device is in normal operating mode.
internal Flash program memory for storing and The 24-bit target address in the program memory is
executing application code. The memory is readable, formed using bits<7:0> of the TBLPAG register and the
writable and erasable during normal operation over the Effective Address (EA) from a W register, specified in
entire VDD range. the table instruction, as shown in Figure 5-1.
Flash memory can be programmed in two ways: The TBLRDL and the TBLWTL instructions are used to
• In-Circuit Serial Programming™ (ICSP™) read or write to bits<15:0> of program memory.
programming capability TBLRDL and TBLWTL can access program memory in
• Run-Time Self-Programming (RTSP) both Word and Byte modes.
ICSP allows for a dsPIC33EPXXXGP50X, The TBLRDH and TBLWTH instructions are used to read
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ or write to bits<23:16> of program memory. TBLRDH
MC20X device to be serially programmed while in the and TBLWTH can also access program memory in Word
end application circuit. This is done with two lines for or Byte mode.
programming clock and programming data (one of the
24 Bits
Using
0 Program Counter 0
Program Counter
Working Reg EA
Using
1/0 TBLPAG Reg
Table Instruction
8 Bits 16 Bits
User/Configuration Byte
Space Select 24-Bit EA Select
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator SYSRST
VDD
Trap Conflict
Illegal Opcode
Uninitialized W Register
Security Reset
Configuration Mismatch
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
2: Some registers and associated bits Interrupt vectors are prioritized in terms of their natural
described in this section may not be priority. This priority is linked to their position in the
available on all devices. Refer to vector table. Lower addresses generally have a higher
Section 4.0 “Memory Organization” in natural priority. For example, the interrupt associated
this data sheet for device-specific register with Vector 0 takes priority over interrupts at any other
and bit information. vector address.
: :
: :
: :
Interrupt Vector 52 0x00007C
Interrupt Vector 53 0x00007E
Interrupt Vector 54 0x000080 See Table 7-1 for
: : Interrupt Vector Details
: :
: :
Interrupt Vector 116 0x0000FC
Interrupt Vector 117 0x0000FE
Interrupt Vector 118 0x000100
Interrupt Vector 119 0x000102
Interrupt Vector 120 0x000104
: :
: :
: :
Interrupt Vector 244 0x0001FC
Interrupt Vector 245 0x0001FE
START OF CODE 0x000200
INTCON1 contains the Interrupt Nesting Disable bit • The CPU STATUS Register, SR, contains the
(NSTDIS), as well as the control and status flags for the IPL<2:0> bits (SR<7:5>). These bits indicate the
processor trap sources. current CPU Interrupt Priority Level. The user
software can change the current CPU Interrupt
The INTCON2 register controls external interrupt Priority Level by writing to the IPLx bits.
request signal behavior and also contains the Global
• The CORCON register contains the IPL3 bit
Interrupt Enable bit (GIE).
which, together with IPL<2:0>, also indicates the
INTCON3 contains the status flags for the DMA and DO current CPU priority level. IPL3 is a read-only bit
stack overflow status trap sources. so that trap events cannot be masked by the user
The INTCON4 register contains the software software.
generated hard trap status bit (SGHT). All Interrupt registers are described in Register 7-3
through Register 7-7 in the following pages.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
Note 1: These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
8.0 DIRECT MEMORY ACCESS The DMA Controller transfers data between Peripheral
Data registers and Data Space SRAM
(DMA)
In addition, DMA can access the entire data memory
Note 1: This data sheet summarizes the space. The Data Memory Bus Arbiter is utilized when
features of the dsPIC33EPXXXGP50X, either the CPU or DMA attempts to access SRAM,
dsPIC33EPXXXMC20X/50X and resulting in potential DMA or CPU stalls.
PIC24EPXXXGP/MC20X families of
The DMA Controller supports 4 independent channels.
devices. It is not intended to be a
Each channel can be configured for transfers to or from
comprehensive reference source. To
selected peripherals. Some of the peripherals
complement the information in this data
supported by the DMA Controller include:
sheet, refer to “Direct Memory Access
(DMA)” (DS70348) in the “dsPIC33/ • ECAN™
PIC24 Family Reference Manual”, which • Analog-to-Digital Converter (ADC)
is available from the Microchip web site • Serial Peripheral Interface (SPI)
(www.microchip.com). • UART
2: Some registers and associated bits • Input Capture
described in this section may not be • Output Compare
available on all devices. Refer to
Section 4.0 “Memory Organization” in Refer to Table 8-1 for a complete list of supported
this data sheet for device-specific register peripherals.
and bit information.
Data Memory
PERIPHERAL DMA Arbiter
(see Figure 4-18)
SRAM
In addition, DMA transfers can be triggered by timers • Peripheral Indirect Addressing mode (peripheral
as well as external interrupts. Each DMA channel is generates destination address)
unidirectional. Two DMA channels must be allocated to • CPU interrupt after half or full block
read and write to a peripheral. If more than one channel transfer complete
receives a request to transfer data, a simple fixed • Byte or word transfers
priority scheme based on channel number, dictates
• Fixed priority channel arbitration
which channel completes the transfer and which
channel, or channels, are left pending. Each DMA • Manual (software) or automatic (peripheral DMA
channel moves a block of data, after which, it generates requests) transfer initiation
an interrupt to the CPU to indicate that the block is • One-Shot or Auto-Repeat Block Transfer modes
available for processing. • Ping-Pong mode (automatic switch between two
The DMA Controller provides these functional SRAM start addresses after each block transfer is
capabilities: complete)
• DMA request for each channel can be selected
• Four DMA channels
from any supported interrupt source
• Register Indirect with Post-Increment
• Debug support features
Addressing mode
• Register Indirect without Post-Increment The peripherals that can utilize DMA are listed in
Addressing mode Table 8-1.
DMA Controller
DMA IRQ to DMA
DMA Ready and Interrupt
Control
DMA
Arbiter Channels Peripheral 1 Controller
Modules
0 1 2 3 CPU DMA
DMA X-Bus
Note: CPU and DMA address buses are not shown for clarity.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the
forced DMA transfer is complete or the channel is disabled (CHEN = 0).
2: This selection is available in dsPIC33EPXXXGP/MC50X devices only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
2: The number of DMA transfers = CNT<13:0> + 1.
REGISTER 8-9: DSADRH: DMA MOST RECENT RAM HIGH ADDRESS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REGISTER 8-10: DSADRL: DMA MOST RECENT RAM LOW ADDRESS REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DSADR<15:8>
bit 15 bit 8
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 DSADR<15:0>: Most Recent DMA Address Accessed by DMA bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
NOTES:
DOZE<2:0>
Primary Oscillator
OSC1 XT, HS, EC
POSCCLK
S2
FCY(2)
DOZE
S3 XTPLL, HSPLL, ECPLL,
FRCPLL, FPLLO
S1 PLL(1) S1/S3
OSC2
POSCMD<1:0>
FP(2)
÷2
FRCDIV
FRCDIV<2:0>
TUN<5:0> FRCDIV16 Reference Clock Generation
÷ 16 S6
POSCCLK
FRC REFCLKO
S0 ÷N
FOSC
RPn
LPRC LPRC
S5
Oscillator
ROSEL RODIV<3:0>
COSC<2:0>
WDT, PWRT,
0b000 NOSC<2:0> FNOSC<2:0>
FSCM
0.8 MHz < FPLLI(1) < 8.0 MHz FPLLO(1) 120 MHz @ +125ºC
120 MHZ < FVCO(1) < 340 MHZ FPLLO(1) 140 MHz @ +85ºC
PLLPRE<4:0>
PLLPOST<1:0>
÷M
PLLDIV<8:0>
PLLDIV + 2
F PLLO = F IN --------------------- = F IN ----------------------------------------------------------------------------------------
M
N1 N2 PLLPRE + 2 2 PLLPOST + 1
Where:
N1 = PLLPRE + 2
N2 = 2 x (PLLPOST + 1)
M = PLLDIV + 2
PLLDIV + 2
Fvco = F IN ------- = F IN -------------------------------------
M
N1 PLLPRE + 2
Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator” (DS70580) in the “dsPIC33/
PIC24 Family Reference Manual” (available from the Microchip web site) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and trigger an oscillator failure trap.
Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator” (DS70580) in the “dsPIC33/
PIC24 Family Reference Manual” (available from the Microchip web site) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and trigger an oscillator failure trap.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
2: This pin is remappable. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This single bit enables and disables all four DMA channels.
NOTES:
11.0 I/O PORTS has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through,” in
Note 1: This data sheet summarizes the which a port’s digital output can drive the input of a
features of the dsPIC33EPXXXGP50X, peripheral that shares the same pin. Figure 11-1
dsPIC33EPXXXMC20X/50X and illustrates how ports are shared with other peripherals
PIC24EPXXXGP/MC20X families of and the associated I/O pin to which they are connected.
devices. It is not intended to be a compre-
hensive reference source. To complement When a peripheral is enabled and the peripheral is
the information in this data sheet, refer to actively driving an associated pin, the use of the pin as a
“I/O Ports” (DS70598) in the “dsPIC33/ general purpose output pin is disabled. The I/O pin can
PIC24 Family Reference Manual”, which be read, but the output driver for the parallel port bit is
is available from the Microchip web site disabled. If a peripheral is enabled, but the peripheral is
(www.microchip.com). not actively driving a pin, that pin can be driven by a port.
2: Some registers and associated bits All port pins have eight registers directly associated with
described in this section may not be their operation as digital I/O. The Data Direction register
available on all devices. Refer to (TRISx) determines whether the pin is an input or an out-
Section 4.0 “Memory Organization” in put. If the data direction bit is a ‘1’, then the pin is an input.
this data sheet for device-specific register All port pins are defined as inputs after a Reset. Reads
and bit information. from the Latch register (LATx) read the latch. Writes to the
Latch write the latch. Reads from the port (PORTx) read
Many of the device pins are shared among the peripher- the port pins, while writes to the port pins write the latch.
als and the parallel I/O ports. All I/O input ports feature
Schmitt Trigger inputs for improved noise immunity. Any bit and its associated data and control registers
that are not valid for a particular device is disabled.
This means the corresponding LATx and TRISx
11.1 Parallel I/O (PIO) Ports
registers and the port pin are read as zeros.
Generally, a parallel I/O port that shares a pin with a When a pin is shared with another peripheral or
peripheral is subservient to the peripheral. The function that is defined as an input only, it is
peripheral’s output buffer data and control signals are nevertheless regarded as a dedicated port because
provided to a pair of multiplexers. The multiplexers there is no other competing source of outputs.
select whether the peripheral or the associated port
Data Bus
D Q I/O Pin
WR TRIS
CK
TRIS Latch
D Q
WR LAT +
WR Port CK
Data Latch
Read LAT
Input Data
Read Port
11.4 Peripheral Pin Select (PPS) In comparison, some digital-only peripheral modules
are never included in the Peripheral Pin Select feature.
A major challenge in general purpose devices is provid- This is because the peripheral’s function requires
ing the largest possible set of peripheral features while special I/O circuitry on a specific port and cannot be
minimizing the conflict of features on I/O pins. The easily connected to multiple pins. These modules
challenge is even greater on low pin count devices. In include I2C™ and the PWM. A similar requirement
an application where more than one peripheral needs excludes all modules with analog inputs, such as the
to be assigned to a single pin, inconvenient work- ADC Converter.
arounds in application code, or a complete redesign,
may be the only option. A key difference between remappable and non-
remappable peripherals is that remappable peripherals
Peripheral Pin Select configuration provides an are not associated with a default I/O pin. The peripheral
alternative to these choices by enabling peripheral set must always be assigned to a specific I/O pin before it
selection and their placement on a wide range of I/O can be used. In contrast, non-remappable peripherals
pins. By increasing the pinout options available on a are always available on a default pin, assuming that the
particular device, users can better tailor the device to peripheral is active and not conflicting with another
their entire application, rather than trimming the peripheral.
application to fit the device.
When a remappable peripheral is active on a given I/O
The Peripheral Pin Select configuration feature oper- pin, it takes priority over all other digital I/O and digital
ates over a fixed subset of digital I/O pins. Users may communication peripherals associated with the pin.
independently map the input and/or output of most dig- Priority is given regardless of the type of peripheral that
ital peripherals to any one of these I/O pins. Hardware is mapped. Remappable peripherals never take priority
safeguards are included that prevent accidental or over any analog functions associated with the pin.
spurious changes to the peripheral mapping once it has
been established. 11.4.3 CONTROLLING PERIPHERAL PIN
SELECT
11.4.1 AVAILABLE PINS
Peripheral Pin Select features are controlled through
The number of available pins is dependent on the two sets of SFRs: one to map peripheral inputs and one
particular device and its pin count. Pins that support the to map outputs. Because they are separately con-
Peripheral Pin Select feature include the label, “RPn” or trolled, a particular peripheral’s input and output (if the
“RPIn”, in their full pin designation, where “n” is the peripheral has both) can be placed on any selectable
remappable pin number. “RP” is used to designate pins function pin without constraint.
that support both remappable input and output
functions, while “RPI” indicates pins that support The association of a peripheral to a peripheral-
remappable input functions only. selectable pin is handled in two different ways,
depending on whether an input or output is being
11.4.2 AVAILABLE PERIPHERALS mapped.
The peripherals managed by the Peripheral Pin Select
are all digital-only peripherals. These include general
serial communications (UART and SPI), general pur-
pose timer clock inputs, timer-related peripherals (input
capture and output compare) and interrupt-on-change
inputs.
n
RPn
EXAMPLE 11-2: CONNECTING IC1 TO THE HOME1 QEI1 DIGITAL FILTER INPUT ON PIN 43 OF
THE dsPIC33EPXXXMC206 DEVICE
RPINR15 = 0x2500; /* Connect the QEI1 HOME1 input to RP37 (pin 43) */
RPINR7 = 0x009; /* Connect the IC1 input to the digital filter on the FHOME1 input */
TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES (CONTINUED)
Peripheral Pin Peripheral Pin
Input/ Input/
Select Input Pin Assignment Select Input Pin Assignment
Output Output
Register Value Register Value
010 1000 I/O RP40 101 0101 — —
010 1001 I/O RP41 101 0110 — —
010 1010 I/O RP42 101 0111 — —
010 1011 I/O RP43 101 1000 — —
010 1100 I RPI44 101 1001 — —
101 1010 — — 110 1101 — —
101 1011 — — 110 1110 — —
101 1100 — — 110 1111 — —
101 1101 — — 111 0000 — —
101 1110 I RPI94 111 0001 — —
101 1111 I RPI95 111 0010 — —
110 0000 I RPI96 111 0011 — —
110 0001 I/O RP97 111 0100 — —
110 0010 — — 111 0101 — —
110 0011 — — 111 0110 I/O RP118
110 0100 — — 111 0111 I RPI119
110 0101 — — 111 1000 I/O RP120
110 0110 — — 111 1001 I RPI121
110 0111 — — 111 1010 — —
110 1000 — — 111 1011 — —
110 1001 — — 111 1100 — —
110 1010 — — 111 1101 — —
110 1011 — — 111 1110 — —
110 1100 — — 111 1111 — —
Legend: Shaded rows indicate PPS Input register values that are unimplemented.
Note 1: See Section 11.4.4.1 “Virtual Connections” for more information on selecting this pin assignment.
2: These inputs are available on dsPIC33EPXXXGP/MC50X devices only.
11.5 I/O Helpful Tips 5. When driving LEDs directly, the I/O pin can source
or sink more current than what is specified in the
1. In some cases, certain pins, as defined in
VOH/IOH and VOL/IOL DC characteristic specifica-
Table 30-11, under “Injection Current”, have inter-
tion. The respective IOH and IOL current rating only
nal protection diodes to VDD and VSS. The term,
applies to maintaining the corresponding output at
“Injection Current”, is also referred to as “Clamp
or above the VOH, and at or below the VOL levels.
Current”. On designated pins, with sufficient exter-
However, for LEDs, unlike digital inputs of an
nal current-limiting precautions by the user, I/O pin
externally connected device, they are not gov-
input voltages are allowed to be greater or less
erned by the same minimum VIH/VIL levels. An I/O
than the data sheet absolute maximum ratings,
pin output can safely sink or source any current
with respect to the VSS and VDD supplies. Note
less than that listed in the absolute maximum
that when the user application forward biases
rating section of this data sheet. For example:
either of the high or low side internal input clamp
diodes, that the resulting current being injected VOH = 2.4V @ IOH = -8 mA and VDD = 3.3V
into the device, that is clamped internally by the The maximum output current sourced by any 8 mA
VDD and VSS power rails, may affect the ADC I/O pin = 12 mA.
accuracy by four to six counts. LED source current < 12 mA is technically
2. I/O pins that are shared with any analog input pin permitted. Refer to the VOH/IOH graphs in
(i.e., ANx) are always analog pins by default after Section 30.0 “Electrical Characteristics” for
any Reset. Consequently, configuring a pin as an additional information.
analog input pin automatically disables the digital 6. The Peripheral Pin Select (PPS) pin mapping rules
input pin buffer and any attempt to read the digital are as follows:
input level by reading PORTx or LATx will always a) Only one “output” function can be active on a
return a ‘0’, regardless of the digital logic level on given pin at any time, regardless if it is a ded-
the pin. To use a pin as a digital I/O pin on a shared icated or remappable function (one pin, one
ANx pin, the user application needs to configure the output).
Analog Pin Configuration registers in the I/O ports b) It is possible to assign a “remappable output”
module (i.e., ANSELx) by setting the appropriate bit function to multiple pins and externally short or
that corresponds to that I/O port pin to a ‘0’. tie them together for increased current drive.
Note: Although it is not possible to use a digital c) If any “dedicated output” function is enabled
input pin when its analog function is on a pin, it will take precedence over any
enabled, it is possible to use the digital I/O remappable “output” function.
output function, TRISx = 0x0, while the
d) If any “dedicated digital” (input or output) func-
analog function is also enabled. However,
tion is enabled on a pin, any number of “input”
this is not recommended, particularly if the
remappable functions can be mapped to the
analog input is connected to an external
same pin.
analog voltage source, which would
create signal contention between the e) If any “dedicated analog” function(s) are
analog signal and the output pin driver. enabled on a given pin, “digital input(s)” of any
kind will all be disabled, although a single “dig-
3. Most I/O pins have multiple functions. Referring to ital output”, at the user’s cautionary discretion,
the device pin diagrams in this data sheet, the prior- can be enabled and active as long as there is
ities of the functions allocated to any pins are no signal contention with an external analog
indicated by reading the pin name from left-to-right. input signal. For example, it is possible for the
The left most function name takes precedence over ADC to convert the digital output logic level, or
any function to its right in the naming convention. to toggle a digital output on a comparator or
For example: AN16/T2CK/T7CK/RC1. This indi- ADC input provided there is no external
cates that AN16 is the highest priority in this analog input, such as for a built-in self-test.
example and will supersede all other functions to its f) Any number of “input” remappable functions
right in the list. Those other functions to its right, can be mapped to the same pin(s) at the same
even if enabled, would not work as long as any time, including to any pin with a single output
other function to its left was enabled. This rule from either a dedicated or remappable “output”.
applies to all of the functions listed for a given pin.
4. Each pin has an internal weak pull-up resistor and
pull-down resistor that can be configured using the
CNPUx and CNPDx registers, respectively. These
resistors eliminate the need for external resistors
in certain applications. The internal pull-up is up to
~(VDD – 0.8), not VDD. This value is still above the
minimum VIH of CMOS and TTL devices.
g) The TRISx registers control only the digital I/O 11.6 I/O Ports Resources
output buffer. Any other dedicated or remappa-
ble active “output” will automatically override Many useful resources are provided on the main prod-
the TRIS setting. The TRISx register does not uct page of the Microchip web site for the devices listed
control the digital logic “input” buffer. Remap- in this data sheet. This product page, which can be
pable digital “inputs” do not automatically accessed using this link, contains the latest updates
override TRIS settings, which means that the and additional information.
TRISx bit must be set to input for pins with only Note: In the event you are not able to access the
remappable input function(s) assigned product page using the link above, enter
h) All analog pins are enabled by default after any this URL in your browser:
Reset and the corresponding digital input http://www.microchip.com/wwwproducts/
buffer on the pin has been disabled. Only the Devices.aspx?dDocName=en555464
Analog Pin Select registers control the digital
input buffer, not the TRISx register. The user 11.6.1 KEY RESOURCES
must disable the analog function on a pin using
• “I/O Ports” (DS70598) in the “dsPIC33/PIC24
the Analog Pin Select registers in order to use
Family Reference Manual”
any “digital input(s)” on a corresponding pin, no
exceptions. • Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
NOTES:
12.0 TIMER1 The Timer1 module can operate in one of the following
modes:
Note 1: This data sheet summarizes the • Timer mode
features of the dsPIC33EPXXXGP50X,
• Gated Timer mode
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of • Synchronous Counter mode
devices. It is not intended to be a • Asynchronous Counter mode
comprehensive reference source. To com- In Timer and Gated Timer modes, the input clock is
plement the information in this data sheet, derived from the internal instruction cycle clock (FCY).
refer to “Timers” (DS70362) in the In Synchronous and Asynchronous Counter modes,
“dsPIC33/PIC24 Family Reference Man- the input clock is derived from the external clock input
ual”, which is available from the Microchip at the T1CK pin.
web site (www.microchip.com).
The Timer modes are determined by the following bits:
2: Some registers and associated bits
described in this section may not be • Timer Clock Source Control bit (TCS): T1CON<1>
available on all devices. Refer to • Timer Synchronization Control bit (TSYNC):
Section 4.0 “Memory Organization” in T1CON<2>
this data sheet for device-specific register • Timer Gate Control bit (TGATE): T1CON<6>
and bit information. Timer control bit setting for different operating modes
The Timer1 module is a 16-bit timer that can operate as are given in the Table 12-1.
a free-running interval timer/counter.
TABLE 12-1: TIMER MODE SETTINGS
The Timer1 module has the following unique features
over other timers: Mode TCS TGATE TSYNC
• Can be operated in Asynchronous Counter mode Timer 0 0 x
from an external clock source Gated Timer 0 1 x
• The external clock input (T1CK) can optionally be
Synchronous 1 x 1
synchronized to the internal device clock and the
Counter
clock synchronization is performed after the prescaler
Asynchronous 1 x 0
A block diagram of Timer1 is shown in Figure 12-1. Counter
0
(1)
FP Prescaler 10 T1CLK
(/n) TGATE
Reset Data
00 TMR1 Latch
TCKPS<1:0>
0 CLK
x1
T1CK Equal
Prescaler Comparator
Sync 1
(/n) CTMU
Edge Control
TGATE Logic
TSYNC
TCKPS<1:0> TCS
PR1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any
attempts by user software to write to the TMR1 register are ignored.
NOTES:
13.0 TIMER2/3 AND TIMER4/5 Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
Note 1: This data sheet summarizes the features listed previously, except for the event trigger;
features of the dsPIC33EPXXXGP50X, this is implemented only with Timer2/3. The operating
dsPIC33EPXXXMC20X/50X and modes and enabled features are determined by setting
PIC24EPXXXGP/MC20X family of the appropriate bit(s) in the T2CON, T3CON, and
devices. It is not intended to be a T4CON, T5CON registers. T2CON and T4CON are
comprehensive reference source. To com- shown in generic form in Register 13-1. T3CON and
plement the information in this data sheet, T5CON are shown in Register 13-2.
refer to “Timers” (DS70362) of the For 32-bit timer/counter operation, Timer2 and Timer4
“dsPIC33/PIC24 Family Reference are the least significant word (lsw); Timer3 and Timer5
Manual”, which is available from the are the most significant word (msw) of the 32-bit timers.
Microchip web site (www.microchip.com).
Note: For 32-bit operation, T3CON and T5CON
2: Some registers and associated bits
control bits are ignored. Only T2CON and
described in this section may not be
T4CON control bits are used for setup and
available on all devices. Refer to
control. Timer2 and Timer4 clock and gate
Section 4.0 “Memory Organization” in
inputs are utilized for the 32-bit timer
this data sheet for device-specific register
modules, but an interrupt is generated
and bit information.
with the Timer3 and Timer5 interrupt flags.
The Timer2/3 and Timer4/5 modules are 32-bit timers, A block diagram for an example 32-bit timer pair (Tim-
which can also be configured as four independent er2/3 and Timer4/5) is shown in Figure 13-3.
16-bit timers with selectable operating modes.
Note: Only Timer2, 3, 4 and 5 can trigger a DMA
As 32-bit timers, Timer2/3 and Timer4/5 operate in
data transfer.
three modes:
• Two Independent 16-Bit Timers (e.g., Timer2 and
Timer3) with all 16-Bit Operating modes (except
Asynchronous Counter mode)
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
They also support these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
• Time Base for Input Capture and Output Compare
Modules (Timer2 and Timer3 only)
• ADC1 Event Trigger (32-bit timer pairs, and
Timer3 and Timer5 only)
0
FP(1) Prescaler 10
TxCLK
(/n) TGATE
Reset Data
00 TMRx Latch
TCKPS<1:0>
CLK
TxCK
Prescaler
Sync x1
(/n) Equal
Comparator
TCKPS<1:0> TGATE
TCS
PRx
0
FP(1) Prescaler 10
TxCLK
(/n) TGATE
Reset Data
00 TMRx Latch
TCKPS<1:0>
CLK
TxCK
Prescaler
Sync x1
(/n) Equal
Comparator
ADC Start of
Conversion Trigger(2)
TCKPS<1:0> TGATE
TCS
PRx
FIGURE 13-3: TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)
PRx PRy
0
TGATE
Equal ADC
Comparator
Data
FP(1) Prescaler 10
(/n) CLK
lsw msw Latch
Reset
00 TMRx TMRy
TCKPS<1:0>
TxCK
Prescaler
Sync x1
(/n)
TMRyHLD
TCKPS<1:0> TGATE
TCS
Data Bus<15:0>
Note 1: The ADC trigger is available on the TMR3:TMR2 andTMR5:TMR4 32-bit timer pairs.
2: Timerx is a Type B timer (x = 2 and 4).
3: Timery is a Type C timer (y = 3 and 5).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer
functions are set through TxCON.
2: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
3: The TyCK pin is not available on all timers. See the “Pin Diagrams” section for the available pins.
NOTES:
Increment
Clock 16
IC Clock 4-Level FIFO Buffer
Sources Select ICxTMR
16
Note 1: The Trigger/Sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for
proper ICx module operation or the Trigger/Sync source must be changed to another source option.
Note 1: The IC32 bit in both the Odd and Even IC must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits). It can be read, set and
cleared in software.
4: Do not use the ICx module as its own Sync or Trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.
6: Each Input Capture x (ICx) module has one PTG input source. See Section 24.0 “Peripheral Trigger
Generator (PTG) Module” for more information.
PTGO8 = IC1
PTGO9 = IC2
PTGO10 = IC3
PTGO11 = IC4
Note 1: The IC32 bit in both the Odd and Even IC must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits). It can be read, set and
cleared in software.
4: Do not use the ICx module as its own Sync or Trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.
6: Each Input Capture x (ICx) module has one PTG input source. See Section 24.0 “Peripheral Trigger
Generator (PTG) Module” for more information.
PTGO8 = IC1
PTGO9 = IC2
PTGO10 = IC3
PTGO11 = IC4
NOTES:
15.0 OUTPUT COMPARE The output compare module can select one of seven
available clock sources for its time base. The module
Note 1: This data sheet summarizes the features compares the value of the timer with the value of one or
of the dsPIC33EPXXXGP50X, two compare registers depending on the operating
dsPIC33EPXXXMC20X/50X and mode selected. The state of the output pin changes
PIC24EPXXXGP/MC20X families of when the timer value matches the compare register
devices. It is not intended to be a compre- value. The output compare module generates either a
hensive reference source. To complement single output pulse or a sequence of output pulses, by
the information in this data sheet, refer to changing the state of the output pin on the compare
“Output Compare” (DS70358) in the match events. The output compare module can also
“dsPIC33/PIC24 Family Reference Man- generate interrupts on compare match events and
ual”, which is available from the Microchip trigger DMA data transfers.
web site (www.microchip.com).
2: Some registers and associated bits Note: See “Output Compare” (DS70358) in
described in this section may not be the “dsPIC33/PIC24 Family Reference
available on all devices. Refer to Manual” for OCxR and OCxRS register
Section 4.0 “Memory Organization” in restrictions.
this data sheet for device-specific register
and bit information.
OCxCON1
OCxCON2
OCxR
CTMU Edge
Rollover/Reset Control Logic
OCxR Buffer
OCx Pin
Comparator
Increment Match
OC Clock Clock Event
Sources Select OCFB
OCxTMR OC Output and
Rollover Fault Logic
Reset
OCFA
Comparator
Match Event Match
Trigger and Event
Trigger and
Sync Sources Sync Logic
OCxRS Buffer
PTG Trigger Input
SYNCSEL<4:0> Rollover/Reset
Trigger(1)
OCx Synchronization/Trigger Event
OCxRS
OCx Interrupt
Reset
Note 1: The Trigger/Sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for
proper OCx module operation or the Trigger/Sync source must be changed to another source option.
R/W-0 U-0 R/W-0, HSC R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0
ENFLTA — OCFLTB OCFLTA TRIGMODE OCM2 OCM1 OCM0
bit 7 bit 0
Note 1: Do not use the OCx module as its own Synchronization or Trigger source.
2: When the OCy module is turned OFF, it sends a trigger out signal. If the OCx module uses the OCy
module as a Trigger source, the OCy module must be unselected as a Trigger source prior to disabling it.
3: Each Output Compare x module (OCx) has one PTG Trigger/Synchronization source. See Section 24.0
“Peripheral Trigger Generator (PTG) Module” for more information.
PTGO0 = OC1
PTGO1 = OC2
PTGO2 = OC3
PTGO3 = OC4
Note 1: Do not use the OCx module as its own Synchronization or Trigger source.
2: When the OCy module is turned OFF, it sends a trigger out signal. If the OCx module uses the OCy
module as a Trigger source, the OCy module must be unselected as a Trigger source prior to disabling it.
3: Each Output Compare x module (OCx) has one PTG Trigger/Synchronization source. See Section 24.0
“Peripheral Trigger Generator (PTG) Module” for more information.
PTGO0 = OC1
PTGO1 = OC2
PTGO2 = OC3
PTGO3 = OC4
16.0 HIGH-SPEED PWM MODULE The high-speed PWMx module contains up to three
PWM generators. Each PWM generator provides two
(dsPIC33EPXXXMC20X/50X PWM outputs: PWMxH and PWMxL. The master time
AND PIC24EPXXXMC20X base generator provides a synchronous signal as a
DEVICES ONLY) common time base to synchronize the various PWM
outputs. The individual PWM outputs are available on
Note 1: This data sheet summarizes the the output pins of the device. The input Fault signals
features of the dsPIC33EPXXXGP50X, and current-limit signals, when enabled, can monitor
dsPIC33EPXXXMC20X/50X and and protect the system by placing the PWM outputs
PIC24EPXXXGP/MC20X families of into a known “safe” state.
devices. It is not intended to be a
Each PWMx can generate a trigger to the ADC module
comprehensive reference source. To com-
to sample the analog signal at a specific instance
plement the information in this data sheet,
during the PWM period. In addition, the high-speed
refer to “High-Speed PWM” (DS70645)
PWMx module also generates a Special Event Trigger
in the “dsPIC33/PIC24 Family Reference
to the ADC module based on either of the two master
Manual”, which is available from the
time bases.
Microchip web site (www.microchip.com).
The high-speed PWMx module can synchronize itself
2: Some registers and associated bits
with an external signal or can act as a synchronizing
described in this section may not be
source to any external device. The SYNCI1 input pin
available on all devices. Refer to
that utilizes PPS, can synchronize the high-speed
Section 4.0 “Memory Organization” in
PWMx module with an external signal. The SYNCO1
this data sheet for device-specific register
pin is an output pin that provides a synchronous signal
and bit information.
to an external device.
The dsPIC33EPXXXMC20X/50X and Figure 16-1 illustrates an architectural overview of the
PIC24EPXXXMC20X devices support a dedicated high-speed PWMx module and its interconnection with
Pulse-Width Modulation (PWM) module with up to the CPU and other peripherals.
6 outputs.
The high-speed PWMx module consists of the 16.1 PWM Faults
following major features:
The PWMx module incorporates multiple external Fault
• Three PWM generators inputs to include FLT1 and FLT2 which are re-
• Two PWM outputs per PWM generator mappable using the PPS feature, FLT3 and FLT4 which
• Individual period and duty cycle for each PWM pair are available only on the larger 44-pin and 64-pin
• Duty cycle, dead time, phase shift and frequency packages, and FLT32 which has been implemented
resolution of TCY/2 (7.14 ns at FCY = 70MHz) with Class B safety features, and is available on a
fixed pin on all dsPIC33EPXXXMC20X/50X and
• Independent Fault and current-limit inputs for
PIC24EPXXXMC20X devices.
six PWM outputs
• Redundant output These Faults provide a safe and reliable way to safely
shut down the PWM outputs when the Fault input is
• Center-Aligned PWM mode
asserted.
• Output override control
• Chop mode (also known as Gated mode) 16.1.1 PWM FAULTS AT RESET
• Special Event Trigger During any Reset event, the PWMx module maintains
• Prescaler for input clock ownership of the Class B Fault, FLT32. At Reset, this
• PWMxL and PWMxH output pin swapping Fault is enabled in Latched mode to ensure the fail-safe
• Independent PWM frequency, duty cycle and power-up of the application. The application software
phase-shift changes for each PWM generator must clear the PWM Fault before enabling the high-
speed motor control PWMx module. To clear the Fault
• Dead-time compensation
condition, the FLT32 pin must first be pulled low
• Enhanced Leading-Edge Blanking (LEB) externally or the internal pull-down resistor in the
functionality CNPDx register can be enabled.
• Frequency resolution enhancement
Note: The Fault mode may be changed using
• PWM capture functionality
the FLTMOD<1:0> bits (FCLCON<1:0>),
Note: In Edge-Aligned PWM mode, the duty regardless of the state of FLT32.
cycle, dead time, phase shift and
frequency resolution are 8.32 ns.
16.1.2 WRITE-PROTECTED REGISTERS To gain write access to these locked registers, the user
application must write two consecutive values of
On dsPIC33EPXXXMC20X/50X and
(0xABCD and 0x4321) to the PWMKEY register to
PIC24EPXXXMC20X devices, write protection is
perform the unlock operation. The write access to the
implemented for the IOCONx and FCLCONx registers.
IOCONx or FCLCONx registers must be the next SFR
The write protection feature prevents any inadvertent
access following the unlock process. There can be no
writes to these registers. This protection feature can be
other SFR accesses during the unlock process and
controlled by the PWMLOCK Configuration bit
subsequent write access. To write to both the IOCONx
(FOSCSEL<6>). The default state of the write
and FCLCONx registers requires two unlock operations.
protection feature is enabled (PWMLOCK = 1). The
write protection feature can be disabled by configuring, The correct unlocking sequence is described in
PWMLOCK = 0. Example 16-1.
SYNCI1
Data Bus
SYNCO1
Synchronization Signal
PWM1 Interrupt(1)
PWM1H
PWM
Generator 1
PWM1L
Fault, Current-Limit
and Dead-Time Compensation
Synchronization Signal
PWM2 Interrupt(1)
CPU PWM2H
PWM
Generator 2
PWM2L
Fault, Current-Limit
and Dead-Time Compensation
Synchronization Signal
Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the
given PWM generator. Refer to the “dsPIC33/PIC24 Family Reference Manual”, “High-Speed PWM”
(DS70645) for more information.
FOSC
SYNCI1
PWMKEY IOCONx and FCLCONx Unlock Register
SYNCO1
PTPER SEVTCMP Special Event Compare Trigger
MUX
16-Bit Data Bus
PWMCONx,
LEBCONx,
AUXCONx TRGCONx
Master Duty Cycle
LEBDLYx
Master Period
DTRx
PWMxH
PWMxL
PWM Generator 2 and PWM Generator 3
FLTx
DTCMPx
Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the
given PWM generator. Refer to the “dsPIC33/PIC24 Family Reference Manual”, “High-Speed PWM”
(DS70645) for more information.
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
2: See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
2: See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
REGISTER 16-2: PTCON2: PWMx PRIMARY MASTER CLOCK DIVIDER SELECT REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
REGISTER 16-3: PTPER: PWMx PRIMARY MASTER TIME BASE PERIOD REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PTPER<15:8>
bit 15 bit 8
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: These bits should not be changed after the PWMx is enabled (PTEN = 1).
3: DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored.
4: The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
5: To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: These bits should not be changed after the PWMx is enabled (PTEN = 1).
3: DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored.
4: The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
5: To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PHASEx<15:0>: PWMx Phase-Shift Value or Independent Time Base Period for the PWM Generator bits
Note 1: If ITB (PWMCONx<9>) = 0, the following applies based on the mode of operation:
Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCON<11:10>) = 00, 01 or 10),
PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs
2: If ITB (PWMCONx<9>) = 1, the following applies based on the mode of operation:
Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10),
PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The secondary PWM generator cannot generate PWMx trigger interrupts.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
Note 1: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The blanking signal is selected via the BLANKSELx bits in the AUXCONx register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
NOTES:
17.0 QUADRATURE ENCODER This chapter describes the Quadrature Encoder Inter-
face (QEI) module and associated operational modes.
INTERFACE (QEI) MODULE
The QEI module provides the interface to incremental
(dsPIC33EPXXXMC20X/50X encoders for obtaining mechanical position data.
and PIC24EPXXXMC20X The operational features of the QEI module include:
DEVICES ONLY) • 32-Bit Position Counter
Note 1: This data sheet summarizes the • 32-Bit Index Pulse Counter
features of the dsPIC33EPXXXGP50X, • 32-Bit Interval Timer
dsPIC33EPXXXMC20X/50X and • 16-Bit Velocity Counter
PIC24EPXXXGP/MC20X families of • 32-Bit Position Initialization/Capture/Compare
devices. It is not intended to be a High register
comprehensive reference source. To com-
• 32-Bit Position Compare Low register
plement the information in this data sheet,
refer to “Quadrature Encoder Interface • x4 Quadrature Count mode
(QEI)” (DS70601) in the “dsPIC33/PIC24 • External Up/Down Count mode
Family Reference Manual”, which is avail- • External Gated Count mode
able from the Microchip web site • External Gated Timer mode
(www.microchip.com).
• Internal Timer mode
2: Some registers and associated bits
Figure 17-1 illustrates the QEI block diagram.
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
HOMEx FHOMEx
DIR_GATE
1
FP
QFDIV COUNT
COUNT_EN
EXTCNT
0
DIVCLK
INDXx FINDXx
Digital
Filter CCM
DIR
QEBx Quadrature COUNT DIR_GATE
Decoder
CNT_DIR
Logic DIR 1’b0
CNTPOL
QEAx EXTCNT
DIR_GATE
PCHGE
PCLLE
CNTCMPx PCLLE
PCLEQ PCHEQ
PCHGE
32-Bit Less Than 32-Bit Greater Than
OUTFNC or Equal Comparator or Equal Comparator
PCLLE PCHGE
FP
INTDIV DIVCLK
32-Bit Less Than or Equal 32-Bit Greater Than or Equal
Compare Register Compare Register
COUNT_EN (POS1CNT)
(QEI1LEC) (QEI1GEC)(1)
(INDX1CNT) 32-Bit Position Counter Register
32-Bit Index Counter Register COUNT_EN
2011-2013 Microchip Technology Inc.
16-Bit Index Counter 32-Bit Interval Timer 16-Bit Velocity 16-Bit Position Counter 32-Bit Initialization and
Hold Register Hold Register QCAPEN
Counter Register Hold Register Capture Register
(INDX1HLD) (INT1HLD) (VEL1CNT) (POS1HLD) (QEI1IC)(1)
Data Bus
Data Bus
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When CCM<1:0> = 10 or 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are
ignored.
2: When CCM<1:0> = 00, and QEA and QEB values match the Index Match Value (IMV), the POSCNTH
and POSCNTL registers are reset. QEA/QEB signals used for the index match have swap and polarity
values applied, as determined by the SWPAB and QEAPOL/QEBPOL bits.
3: The selected clock rate should be at least twice the expected maximum quadrature count rate.
Note 1: When CCM<1:0> = 10 or 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are
ignored.
2: When CCM<1:0> = 00, and QEA and QEB values match the Index Match Value (IMV), the POSCNTH
and POSCNTL registers are reset. QEA/QEB signals used for the index match have swap and polarity
values applied, as determined by the SWPAB and QEAPOL/QEBPOL bits.
3: The selected clock rate should be at least twice the expected maximum quadrature count rate.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0
PCIIRQ(1) PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN
bit 7 bit 0
Note 1: This status bit is only applicable to PIMOD<2:0> modes, ‘011’ and ‘100’.
Note 1: This status bit is only applicable to PIMOD<2:0> modes, ‘011’ and ‘100’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 POSCNT<31:16>: High Word Used to Form 32-Bit Position Counter Register (POS1CNT) bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 POSCNT<15:0>: Low Word Used to Form 32-Bit Position Counter Register (POS1CNT) bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 POSHLD<15:0>: Hold Register for Reading and Writing POS1CNTH bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INDXCNT<31:16>: High Word Used to Form 32-Bit Index Counter Register (INDX1CNT) bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INDXCNT<15:0>: Low Word Used to Form 32-Bit Index Counter Register (INDX1CNT) bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INDXHLD<15:0>: Hold Register for Reading and Writing INDX1CNTH bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEIIC<31:16>: High Word Used to Form 32-Bit Initialization/Capture Register (QEI1IC) bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEIIC<15:0>: Low Word Used to Form 32-Bit Initialization/Capture Register (QEI1IC) bits
REGISTER 17-13: QEI1LECH: QEI1 LESS THAN OR EQUAL COMPARE HIGH WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEILEC<31:24>
bit 15 bit 8
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEILEC<31:16>: High Word Used to Form 32-Bit Less Than or Equal Compare Register (QEI1LEC) bits
REGISTER 17-14: QEI1LECL: QEI1 LESS THAN OR EQUAL COMPARE LOW WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEILEC<15:8>
bit 15 bit 8
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEILEC<15:0>: Low Word Used to Form 32-Bit Less Than or Equal Compare Register (QEI1LEC) bits
REGISTER 17-15: QEI1GECH: QEI1 GREATER THAN OR EQUAL COMPARE HIGH WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIGEC<31:24>
bit 15 bit 8
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEIGEC<31:16>: High Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEI1GEC) bits
REGISTER 17-16: QEI1GECL: QEI1 GREATER THAN OR EQUAL COMPARE LOW WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIGEC<15:8>
bit 15 bit 8
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEIGEC<15:0>: Low Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEI1GEC) bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INTTMR<31:16>: High Word Used to Form 32-Bit Interval Timer Register (INT1TMR) bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INTTMR<15:0>: Low Word Used to Form 32-Bit Interval Timer Register (INT1TMR) bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INTHLD<31:16>: Hold Register for Reading and Writing INT1TMRH bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INTHLD<15:0>: Hold Register for Reading and Writing INT1TMRL bits
Enable
SDIx bit 0 Master Clock
SPIxSR
Transfer Transfer
SPIxBUF
16
Internal Data Bus
R/W-0 R/C-0, HS R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R-0, HS, HC
SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to the value of 1:1.
Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to the value of 1:1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx/ASCLx Clock
I2CxRSR
LSb
I2CxMSK
Write Read
I2CxADD
Read
Read
Collision Write
Detect
I2CxCON
Acknowledge
Generation Read
Clock
Stretching
Write
I2CxTRN
LSb
Shift Clock Read
Reload
Control
Write
Read
FP/2
Note 1: When performing master operations, ensure that the IPMIEN bit is set to ‘0’.
Note 1: When performing master operations, ensure that the IPMIEN bit is set to ‘0’.
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D_A P S R_W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware is set or clear at the end of slave Acknowledge.
bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No bus collision detected
Hardware is set at detection of a bus collision.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when address matches general call address. Hardware is clear at Stop detection.
bit 8 ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at the match of the 2nd byte of the matched 10-bit address. Hardware is clear at Stop
detection.
bit 7 IWCOL: I2Cx Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware is set at the occurrence of a write to I2CxTRN while busy (cleared by software).
bit 6 I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register was still holding the previous byte
0 = No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5 D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware is clear at a device address match. Hardware is set by reception of a slave byte.
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is set or clear when a Start, Repeated Start or Stop is detected.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
20.0 UNIVERSAL ASYNCHRONOUS The primary features of the UARTx module are:
RECEIVER TRANSMITTER • Full-Duplex, 8 or 9-Bit Data Transmission through
(UART) the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
Note 1: This data sheet summarizes the • One or Two Stop bits
features of the dsPIC33EPXXXGP50X,
• Hardware Flow Control Option with UxCTS and
dsPIC33EPXXXMC20X/50X and
UxRTS Pins
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre- • Fully Integrated Baud Rate Generator with 16-Bit
hensive reference source. To complement Prescaler
the information in this data sheet, refer to • Baud Rates Ranging from 4.375 Mbps to 67 bps at
“UART” (DS70582) in the “dsPIC33/ 16x mode at 70 MIPS
PIC24 Family Reference Manual”, which is • Baud Rates Ranging from 17.5 Mbps to 267 bps at
available from the Microchip web site 4x mode at 70 MIPS
(www.microchip.com).
• 4-Deep First-In First-Out (FIFO) Transmit Data
2: Some registers and associated bits Buffer
described in this section may not be
• 4-Deep FIFO Receive Data Buffer
available on all devices. Refer to
Section 4.0 “Memory Organization” in • Parity, Framing and Buffer Overrun Error Detection
this data sheet for device-specific register • Support for 9-bit mode with Address Detect
and bit information. (9th bit = 1)
• Transmit and Receive Interrupts
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X family of devices • A Separate Interrupt for all UARTx Error Conditions
contains two UART modules. • Loopback mode for Diagnostic Support
The Universal Asynchronous Receiver Transmitter • Support for Sync and Break Characters
(UART) module is one of the serial I/O modules available • Support for Automatic Baud Rate Detection
in the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ • IrDA® Encoder and Decoder Logic
50X and PIC24EPXXXGP/MC20X device family. The • 16x Baud Clock Output for IrDA Support
UART is a full-duplex, asynchronous system that can
communicate with peripheral devices, such as personal A simplified block diagram of the UARTx module is
computers, LIN/J2602, RS-232 and RS-485 interfaces. shown in Figure 20-1. The UARTx module consists of
The module also supports a hardware flow control option these key hardware elements:
with the UxCTS and UxRTS pins, and also includes an • Baud Rate Generator
IrDA® encoder and decoder.
• Asynchronous Transmitter
Note: Hardware flow control using UxRTS and • Asynchronous Receiver
UxCTS is not available on all pin count
devices. See the “Pin Diagrams” section
for availability.
IrDA®
Note 1: Refer to the “UART” (DS70582) section in the “dsPIC33/PIC24 Family Reference Manual” for information on
enabling the UARTx module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: This feature is only available on 44-pin and 64-pin devices.
4: This feature is only available on 64-pin devices.
Note 1: Refer to the “UART” (DS70582) section in the “dsPIC33/PIC24 Family Reference Manual” for information on
enabling the UARTx module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: This feature is only available on 44-pin and 64-pin devices.
4: This feature is only available on 64-pin devices.
Note 1: Refer to the “UART” (DS70582) section in the “dsPIC33/PIC24 Family Reference Manual” for information
on enabling the UARTx module for transmit operation.
Note 1: Refer to the “UART” (DS70582) section in the “dsPIC33/PIC24 Family Reference Manual” for information
on enabling the UARTx module for transmit operation.
21.0 ENHANCED CAN (ECAN™) The ECAN module features are as follows:
MODULE (dsPIC33EPXXXGP/ • Implementation of the CAN protocol, CAN 1.2,
MC50X DEVICES ONLY) CAN 2.0A and CAN 2.0B
• Standard and extended data frames
Note 1: This data sheet summarizes the • 0-8 bytes data length
features of the dsPIC33EPXXXGP50X, • Programmable bit rate up to 1 Mbit/sec
dsPIC33EPXXXMC20X/50X and
• Automatic response to remote transmission
PIC24EPXXXGP/MC20X families of
requests
devices. It is not intended to be a
comprehensive reference source. To com- • Up to eight transmit buffers with application speci-
plement the information in this data sheet, fied prioritization and abort capability (each buffer
refer to “Enhanced Controller Area can contain up to 8 bytes of data)
Network (ECAN™)” (DS70353) in the • Up to 32 receive buffers (each buffer can contain
“dsPIC33/PIC24 Family Reference Man- up to 8 bytes of data)
ual”, which is available from the Microchip • Up to 16 full (Standard/Extended Identifier)
web site (www.microchip.com). acceptance filters
2: Some registers and associated bits • Three full acceptance filter masks
described in this section may not be • DeviceNet™ addressing support
available on all devices. Refer to • Programmable wake-up functionality with
Section 4.0 “Memory Organization” in integrated low-pass filter
this data sheet for device-specific register
• Programmable Loopback mode supports self-test
and bit information.
operation
• Signaling via interrupt capabilities for all CAN
21.1 Overview receiver and transmitter error states
The Enhanced Controller Area Network (ECAN) • Programmable clock source
module is a serial interface, useful for communicat- • Programmable link to Input Capture (IC2) module
ing with other CAN modules or microcontroller for time-stamping and network synchronization
devices. This interface/protocol was designed to • Low-power Sleep and Idle mode
allow communications within noisy environments.
The CAN bus module consists of a protocol engine and
The dsPIC33EPXXXGP/MC50X devices contain one
message buffering/control. The CAN protocol engine
ECAN module.
handles all functions for receiving and transmitting
The ECAN module is a communication controller messages on the CAN bus. Messages are transmitted
implementing the CAN 2.0 A/B protocol, as defined in by first loading the appropriate data registers. Status
the BOSCH CAN specification. The module supports and errors can be checked by reading the appropriate
CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B registers. Any message detected on the CAN bus is
Active versions of the protocol. The module implemen- checked for errors and then matched against filters to
tation is a full CAN system. The CAN specification is see if it should be received and stored in one of the
not covered within this data sheet. The reader can refer receive registers.
to the BOSCH CAN specification for further details.
RxF15 Filter
RxF14 Filter
RxF13 Filter
RxF12 Filter
RxF11 Filter
DMA Controller
RxF10 Filter
RxF9 Filter
RxF8 Filter
Control
CPU
Configuration Bus
Logic
CAN Protocol
Engine
Interrupts
CxTx CxRx
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: The buffers, SID, EID, DLC, Data Field, and Receive Status registers are located in DMA RAM.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Only written by module for receive buffers, unused for transmit buffers.
NOTES:
22.0 CHARGE TIME The Charge Time Measurement Unit is a flexible analog
module that provides accurate differential time measure-
MEASUREMENT UNIT (CTMU) ment between pulse sources, as well as asynchronous
Note 1: This data sheet summarizes the pulse generation. Its key features include:
features of the dsPIC33EPXXXGP50X, • Four Edge Input Trigger Sources
dsPIC33EPXXXMC20X/50X and • Polarity Control for Each Edge Source
PIC24EPXXXGP/MC20X family of
• Control of Edge Sequence
devices. It is not intended to be a
comprehensive reference source. To • Control of Response to Edges
complement the information in this data • Precise Time Measurement Resolution of 1 ns
sheet, refer to “Charge Time Measure- • Accurate Current Source Suitable for Capacitive
ment Unit (CTMU)” (DS70661) in the Measurement
“dsPIC33/PIC24 Family Reference Man- • On-Chip Temperature Measurement using a
ual”, which is available on the Microchip Built-in Diode
web site (www.microchip.com).
Together with other on-chip analog modules, the CTMU
2: Some registers and associated bits can be used to precisely measure time, measure
described in this section may not be capacitance, measure relative changes in capacitance
available on all devices. Refer to or generate output pulses that are independent of the
Section 4.0 “Memory Organization” in system clock.
this data sheet for device-specific register
The CTMU module is ideal for interfacing with
and bit information.
capacitive-based sensors.The CTMU is controlled
through three registers: CTMUCON1, CTMUCON2
and CTMUICON. CTMUCON1 and CTMUCON2
enable the module and control edge source selection,
edge source polarity selection and edge sequencing.
The CTMUICON register controls the selection and
trim of the current source.
CTMUCON1 or CTMUCON2(1)
CTMUICON
ITRIM<5:0>
IRNG<1:0>
Current Source
CTED1 Edge
EDG1STAT CTMU
Control Analog-to-Digital
EDG2STAT TGEN Control
CTED2 Logic Trigger
Current Logic
Control
Timer1
OC1 Pulse
IC1 CTPLS
CTMUI to ADC(2) Generator
CMP1
CTMUP
CTMU TEMP(3)
CTMU C1IN1-
Temperature
Sensor
CDelay
CMP1
External Capacitor
for Pulse Generation
ADC
CH0(5)
Note 1: When the CTMU is not actively used, set TGEN = 1, and ensure that EDG1STAT = EDG2STAT. All other settings allow current
to flow into the ADC or the C1IN1- pin. If using the ADC for other purposes besides the CTMU, set IDISSEN = 0. If IDISSEN is
set to ‘1’, it will short the output of the ADC CH0 MUX to VSS.
2: CTMUI connects to the output of the ADC CH0 MUX. When CTMU current is steered into this node, the current will flow out
through the selected ADC channel determined by the CH0 MUX (see the CH0Sx bits in the AD1CHS0 register).
3: CTMU TEMP connects to one of the ADC CH0 inputs; see CH0SA and CH0SB (AD1CHS0<12:8,4:0).
4: If TGEN = 1 and EDG1STAT = EDG2STAT, CTMU current source is still enabled and may be shunted to VSS internally. This
should be considered in low-power applications.
5: The switch connected to ADC CH0 is closed when IDISSEN (CTMUCON1<9>) = 1, and opened when IDISSEN = 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The ADC module Sample-and-Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitance measurement must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This current range is not available to be used with the internal temperature measurement diode.
2: Refer to the CTMU Current Source Specifications (Table 30-56) in Section 30.0 “Electrical
Characteristics” for the current range selection values.
NOTES:
AN1/C2IN1+/RA1 CH123Nx
0 S&H2
+ OPMODE + Alternate Input
1 CH2 ALTS (MUXA/MUXB)
– – Selection
OA2 CH123Sx
VREF+(1) AVDD VREF-(1) AVSS
VREFL 0x
10
AN10/RPI28/RA12 11
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
CH123Nx
S&H3 VCFG<2:0> ADC1BUF0(4)
0
2011-2013 Microchip Technology Inc.
ADC1BUFE(4)
CH123Nx
ADC1BUFF(4)
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
3: These bits can be updated with Step commands from the PTG module. See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for more information.
4: When ADDMAEN (AD1CON4<8>) = 1, enabling DMA, only ADC1BUF0 is used.
5: OA3 is not available for 28-pin devices.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
AD1CON3<15>
ADC Internal 1
RC Clock(2)
TAD
AD1CON3<7:0> 0
ADC Conversion
TP(1) Clock Multiplier
1, 2, 3, 4, 5,..., 256
Note 1: TP = 1/FP.
2: See the ADC electrical specifications in Section 30.0 “Electrical Characteristics” for the
exact RC clock value.
23.2 ADC Helpful Tips 5. Enabling op amps, comparator inputs and exter-
nal voltage references can limit the availability of
1. The SMPIx control bits in the AD1CON2 register: analog inputs (ANx pins). For example, when Op
a) Determine when the ADC interrupt flag is Amp 2 is enabled, the pins for AN0, AN1 and AN2
set and an interrupt is generated, if are used by the op amp’s inputs and output. This
enabled. negates the usefulness of Alternate Input mode
b) When the CSCNA bit in the AD1CON2 reg- since the MUXA selections use AN0-AN2.
isters is set to ‘1’, this determines when the Carefully study the ADC block diagram to deter-
ADC analog scan channel list, defined in mine the configuration that will best suit your
the AD1CSSL/AD1CSSH registers, starts application. Configuration examples are avail-
over from the beginning. able in the “Analog-to-Digital Converter
c) When the DMA peripheral is not used (ADC)” (DS70621) section in the “dsPIC33/
(ADDMAEN = 0), this determines when the PIC24 Family Reference Manual”.
ADC Result Buffer Pointer to ADC1BUF0-
ADC1BUFF gets reset back to the 23.3 ADC Resources
beginning at ADC1BUF0.
Many useful resources are provided on the main prod-
d) When the DMA peripheral is used uct page of the Microchip web site for the devices listed
(ADDMAEN = 1), this determines when the in this data sheet. This product page, which can be
DMA Address Pointer is incremented after a accessed using this link, contains the latest updates
sample/conversion operation. ADC1BUF0 is and additional information.
the only ADC buffer used in this mode. The
ADC Result Buffer Pointer to ADC1BUF0- Note: In the event you are not able to access the
ADC1BUFF gets reset back to the beginning product page using the link above, enter
at ADC1BUF0. The DMA address is this URL in your browser:
incremented after completion of every 32nd http://www.microchip.com/wwwproducts/
sample/conversion operation. Conversion Devices.aspx?dDocName=en555464
results are stored in the ADC1BUF0 register
for transfer to RAM using DMA. 23.3.1 KEY RESOURCES
2. When the DMA module is disabled • “Analog-to-Digital Converter (ADC)”
(ADDMAEN = 0), the ADC has 16 result buffers. (DS70621) in the “dsPIC33/PIC24 Family
ADC conversion results are stored sequentially Reference Manual”
in ADC1BUF0-ADC1BUFF, regardless of which • Code Samples
analog inputs are being used subject to the
• Application Notes
SMPIx bits and the condition described in 1c)
above. There is no relationship between the • Software Libraries
ANx input being measured and which ADC • Webinars
buffer (ADC1BUF0-ADC1BUFF) that the • All Related “dsPIC33/PIC24 Family Reference
conversion results will be placed in. Manual” Sections
3. When the DMA module is enabled • Development Tools
(ADDMAEN = 1), the ADC module has only
1 ADC result buffer (i.e., ADC1BUF0) per ADC
peripheral and the ADC conversion result must
be read, either by the CPU or DMA Controller,
before the next ADC conversion is complete to
avoid overwriting the previous value.
4. The DONE bit (AD1CON1<0>) is only cleared at
the start of each conversion and is set at the
completion of the conversion, but remains set
indefinitely, even through the next sample phase
until the next conversion begins. If application
code is monitoring the DONE bit in any kind of
software loop, the user must consider this behav-
ior because the CPU code execution is faster
than the ADC. As a result, in Manual Sample
mode, particularly where the user’s code is set-
ting the SAMP bit (AD1CON1<1>), the DONE bit
should also be cleared by the user application
just before setting the SAMP bit.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HC, HS R/C-0, HC, HS
SSRC2 SSRC1 SSRC0 SSRCG SIMSAM ASAM SAMP DONE(3)
bit 7 bit 0
Note 1: See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
2: This setting is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
3: Do not clear the DONE bit in software if Auto-Sample is enabled (ASAM = 1).
Note 1: See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
2: This setting is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
3: Do not clear the DONE bit in software if Auto-Sample is enabled (ASAM = 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is only used if SSRC<2:0> (AD1CON1<7:5>) = 111 and SSRCG (AD1CON1<4>) = 0.
2: This bit is not used if ADRC (AD1CON3<15>) = 1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample MUXB bit
In 12-bit mode (AD21B = 1), CH123SB is Unimplemented and is Read as ‘0’:
ADC Channel
Value
CH1 CH2 CH3
(2) OA1/AN3 OA2/AN0 OA3/AN6
1
0(1,2) OA2/AN0 AN1 AN2
Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2
and 3.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1);
otherwise, the ANx input is used.
ADC Channel
Value
CH1 CH2 CH3
(2)
1 OA1/AN3 OA2/AN0 OA3/AN6
0(1,2) OA2/AN0 AN1 AN2
Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2
and 3.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1);
otherwise, the ANx input is used.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: Channel 0 Negative Input Select for Sample MUXB bit
1 = Channel 0 negative input is AN1(1)
0 = Channel 0 negative input is VREFL
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample MUXB bits(1)
11111 = Open; use this selection with CTMU capacitive and time measurement
11110 = Channel 0 positive input is connected to the CTMU temperature measurement diode (CTMU TEMP)
11101 = Reserved
11100 = Reserved
11011 = Reserved
11010 = Channel 0 positive input is the output of OA3/AN6(2,3)
11001 = Channel 0 positive input is the output of OA2/AN0(2)
11000 = Channel 0 positive input is the output of OA1/AN3(2)
10111 = Reserved
•
•
•
10000 = Reserved
01111 = Channel 0 positive input is AN15(3)
01110 = Channel 0 positive input is AN14(3)
01101 = Channel 0 positive input is AN13(3)
•
•
•
00010 = Channel 0 positive input is AN2(3)
00001 = Channel 0 positive input is AN1(3)
00000 = Channel 0 positive input is AN0(3)
bit 7 CH0NA: Channel 0 Negative Input Select for Sample MUXA bit
1 = Channel 0 negative input is AN1(1)
0 = Channel 0 negative input is VREFL
bit 6-5 Unimplemented: Read as ‘0’
Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2
and 3.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1);
otherwise, the ANx input is used.
3: See the “Pin Diagrams” section for the available analog channels for each device.
Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2
and 3.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1);
otherwise, the ANx input is used.
3: See the “Pin Diagrams” section for the available analog channels for each device.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: All AD1CSSH bits can be selected by user software. However, inputs selected for scan, without a
corresponding input on the device, convert VREFL.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1);
otherwise, the ANx input is used.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: On devices with less than 16 analog inputs, all AD1CSSL bits can be selected by the user. However,
inputs selected for scan, without a corresponding input on the device, convert VREFL.
2: CSSx = ANx, where x = 0-15.
24.0 PERIPHERAL TRIGGER The PTG module has the following major features:
GENERATOR (PTG) MODULE • Multiple clock sources
• Two 16-bit general purpose timers
Note 1: This data sheet summarizes the
• Two 16-bit general limit counters
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and • Configurable for rising or falling edge triggering
PIC24EPXXXGP/MC20X families of • Generates processor interrupts to include:
devices. It is not intended to be a - Four configurable processor interrupts
comprehensive reference source. To - Interrupt on a Step event in Single-Step mode
complement the information in this data - Interrupt on a PTG Watchdog Timer time-out
sheet, refer to “Peripheral Trigger
• Able to receive trigger signals from these
Generator (PTG)” (DS70669) in the
peripherals:
“dsPIC33/PIC24 Family Reference
Manual”, which is available from the - ADC
Microchip web site (www.microchip.com). - PWM
2: Some registers and associated bits - Output Compare
described in this section may not be - Input Capture
available on all devices. Refer to - Op Amp/Comparator
Section 4.0 “Memory Organization” in - INT2
this data sheet for device-specific register
• Able to trigger or synchronize to these
and bit information.
peripherals:
- Watchdog Timer
24.1 Module Introduction - Output Compare
The Peripheral Trigger Generator (PTG) provides a - Input Capture
means to schedule complex high-speed peripheral - ADC
operations that would be difficult to achieve using soft- - PWM
ware. The PTG module uses 8-bit commands, called
- Op Amp/Comparator
“Steps”, that the user writes to the PTG Queue
registers (PTGQUE0-PTGQUE7), which perform oper-
ations, such as wait for input signal, generate output
trigger and wait for timer.
PTGHOLD
PTGL0<15:0> PTGTxLIM<15:0> PTGCxLIM<15:0> PTGSDLIM<15:0>
PTGADJ
PTG General PTG Step
PTG Loop
Purpose Counter x Delay Timer
Step Command Timerx
PTGBTE<15:0>
PTGCST<15:0>
PTGDIV<4:0>
Trigger Outputs
PTGO0
PTGCLK<2:0> •
•
•
PTGO31
16-Bit Data Bus
FP
Clock Inputs
TAD
T1CLK
T2CLK
PTG Control Logic
T3CLK Step Command
FOSC
Step Command
PTG Interrupts
PTG0IF
•
PWM •
OC1
Trigger Inputs
•
OC2 PTG3IF
IC1
CMPx
ADC
INT2
AD1CHS0<15:0>
PTGQPTR<4:0>
PTG Watchdog
Timer(1) PTGWDTIF
PTGQUE0
PTGQUE1
PTGQUE2
PTGQUE3 Command
PTGQUE4 Decoder
PTGQUE5
PTGQUE6
PTGQUE7
PTGSTEPIF
Note 1: This is a dedicated Watchdog Timer for the PTG module and is independent of the device Watchdog Timer.
Note 1: These bits apply to the PTGWHI and PTGWLO commands only.
2: This bit is only used with the PTGCTRL step command software trigger option.
3: Use of the PTG Single-Step mode is reserved for debugging tools only.
Note 1: These bits apply to the PTGWHI and PTGWLO commands only.
2: This bit is only used with the PTGCTRL step command software trigger option.
3: Use of the PTG Single-Step mode is reserved for debugging tools only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
2: This register is only used with the PTGCTRL OPTION = 1111 Step command.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
2: This register is only used with the PTGCTRL OPTION = 1111 Step command.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: A base Step delay of one PTG clock is added to any value written to the PTGSDLIM register
(Step Delay = (PTGSDLIM) + 1).
2: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 STEP(2x + 1)<7:0>: PTG Step Queue Pointer Register bits(2)
A queue location for storage of the STEP(2x + 1) command byte.
bit 7-0 STEP(2x)<7:0>: PTG Step Queue Pointer Register bits(2)
A queue location for storage of the STEP(2x) command byte.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
2: Refer to Table 24-1 for the Step command encoding.
3: The Step registers maintain their values on any type of Reset.
NOTES:
CCH<1:0> (CMxCON<1:0>)
CxIN1- 00
Op Amp/Comparator(2)
CXIN2-(1) 01
VIN- – Blanking Digital CxOUT(1)
CMPx Function Filter
VIN+ (see Figure 25-4) (see Figure 25-5) PTG Trigger
CxIN1+ 0 + Input
OPMODE (CMxCON<10>)
CVREFIN(1) 1
– RINT1
Op Ampx OAxOUT/ANx
+
OAx/ANx(3)
(to ADC)
CREF (CMxCON<4>)
Note 1: This input/output is not available as a selection when configured as an op amp (OPMODE (CMxCON<10>) = 1).
2: This module can be configured either as an op amp or a comparator using the OPMODE bit.
3: When configured as an op amp (OPMODE = 1), the ADC samples the op amp output; otherwise, the ADC
samples the ANx pin.
CCH<1:0> (CM4CON<1:0>)
OA1/AN3 01
OA2/AN0 10
OA3/AN6 11
CVREFIN 0
CREF (CMxCON<4>)
VREFSEL
(1)
(CVRCON<10>)
CVRSS = 1
VREF+ CVRSRC CVRCON<3:0>
CVR3
CVR2
CVR1
AVDD CVR0 1
CVRSS = 0 8R
CVREFIN
R
CVREN 0
R
R
16-to-1 MUX
16 Steps
CVREF1O
R CVR1OE
(CVRCON<6>)
R
R
CVRR 8R AVDD
CVREF2O(2)
AVSS
AVSS
CVR2OE
(CVRCON<14>)
Note 1: In order to operate with CVRSS = 1, at least one of the comparator modules must be enabled.
2: This reference is (AVDD + AVSS)/2.
SELSRCA<3:0>
(CMxMSKSRC<3:0>)
MUX A
MAI Blanking
Blanking “AND-OR” Function Logic
Signals MAI
MBI ANDI
AND
SELSRCB<3:0> MCI
(CMxMSKSRC<7:4)
MAI HLMS
(CMxMSKCON<15)
MUX B
MCI
SELSRCC<3:0>
(CMxMSKSRC<11:8)
CMxMSKCON
MUX C
Blanking MCI
Signals
TxCLK(1,2) 1xx
SYNCO1(3) 010
FP(4) 000
FOSC(4) 001
CFDIV
CFSEL<2:0> CFLTREN
(CMxFLTR<6:4>) (CMxFLTR<3>)
RFEEDBACK(2)
R1
VIN CxIN1- –
RINT1(1)
Op Ampx OAxOUT
Bias CxIN1+ (VOAXOUT)
+
Voltage(4) VADC
OAx
(to ADC)
ADC(3)
R FEEDBACK + R INT1
V ADC = --------------------------------------------------- Bias Voltage – V IN
R1
R FEEDBACK
V OAxOUT = ------------------------------ Bias Voltage – VIN
R1
RFEEDBACK(2)
R1
VIN CxIN1- –
RINT1(1)
Op Ampx OAxOUT
(VOAXOUT)
Bias CxIN1+
+
Voltage(4)
ANy
ADC(3)
R FEEDBACK
V OAxOUT = ------------------------------ Bias Voltage – VIN
R1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register,
CMxCON<9>.
2: Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON<8>.
Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register,
CMxCON<9>.
2: Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON<8>.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
2: This output is not available when OPMODE (CMxCON<10>) = 1.
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
2: This output is not available when OPMODE (CMxCON<10>) = 1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: CVRxOE overrides the TRISx and the ANSELx bit settings.
2: In order to operate with CVRSS = 1, at least one of the comparator modules must be enabled.
NOTES:
26.0 PROGRAMMABLE CYCLIC The programmable CRC generator offers the following
features:
REDUNDANCY CHECK (CRC)
GENERATOR • User-programmable (up to 32nd order)
polynomial CRC equation
Note 1: This data sheet summarizes the • Interrupt output
features of the dsPIC33EPXXXGP50X, • Data FIFO
dsPIC33EPXXXMC20X/50X and
The programmable CRC generator provides a
PIC24EPXXXGP/MC20X families of
hardware implemented method of quickly generating
devices. It is not intended to be a compre-
checksums for various networking and security
hensive reference source. To complement
applications. It offers the following features:
the information in this data sheet, refer to
“Programmable Cyclic Redundancy • User-programmable CRC polynomial equation,
Check (CRC)” (DS70346) of the up to 32 bits
“dsPIC33/PIC24 Family Reference Man- • Programmable shift direction (little or big-endian)
ual”, which is available from the Microchip • Independent data and polynomial lengths
web site (www.microchip.com).
• Configurable interrupt output
2: Some registers and associated bits • Data FIFO
described in this section may not be
available on all devices. Refer to A simplified block diagram of the CRC generator is
Section 4.0 “Memory Organization” in shown in Figure 26-1. A simple version of the CRC shift
this data sheet for device-specific register engine is shown in Figure 26-2.
and bit information.
CRCDATH CRCDATL
CRCISEL
2 * FP Shift Clock
Shift Buffer
1
Set CRCIF
0
0 1 LENDIAN
CRCWDATH CRCWDATL
CRCWDATH CRCWDATL
Read/Write Bus
Shift Buffer
Data Bit 0 Bit 1 Bit 2 Bit n(2)
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
2: Polynomial length n is determined by ([PLEN<4:0>] + 1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
NOTES:
Reserved 0057EC 32
00AFEC 64
0157EC 128 — — — — — — — — —
02AFEC 256
0557EC 512
Reserved 0057EE 32
00AFEE 64
0157EE 128 — — — — — — — — —
02AFEE 256
0557EE 512
FICD 0057F0 32
00AFF0 64
0157F0 128 — Reserved(3) — JTAGEN Reserved(2) Reserved(3) — ICS<1:0>
02AFF0 256
0557F0 512
FPOR 0057F2 32
00AFF2 64
0157F2 128 — WDTWIN<1:0> ALTI2C2 ALTI2C1 Reserved(3) — — —
02AFF2 256
0557F2 512
FWDT 0057F4 32
00AFF4 64
0157F4 128 — FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
02AFF4 256
0557F4 512
FOSC 0057F6 32
00AFF6 64
0157F6 128 — FCKSM<1:0> IOL1WAY — — OSCIOFNC POSCMD<1:0>
02AFF6 256
0557F6 512
FOSCSEL 0057F8 32
00AFF8 64
0157F8 128 — IESO PWMLOCK(1) — — — FNOSC<2:0>
02AFF8 256
0557F8 512
FGS 0057FA 32
00AFFA 64
0157FA 128 — — — — — — — GCP GWRP
02AFFA 256
0557FA 512
Reserved 0057FC 32
00AFFC 64
0157FC 128 — — — — — — — — —
02AFFC 256
0557FC 512
Reserved 057FFE 32
00AFFE 64
0157FE 128 — — — — — — — — —
02AFFE 256
0557FE 512
Legend: — = unimplemented, read as ‘1’.
Note 1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2: This bit is reserved and must be programmed as ‘0’.
3: These bits are reserved and must be programmed as ‘1’.
R R R R R R R R
DEVID<15:8>(1)
bit 15 bit 8
R R R R R R R R
DEVID<7:0>(1)
bit 7 bit 0
Note 1: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for the list of device ID values.
R R R R R R R R
(1)
DEVREV<15:8>
bit 15 bit 8
R R R R R R R R
(1)
DEVREV<7:0>
bit 7 bit 0
Note 1: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for the list of device revision values.
Sleep/Idle
WDTPRE WDTPOST<3:0>
SWDTEN WDT
FWDTEN Wake-up
1
RS RS
Prescaler Postscaler
LPRC Clock (Divide-by-N1) (Divide-by-N2) WDT
0 Reset
WINDIS
WDT Window Select
WDTWIN<1:0>
CLRWDT Instruction
28.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
Note: This data sheet summarizes the features • The W register (with or without an address
of the dsPIC33EPXXXGP50X, modifier) or file register (specified by the value of
dsPIC33EPXXXMC20X/50X and ‘Ws’ or ‘f’)
PIC24EPXXXGP/MC20X families of
• The bit in the W register or file register (specified
devices. It is not intended to be a
by a literal value or indirectly by the contents of
comprehensive reference source. To
register ‘Wb’)
complement the information in this data
sheet, refer to the related section of the The literal instructions that involve data movement can
“dsPIC33/PIC24 Family Reference use some of the following operands:
Manual”, which is available from the • A literal value to be loaded into a W register or file
Microchip web site (www.microchip.com). register (specified by ‘k’)
The dsPIC33EP instruction set is almost identical to • The W register or file register where the literal
that of the dsPIC30F and dsPIC33F. The PIC24EP value is to be loaded (specified by ‘Wb’ or ‘f’)
instruction set is almost identical to that of the PIC24F However, literal instructions that involve arithmetic or
and PIC24H. logical operations use some of the following operands:
Most instructions are a single program memory word • The first source operand, which is a register ‘Wb’
(24 bits). Only three instructions require two program without any address modifier
memory locations. • The second source operand, which is a literal
Each single-word instruction is a 24-bit word, divided value
into an 8-bit opcode, which specifies the instruction • The destination of the result (only if not the same
type and one or more operands, which further specify as the first source operand), which is typically a
the operation of the instruction. register ‘Wd’ with or without an address modifier
The instruction set is highly orthogonal and is grouped The MAC class of DSP instructions can use some of the
into five basic categories: following operands:
• Word or byte-oriented operations • The accumulator (A or B) to be used (required
• Bit-oriented operations operand)
• Literal operations • The W registers to be used as the two operands
• DSP operations • The X and Y address space prefetch operations
• Control operations • The X and Y address space prefetch destinations
Table 28-1 lists the general symbols used in describing • The accumulator write back destination
the instructions. The other DSP instructions do not involve any
The dsPIC33E instruction set summary in Table 28-2 multiplication and can include:
lists all the instructions, along with the status flags • The accumulator to be used (required)
affected by each instruction. • The source or destination operand (designated as
Most word or byte-oriented W register instructions Wso or Wdo, respectively) with or without an
(including barrel shift instructions) have three address modifier
operands: • The amount of shift specified by a W register ‘Wn’
• The first source operand, which is typically a or a literal value
register ‘Wb’ without any address modifier The control instructions can use some of the following
• The second source operand, which is typically a operands:
register ‘Ws’ with or without an address modifier • A program memory address
• The destination of the result, which is typically a • The mode of the Table Read and Table Write
register ‘Wd’ with or without an address modifier instructions
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
Most instructions are a single word. Certain double-word two or three cycles if the skip is performed, depending on
instructions are designed to provide all the required whether the instruction being skipped is a single-word or
information in these 48 bits. In the second word, the two-word instruction. Moreover, double-word moves
8 MSbs are ‘0’s. If this second word is executed as an require two cycles.
instruction (by itself), it executes as a NOP.
Note: For more details on the instruction set,
The double-word instructions execute in two instruction refer to the “16-bit MCU and DSC
cycles. Programmer’s Reference Manual”
Most single-word instructions are executed in a single (DS70157).
instruction cycle, unless a conditional test is true, or the For more information on instructions that
Program Counter is changed as a result of the instruction, take more than one instruction cycle to
or a PSV or Table Read is performed, or an SFR register execute, refer to “CPU” (DS70359) in
is read. In these cases, the execution takes multiple the “dsPIC33/PIC24 Family Reference
instruction cycles with the additional instruction cycle(s) Manual”, particularly the “Instruction
executed as a NOP. Certain instructions that involve Flow Types” section.
skipping over the subsequent instruction require either
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
29.6 MPLAB X SIM Software Simulator 29.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB
buffer and logic analyzer display extend the power of IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 29.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
29.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the
programs all 8, 16 and 32-bit MCU, and DSC devices target via a Microchip debug (RJ-11) connector (com-
with the easy-to-use, powerful graphical user interface of patible with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 29.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display
downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod-
significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
4: Exceptions are: dsPIC33EPXXXGP502, dsPIC33EPXXXMC202/502 and PIC24EPXXXGP/MC202 devices,
which have a maximum sink/source capability of 130 mA.
30.1 DC Characteristics
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSC2
VSS 15 pF for OSC2 output
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKO
OS41 OS40
I/O Pin
(Input)
DI35
DI40
MCLR
TMCLR
(SY20)
BOR
Reset Sequence
TABLE 30-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions
No.
SY00 TPU Power-up Period — 400 600 s
SY10 TOST Oscillator Start-up Time — 1024 TOSC — — TOSC = OSC1 period
SY12 TWDT Watchdog Timer 0.81 0.98 1.22 ms WDTPRE = 0,
Time-out Period WDTPOST<3:0> = 0000, using
LPRC tolerances indicated in F21
(see Table 30-20) at +85ºC
3.26 3.91 4.88 ms WDTPRE = 1,
WDTPOST<3:0> = 0000, using
LPRC tolerances indicated in F21
(see Table 30-20) at +85ºC
SY13 TIOZ I/O High-Impedance 0.68 0.72 1.2 s
from MCLR Low or
Watchdog Timer Reset
SY20 TMCLR MCLR Pulse Width (low) 2 — — s
SY30 TBOR BOR Pulse Width (low) 1 — — s
SY35 TFSCM Fail-Safe Clock Monitor — 500 900 s -40°C to +85°C
Delay
SY36 TVREG Voltage Regulator — — 30 s
Standby-to-Active mode
Transition Time
SY37 TOSCDFRC FRC Oscillator Start-up 46 48 54 s
Delay
SY38 TOSCDLPRC LPRC Oscillator Start-up — — 70 s
Delay
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRx
TABLE 30-24: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol Characteristic(1) Min. Typ. Max. Units Conditions
No.
TB10 TtxH TxCK High Synchronous Greater of: — — ns Must also meet
Time mode 20 or Parameter TB15,
(TCY + 20)/N N = prescale
value
(1, 8, 64, 256)
TB11 TtxL TxCK Low Synchronous Greater of: — — ns Must also meet
Time mode 20 or Parameter TB15,
(TCY + 20)/N N = prescale
value
(1, 8, 64, 256)
TB15 TtxP TxCK Synchronous Greater of: — — ns N = prescale
Input mode 40 or value
Period (2 TCY + 40)/N (1, 8, 64, 256)
TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns
Clock Edge to Timer
Increment
Note 1: These parameters are characterized, but are not tested in manufacturing.
TABLE 30-25: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol Characteristic(1) Min. Typ. Max. Units Conditions
No.
TC10 TtxH TxCK High Synchronous TCY + 20 — — ns Must also meet
Time Parameter TC15
TC11 TtxL TxCK Low Synchronous TCY + 20 — — ns Must also meet
Time Parameter TC15
TC15 TtxP TxCK Input Synchronous, 2 TCY + 40 — — ns N = prescale
Period with prescaler value
(1, 8, 64, 256)
TC20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns
Clock Edge to Timer
Increment
Note 1: These parameters are characterized, but are not tested in manufacturing.
ICx
IC10 IC11
IC15
OCx
(Output Compare x
or PWMx Mode)
OC11 OC10
OC20
OCFA
OC15
OCx
MP30
Fault Input
(active-low)
MP20
PWMx
MP11 MP10
PWMx
QEB
TQ10 TQ11
TQ15 TQ20
POSCNT
TQ36
QEA
(input)
TQ31 TQ30
TQ35
QEB
(input)
TQ41 TQ40
TQ31 TQ30
TQ35
QEB
Internal
QEA
(input)
QEB
(input)
Ungated
Index
TQ51 TQ50
Index Internal
TQ55
Position Counter
Reset
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SP36
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SP30, SP31
TABLE 30-34: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions
SP10 FscP Maximum SCK2 Frequency — — 15 MHz (Note 3)
SP20 TscF SCK2 Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCK2 Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO2 Data Output Valid after — 6 20 ns
TscL2doV SCK2 Edge
SP36 TdiV2scH, SDO2 Data Output Setup to 30 — — ns
TdiV2scL First SCK2 Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
SCK2
(CKP = 1)
SP30, SP31
SP40
SP41
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SP40 SP41
SP60
SS2
SP50 SP52
SCK2
(CKP = 0)
SCK2
(CKP = 1) SP36
SP35
SP72 SP73
SP40
SP60
SS2
SP50 SP52
SCK2
(CKP = 0)
SCK2
(CKP = 1) SP36
SP35
SP72 SP73
SP40
SS2
SP50 SP52
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SP72 SP73
SP35 SP36
SP40
SS2
SP50 SP52
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SP72 SP73
SP35 SP36
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SP36
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SP30, SP31
TABLE 30-42: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions
SP10 FscP Maximum SCK1 Frequency — — 15 MHz (Note 3)
SP20 TscF SCK1 Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCK1 Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO1 Data Output Valid after — 6 20 ns
TscL2doV SCK1 Edge
SP36 TdiV2scH, SDO1 Data Output Setup to 30 — — ns
TdiV2scL First SCK1 Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
SP36
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SP30, SP31
SP40
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SP40 SP41
SP60
SS1
SP50 SP52
SCK1
(CKP = 0)
SCK1
(CKP = 1) SP36
SP35
SP72 SP73
SP60
SS1
SP50 SP52
SCK1
(CKP = 0)
SCK1
(CKP = 1) SP36
SP35
SP72 SP73
SP40
SS1
SP50 SP52
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SP72 SP73
SP35 SP36
SP40
SS1
SP50 SP52
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SP72 SP73
SP35 SP36
SP40
FIGURE 30-30: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31 IM34
IM30 IM33
SDAx
Start Stop
Condition Condition
SDAx
In
IM40 IM40 IM45
SDAx
Out
FIGURE 30-32: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31 IS34
IS30 IS33
SDAx
Start Stop
Condition Condition
SDAx
In
IS40 IS40 IS45
SDAx
Out
CA10, CA11
CxRx Pin
(input)
CA20
UA20
AD50
ADCLK
SAMP
AD61
AD60
TSAMP AD55
DONE
AD1IF
1 2 3 4 5 6 7 8 9
AD50
ADCLK
SAMP
AD61
AD60
DONE
AD1IF
1 2 3 4 5 6 7 8 5 6 7 8
FIGURE 30-38: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010)
AD50
ADCLK
Instruction
Execution Set ADON
AD62
SAMP
TSAMP AD55 AD55 TSAMP AD55
AD1IF
DONE
1 2 3 4 5 6 7 3 4 5 6 8
2 – Sampling starts after discharge period. TSAMP is described in 6 – One TAD for end of conversion.
“Analog-to-Digital Converter (ADC)” (DS70621)
in the “dsPIC33/PIC24 Family Reference Manual”. 7 – Begin conversion of next channel.
3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>.
4 – Convert bit 8.
NOTES:
Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which
the total operating time from +125°C to +150°C will be greater than 1,000 hours is not warranted without
prior written approval from Microchip Technology Inc.
3: Refer to the “Pin Diagrams” section for 5V tolerant pins.
4: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2).
31.2 AC Characteristics and Timing Parameters in this section begin with an H, which denotes
Parameters High temperature. For example, Parameter OS53 in
Section 30.2 “AC Characteristics and Timing
The information contained in this section defines Parameters” is the Industrial and Extended temperature
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X equivalent of HOS53.
and PIC24EPXXXGP/MC20X AC characteristics and
timing parameters for high-temperature devices.
However, all AC timing specifications in this section are
the same as those in Section 30.2 “AC Characteristics
and Timing Parameters”, with the exception of the
parameters listed in this section.
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSC2
VSS 15 pF for OSC2 output
For example: FOSC = 32 MHz, DCLK = 5%, SPIx bit rate clock (i.e., SCKx) is 2 MHz.
D CLK 5% 5%
SPI SCK Jitter = ------------------------------ = ---------- = -------- = 1.25%
16 4
32
--------------------
MHz
2 MHz
NOTES:
FIGURE 32-1: VOH – 4x DRIVER PINS FIGURE 32-3: VOL – 4x DRIVER PINS
VOH (V)
-0.050 VOL(V)
0.050
-0.045 3.6V
0.045 3.6V
-0.040
3.3V 0.040 3.3V
-0.035
0.035 3V
-0.030 3V
0.030
IOH(A)
IOH(A)
-0.025 0.025
-0.020 0.020
-0.015 Absolute Maximum 0.015 Absolute Maximum
-0.010 0.010
-0.005 0.005
0.000 0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FIGURE 32-2: VOH – 8x DRIVER PINS FIGURE 32-4: VOL – 8x DRIVER PINS
8X
VOH(V) VOL(V)
-0.080 0.080 3.6V
3.6V
-0.070 0.070 3.3V
3.3V
-0.060 0.060 3V
-0.050 3V 0.050
IOH(A)
IOH(A)
-0.040 0.040
DS70000657H-page 475
0 030
-0.030 0.030
Absolute Maximum Absolute Maximum
-0.020 0 020
0.020
-0.010 0.010
0.000 0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FIGURE 32-5: TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 32-7: TYPICAL IDOZE CURRENT @ VDD = 3.3V
DS70000657H-page 476
45.00
700.00
40.00
600.00
35.00
500.00 30.00
400.00
25.00
20.00
300.00
IDOZE
15.00
200.00 10.00
100.00 5.00
0.00
0.00
1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
Doze Ratio
Temperature (Celsius)
FIGURE 32-6: TYPICAL/MAXIMUM IDD CURRENT @ VDD = 3.3V FIGURE 32-8: TYPICAL IIDLE CURRENT @ VDD = 3.3V
70
25.00
60
50 20.00
IDD (mA)
40 15.00
Typ.
30 Max.
10.00
IIDLE (EC+PLL)
20
5.00
10 IIDLE (EC)
0.00
0
0 10 20 30 40 50 60 70
0 10 20 30 40 50 60 70 80 MIPS
MIPS
FIGURE 32-9: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 32-11: TYPICAL CTMU TEMPERATURE DIODE
2011-2013 Microchip Technology Inc.
FORWARD VOLTAGE
7370 0.800
7360 0.750
65 µ
VF = 0.721 A, V
7350 0.700 F
VR
= -1
.56
mV
7340 0.650 VF = 0.658 /ºC
6.5
µA,
7330 VF
0.600 VR
= -1
VF = 0.598 .74
m V/ºC
7320 0.550
0 .6
5µ
A, V
7310 0.500 FVR
= -1
.9 2
7300 0.450 mV
/ºC
7290 0.400
7280 0.350
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
33
LPRC Frequency (kHz)
32
31
DS70000657H-page 477
30
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature (Celsius)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
NOTES:
XXXXXXXXXXXXXXXXX dsPIC33EP64GP
XXXXXXXXXXXXXXXXX 502-I/SP e3
YYWWNNN 1310017
XXXXXXXXXXXXXXXXXXXX dsPIC33EP64GP
XXXXXXXXXXXXXXXXXXXX 502-I/SO e3
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YYWWNNN
XXXXXXXXXXXX dsPIC33EP64
XXXXXXXXXXXX GP502-I/SS e3
YYWWNNN 1310017
XXXXXXXX 33EP64GP
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YYWWNNN 1310017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
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YYWWNNN
XXXXXXXXXX 33EP64GP
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XXXXXXXXXX 33EP64GP
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XXXXXXXXXX 1310017
YYWWNNN
XXXXXXXXXXX 33EP64GP
XXXXXXXXXXX 504-I/ML e3
XXXXXXXXXXX 1310017
YYWWNNN
XXXXXXXXXXX 33EP64GP
XXXXXXXXXXX 504-I/MV e3
XXXXXXXXXXX 1310017
YYWWNNN
XXXXXXXXXXX dsPIC33EP
XXXXXXXXXXX 64GP506
XXXXXXXXXXX -I/MR e3
YYWWNNN 1310017
XXXXXXXXXX dsPIC33EP
XXXXXXXXXX 64GP506
XXXXXXXXXX -I/PT e3
YYWWNNN 1310017
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
β A1
L L1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 64
Lead Pitch e 0.50 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 – 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ 0° 3.5° 7°
Overall Width E 12.00 BSC
Overall Length D 12.00 BSC
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.09 – 0.20
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top α 11° 12° 13°
Mold Draft Angle Bottom β 11° 12° 13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085B
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Removed Parameter DC18 (VCORE) and Note 3 from the DC Temperature and
Voltage Specifications (see Table 30-4).
Updated Note 1 in the DC Characteristics: Operating Current (IDD) (see Table 30-6).
Updated Note 1 in the DC Characteristics: Idle Current (IIDLE) (see Table 30-7).
Changed the Typical values for Parameters DC60a-DC60d and updated Note 1 in the
DC Characteristics: Power-down Current (IPD) (see Table 30-8).
Updated Note 1 in the DC Characteristics: Doze Current (IDOZE) (see Table 30-9).
Updated Note 2 in the Electrical Characteristics: BOR (see Table 30-12).
Updated Parameters CM20 and CM31, and added Parameters CM44 and CM45 in
the AC/DC Characteristics: Op amp/Comparator (see Table 30-14).
Added the Op amp/Comparator Reference Voltage Settling Time Specifications (see
Table 30-15).
Added Op amp/Comparator Voltage Reference DC Specifications (see Table 30-16).
Updated Internal FRC Accuracy Parameter F20a (see Table 30-21).
Updated the Typical value and Units for Parameter CTMUI1, and added Parameters
CTMUI4, CTMUFV1, and CTMUFV2 to the CTMU Current Source Specifications (see
Table 30-55).
Section 31.0 “Packaging Updated packages by replacing references of VLAP with TLA.
Information”
“Product Identification Changed VLAP to TLA.
System”
INDEX
A Timer1 External Clock Requirements ....................... 418
Timer2/Timer4 External Clock Requirements........... 419
Absolute Maximum Ratings .............................................. 401
AC Characteristics .................................................... 413, 471 Timer3/Timer5 External Clock Requirements........... 419
10-Bit ADC Conversion Requirements ..................... 465 UARTx I/O Requirements......................................... 454
ADC
12-Bit ADC Conversion Requirements ..................... 463
ADC Module.............................................................. 459 Control Registers...................................................... 325
ADC Module (10-Bit Mode)............................... 461, 473 Helpful Tips............................................................... 324
Key Features ............................................................ 321
ADC Module (12-Bit Mode)............................... 460, 473
Capacitive Loading Requirements on Resources ................................................................ 324
Output Pins ....................................................... 413 Arithmetic Logic Unit (ALU) ................................................ 44
Assembler
DMA Module Requirements...................................... 465
ECANx I/O Requirements ......................................... 454 MPASM Assembler .................................................. 398
External Clock........................................................... 414 B
High-Speed PWMx Requirements ............................ 422
Bit-Reversed Addressing .................................................. 115
I/O Timing Requirements .......................................... 416
Example.................................................................... 116
I2Cx Bus Data Requirements (Master Mode) ........... 451
Implementation ......................................................... 115
I2Cx Bus Data Requirements (Slave Mode) ............. 453
Sequence Table (16-Entry) ...................................... 116
Input Capture x Requirements .................................. 420
Block Diagrams
Internal FRC Accuracy.............................................. 415
Data Access from Program Space
Internal LPRC Accuracy............................................ 415
Address Generation ................................. 117
Internal RC Accuracy ................................................ 472
16-Bit Timer1 Module ............................................... 203
Load Conditions ................................................ 413, 471
ADC Conversion Clock Period ................................. 323
OCx/PWMx Mode Requirements.............................. 421
ADC with Connection Options for ANx Pins
Op Amp/Comparator Voltage Reference
and Op Amps ................................................... 322
Settling Time Specifications.............................. 457
Arbiter Architecture................................................... 110
Output Compare x Requirements ............................. 421
BEMF Voltage Measurement Using ADC................... 34
PLL Clock.......................................................... 415, 471
Boost Converter Implementation ................................ 32
QEI External Clock Requirements ............................ 423
CALL Stack Frame ................................................... 111
QEI Index Pulse Requirements................................. 425
Comparator (Module 4) ............................................ 356
Quadrature Decoder Requirements.......................... 424
Connections for On-Chip Voltage Regulator ............ 384
Reset, Watchdog Timer, Oscillator Start-up Timer,
CPU Core ................................................................... 36
Power-up Timer Requirements ......................... 417
CRC Module ............................................................. 373
SPI1 Master Mode (Full-Duplex, CKE = 0, CKP = x,
CRC Shift Engine ..................................................... 374
SMP = 1) Requirements ................................... 441
CTMU Module .......................................................... 316
SPI1 Master Mode (Full-Duplex, CKE = 1, CKP = x,
Digital Filter Interconnect .......................................... 357
SMP = 1) Requirements ................................... 440
DMA Controller ......................................................... 141
SPI1 Master Mode (Half-Duplex, Transmit Only)
DMA Controller Module ............................................ 139
Requirements ................................................... 439
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
SPI1 Maximum Data/Clock Rate Summary .............. 438
and PIC24EPXXXGP/MC20X ............................ 25
SPI1 Slave Mode (Full-Duplex, CKE = 0,
ECAN Module........................................................... 288
CKP = 0, SMP = 0) Requirements .................... 449
EDS Read Address Generation................................ 105
SPI1 Slave Mode (Full-Duplex, CKE = 0,
EDS Write Address Generation................................ 106
CKP = 1, SMP = 0) Requirements .................... 447
Example of MCLR Pin Connections ........................... 30
SPI1 Slave Mode (Full-Duplex, CKE = 1,
High-Speed PWMx Architectural Overview .............. 227
CKP = 0, SMP = 0) Requirements .................... 443
High-Speed PWMx Register Interconnection ........... 228
SPI1 Slave Mode (Full-Duplex, CKE = 1,
I2Cx Module ............................................................. 274
CKP = 1, SMP = 0) Requirements .................... 445
Input Capture x ......................................................... 213
SPI2 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP
Interleaved PFC.......................................................... 34
= 1) Requirements ............................................ 429
Multiphase Synchronous Buck Converter .................. 33
SPI2 Master Mode (Full-Duplex, CKE = 1,
Multiplexing Remappable Output for RPn ................ 180
CKP = x, SMP = 1) Requirements .................... 428
Op Amp Configuration A........................................... 358
SPI2 Master Mode (Half-Duplex, Transmit Only)
Op Amp Configuration B........................................... 359
Requirements ................................................... 427
Op Amp/Comparator Voltage Reference Module..... 356
SPI2 Maximum Data/Clock Rate Summary .............. 426
Op Amp/Comparator x (Modules 1, 2, 3).................. 355
SPI2 Slave Mode (Full-Duplex, CKE = 0,
Oscillator System...................................................... 153
CKP = 0, SMP = 0) Requirements .................... 437
Output Compare x Module ....................................... 219
SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP
PLL ........................................................................... 154
= 0) Requirements ............................................ 435
Programmer’s Model .................................................. 38
SPI2 Slave Mode (Full-Duplex, CKE = 1,
PTG Module ............................................................. 338
CKP = 0, SMP = 0) Requirements .................... 431
Quadrature Encoder Interface .................................. 250
SPI2 Slave Mode (Full-Duplex, CKE = 1,
Recommended Minimum Connection ........................ 30
CKP = 1, SMP = 0) Requirements .................... 433
Remappable Input for U1RX ..................................... 176 Memory Map for PIC24EP256GP/MC20X/50X
Reset System............................................................ 123 Devices............................................................... 60
Shared Port Structure ............................................... 173 Memory Map for PIC24EP32GP/MC20X/50X
Single-Phase Synchronous Buck Converter ............... 33 Devices............................................................... 57
SPIx Module.............................................................. 266 Memory Map for PIC24EP512GP/MC20X/50X
Suggested Oscillator Circuit Placement...................... 31 Devices............................................................... 61
Type B Timer (Timer2 and Timer4)........................... 208 Memory Map for PIC24EP64GP/MC20X/50X
Type B/Type C Timer Pair (32-Bit Timer).................. 209 Devices............................................................... 58
Type C Timer (Timer3 and Timer5) .......................... 208 Near Data Space ........................................................ 51
UARTx Module.......................................................... 281 Organization, Alignment ............................................. 51
User-Programmable Blanking Function .................... 357 SFR Space ................................................................. 51
Watchdog Timer (WDT) ............................................ 385 Width .......................................................................... 51
Brown-out Reset (BOR) .................................................... 384 Data Memory
Arbitration and Bus Master Priority ........................... 110
C Data Space
C Compilers Extended X ............................................................... 109
MPLAB XC Compilers............................................... 398 Paged Memory Scheme ........................................... 105
Charge Time Measurement Unit. See CTMU. DC and AC Characteristics
Code Examples Graphs ...................................................................... 475
IC1 Connection to QEI1 Input on DC Characteristics
Pin 43 of dsPIC33EPXXXMC206 ..................... 176 BOR .......................................................................... 411
Port Write/Read ........................................................ 174 CTMU Current Source Requirements....................... 458
PWMx Write-Protected Register Doze Current (IDOZE) ........................................ 407, 469
Unlock Sequence.............................................. 226 High Temperature..................................................... 468
PWRSAV Instruction Syntax ..................................... 163 I/O Pin Input Specifications....................................... 408
Code Protection ........................................................ 379, 386 I/O Pin Output Specifications............................ 411, 470
CodeGuard Security.................................................. 379, 386 Idle Current (IIDLE) ............................................ 405, 469
Configuration Bits.............................................................. 379 Op Amp/Comparator Requirements ......................... 455
Description ................................................................ 381 Op Amp/Comparator Voltage Reference
Configuration Byte Register Map ...................................... 380 Requirements ................................................... 457
Configuring Analog and Digital Port Pins .......................... 174 Operating Current (IDD) .................................... 404, 469
CPU Operating MIPS vs. Voltage ............................. 402, 468
Addressing Modes ...................................................... 35 Power-Down Current (IPD)................................ 406, 469
Clocking System Options .......................................... 154 Program Memory ...................................................... 412
Fast RC (FRC) Oscillator .................................. 154 Temperature and Voltage ......................................... 468
FRC Oscillator with PLL.................................... 154 Temperature and Voltage Specifications.................. 403
FRC Oscillator with Postscaler ......................... 154 Thermal Operating Conditions.................................. 468
Low-Power RC (LPRC) Oscillator..................... 154 Watchdog Timer Delta Current ................................. 407
Primary (XT, HS, EC) Oscillator........................ 154 Demo/Development Boards, Evaluation and
Primary Oscillator with PLL............................... 154 Starter Kits ................................................................ 400
Control Registers ........................................................ 40 Development Support ....................................................... 397
Data Space Addressing .............................................. 35 Third-Party Tools ...................................................... 400
Instruction Set ............................................................. 35 DMA Controller
Resources ................................................................... 39 Channel to Peripheral Associations.......................... 140
CTMU Control Registers ...................................................... 141
Control Registers ...................................................... 317 DMAxCNT ........................................................ 141
Resources ................................................................. 316 DMAxCON........................................................ 141
Customer Change Notification Service ............................. 524 DMAxPAD ........................................................ 141
Customer Notification Service........................................... 524 DMAxREQ ........................................................ 141
Customer Support ............................................................. 524 DMAxSTA ......................................................... 141
DMAxSTB ......................................................... 141
D Resources ................................................................ 141
Data Address Space ........................................................... 51 Supported Peripherals .............................................. 139
Memory Map for dsPIC33EP128MC20X/50X, Doze Mode ....................................................................... 165
dsPIC33EP128GP50X Devices .......................... 54 DSP Engine ........................................................................ 44
Memory Map for dsPIC33EP256MC20X/50X,
dsPIC33EP256GP50X Devices .......................... 55 E
Memory Map for dsPIC33EP32MC20X/50X, ECAN Message Buffers
dsPIC33EP32GP50X Devices ............................ 52 Word 0 ...................................................................... 310
Memory Map for dsPIC33EP512MC20X/50X, Word 1 ...................................................................... 310
dsPIC33EP512GP50X Devices .......................... 56 Word 2 ...................................................................... 311
Memory Map for dsPIC33EP64MC20X/50X, Word 3 ...................................................................... 311
dsPIC33EP64GP50X Devices ............................ 53 Word 4 ...................................................................... 312
Memory Map for PIC24EP128GP/MC20X/50X Word 5 ...................................................................... 312
Devices ............................................................... 59 Word 6 ...................................................................... 313
Word 7 ...................................................................... 313
P Q
Packaging ......................................................................... 479 QEI
Details ....................................................................... 505 Control Registers ...................................................... 252
Marking ............................................................. 479, 481 Resources ................................................................ 251
Peripheral Module Disable (PMD)..................................... 165 Quadrature Encoder Interface (QEI)................................. 249
Peripheral Pin Select (PPS) .............................................. 175
Available Peripherals ................................................ 175 R
Available Pins ........................................................... 175 Register Maps
Control ...................................................................... 175 ADC1 .......................................................................... 84
Control Registers ...................................................... 183 CPU Core (dsPIC33EPXXXMC20X/50X,
Input Mapping ........................................................... 176 dsPIC33EPXXXGP50X Devices) ....................... 63
Output Selection for Remappable Pins ..................... 180 CPU Core (PIC24EPXXXGP/MC20X Devices) .......... 65
Pin Selection for Selectable Input Sources ............... 178 CRC ............................................................................ 88
Selectable Input Sources .......................................... 177 CTMU ......................................................................... 97
Peripheral Trigger Generator (PTG) Module..................... 337 DMAC ......................................................................... 98
PICkit 3 In-Circuit Debugger/Programmer ........................ 399 ECAN1 (When WIN (C1CTRL1) = 0 or 1)
Pinout I/O Descriptions (table) ............................................ 26 for dsPIC33EPXXXMC/GP50X Devices............. 85
Power-Saving Features..................................................... 163 ECAN1 (When WIN (C1CTRL1) = 0) for
Clock Frequency ....................................................... 163 dsPIC33EPXXXMC/GP50X Devices.................. 85
Clock Switching......................................................... 163 ECAN1 (WIN (C1CTRL1) = 1) for
Instruction-Based Modes .......................................... 163 dsPIC33EPXXXMC/GP50X Devices.................. 86
Idle .................................................................... 164 I2C1 and I2C2 ............................................................ 82
Interrupts Coincident with Power Input Capture 1 through Input Capture 4 .................... 76
Save Instructions ...................................... 164 Interrupt Controller
Sleep................................................................. 164 (dsPIC33EPXXXGP50X Devices) ...................... 69
Resources ................................................................. 165 Interrupt Controller
Program Address Space ..................................................... 45 (dsPIC33EPXXXMC20X Devices)...................... 71
Construction .............................................................. 117 Interrupt Controller
Data Access from Program Memory Using (dsPIC33EPXXXMC50X Devices)...................... 73
Table Instructions.............................................. 118 Interrupt Controller
Memory Map (dsPIC33EP128GP50X, (PIC24EPXXXGP20X Devices).......................... 66
dsPIC33EP128MC20X/50X, Interrupt Controller
PIC24EP128GP/MC20X Devices) ...................... 47 (PIC24EPXXXMC20X Devices) ......................... 67
Memory Map (dsPIC33EP256GP50X, JTAG Interface ........................................................... 97
dsPIC33EP256MC20X/50X, NVM............................................................................ 93
PIC24EP256GP/MC20X Devices) ...................... 48 Op Amp/Comparator................................................... 97
Memory Map (dsPIC33EP32GP50X, Output Compare 1 through Output Compare 4 .......... 77
dsPIC33EP32MC20X/50X, Peripheral Pin Select Input
PIC24EP32GP/MC20X Devices) ........................ 45 (dsPIC33EPXXXGP50X Devices) ...................... 91
Memory Map (dsPIC33EP512GP50X, Peripheral Pin Select Input
dsPIC33EP512MC20X/50X, (dsPIC33EPXXXMC20X Devices)...................... 92
PIC24EP512GP/MC20X Devices) ...................... 49 Peripheral Pin Select Input
Memory Map (dsPIC33EP64GP50X, (dsPIC33EPXXXMC50X Devices)...................... 91
dsPIC33EP64MC20X/50X, Peripheral Pin Select Input
PIC24EP64GP/MC20X Devices) ........................ 46 (PIC24EPXXXGP20X Devices).......................... 90
Table Read High Instructions Peripheral Pin Select Input
TBLRDH............................................................ 118 (PIC24EPXXXMC20X Devices) ......................... 90
Table Read Low Instructions (TBLRDL) ................... 118 Peripheral Pin Select Output
Program Memory (dsPIC33EPXXXGP/MC202/502,
Organization................................................................ 50 PIC24EPXXXGP/MC202 Devices)..................... 88
Reset Vector ............................................................... 50 Peripheral Pin Select Output
Programmable CRC Generator......................................... 373 (dsPIC33EPXXXGP/MC203/503,
Control Registers ...................................................... 375 PIC24EPXXXGP/MC203 Devices)..................... 88
Overview ................................................................... 374 Peripheral Pin Select Output
Resources ................................................................. 374 (dsPIC33EPXXXGP/MC204/504,
Programmer’s Model........................................................... 37 PIC24EPXXXGP/MC204 Devices)..................... 89
Register Descriptions .................................................. 37 Peripheral Pin Select Output
PTG (dsPIC33EPXXXGP/MC206/506,
Control Registers ...................................................... 340 PIC24EPXXGP/MC206 Devices) ....................... 89
Introduction ............................................................... 337 PMD (dsPIC33EPXXXGP50X Devices) ..................... 95
Output Descriptions .................................................. 353 PMD (dsPIC33EPXXXMC20X Devices)..................... 96
Resources ................................................................. 339 PMD (dsPIC33EPXXXMC50X Devices)..................... 95
Step Commands and Format .................................... 350 PMD (PIC24EPXXXGP20X Devices) ......................... 94
TyCON (Timer3 and Timer5 Control)........................ 211 Input Capture x (ICx) ................................................ 420
UxMODE (UARTx Mode).......................................... 283 OCx/PWMx............................................................... 421
UxSTA (UARTx Status and Control)......................... 285 Output Compare x (OCx).......................................... 421
VEL1CNT (Velocity Counter 1) ................................. 259 QEA/QEB Input ........................................................ 424
Resets ............................................................................... 123 QEI Module Index Pulse........................................... 425
Brown-out Reset (BOR) ............................................ 123 SPI1 Master Mode (Full-Duplex, CKE = 0,
Configuration Mismatch Reset (CM)......................... 123 CKP = x, SMP = 1) ........................................... 441
Illegal Condition Reset (IOPUWR)............................ 123 SPI1 Master Mode (Full-Duplex, CKE = 1,
Illegal Opcode ................................................... 123 CKP = x, SMP = 1) ........................................... 440
Security ............................................................. 123 SPI1 Master Mode (Half-Duplex, Transmit Only,
Uninitialized W Register.................................... 123 CKE = 0)........................................................... 438
Master Clear (MCLR) Pin Reset ............................... 123 SPI1 Master Mode (Half-Duplex, Transmit Only,
Power-on Reset (POR) ............................................. 123 CKE = 1)........................................................... 439
RESET Instruction (SWR)......................................... 123 SPI1 Slave Mode (Full-Duplex, CKE = 0,
Resources................................................................. 124 CKP = 0, SMP = 0) ........................................... 448
Trap Conflict Reset (TRAPR).................................... 123 SPI1 Slave Mode (Full-Duplex, CKE = 0,
Watchdog Timer Time-out Reset (WDTO)................ 123 CKP = 1, SMP = 0) ........................................... 446
Resources Required for Digital PFC ............................. 32, 34 SPI1 Slave Mode (Full-Duplex, CKE = 1,
Revision History ................................................................ 507 CKP = 0, SMP = 0) ........................................... 442
SPI1 Slave Mode (Full-Duplex, CKE = 1,
S CKP = 1, SMP = 0) ........................................... 444
Serial Peripheral Interface (SPI) ....................................... 265 SPI2 Master Mode (Full-Duplex, CKE = 0,
Software Stack Pointer (SSP) ........................................... 111 CKP = x, SMP = 1) ........................................... 429
Special Features of the CPU ............................................ 379 SPI2 Master Mode (Full-Duplex, CKE = 1,
SPI CKP = x, SMP = 1) ........................................... 428
Control Registers ...................................................... 268 SPI2 Master Mode (Half-Duplex, Transmit Only,
Helpful Tips ............................................................... 267 CKE = 0)........................................................... 426
Resources................................................................. 267 SPI2 Master Mode (Half-Duplex, Transmit Only,
CKE = 1)........................................................... 427
T SPI2 Slave Mode (Full-Duplex, CKE = 0,
Temperature and Voltage Specifications CKP = 0, SMP = 0) ........................................... 436
AC ..................................................................... 413, 471 SPI2 Slave Mode (Full-Duplex, CKE = 0,
Thermal Operating Conditions .......................................... 402 CKP = 1, SMP = 0) ........................................... 434
Thermal Packaging Characteristics .................................. 402 SPI2 Slave Mode (Full-Duplex, CKE = 1,
Timer1 ............................................................................... 203 CKP = 0, SMP = 0) ........................................... 430
Control Register ........................................................ 205 SPI2 Slave Mode (Full-Duplex, CKE = 1,
Resources................................................................. 204 CKP = 1, SMP = 0) ........................................... 432
Timer2/3 and Timer4/5...................................................... 207 Timer1-Timer5 External Clock .................................. 418
Control Registers ...................................................... 210 TimerQ (QEI Module) External Clock ....................... 423
Resources................................................................. 209 UARTx I/O ................................................................ 454
Timing Diagrams
10-Bit ADC Conversion (CHPS<1:0> = 01, U
SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000, Universal Asynchronous Receiver
SSRCG = 0)...................................................... 464 Transmitter (UART) .................................................. 281
10-Bit ADC Conversion (CHPS<1:0> = 01, Control Registers...................................................... 283
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, Helpful Tips............................................................... 282
SSRCG = 0, SAMC<4:0> = 00010) .................. 464 Resources ................................................................ 282
12-Bit ADC Conversion (ASAM = 0, User ID Words .................................................................. 384
SSRC<2:0> = 000, SSRCG = 0) ...................... 462
BOR and Master Clear Reset ................................... 416 V
ECANx I/O ................................................................ 454 Voltage Regulator (On-Chip) ............................................ 384
External Clock........................................................... 414
High-Speed PWMx Fault .......................................... 422 W
High-Speed PWMx Module....................................... 422 Watchdog Timer (WDT)............................................ 379, 385
I/O Characteristics .................................................... 416 Programming Considerations ................................... 385
I2Cx Bus Data (Master Mode) .................................. 450 WWW Address ................................................................. 524
I2Cx Bus Data (Slave Mode) .................................... 452 WWW, On-Line Support ..................................................... 23
I2Cx Bus Start/Stop Bits (Master Mode) ................... 450
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 452
NOTES:
NOTES:
NOTES:
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Authorized Distributor
Microchip:
PIC24EP64GP202-E/SS PIC24EP64GP202-I/SS PIC24EP64MC202T-I/SS PIC24EP64GP202T-I/SS
PIC24EP64MC202-E/SS PIC24EP64MC202-I/SS PIC24EP64GP202-E/MM PIC24EP64GP202-E/SO
PIC24EP64GP202-E/SP PIC24EP64GP202-I/MM PIC24EP64GP202-I/SO PIC24EP64GP202-I/SP
PIC24EP64GP202T-I/MM PIC24EP64GP202T-I/SO PIC24EP64GP203-E/TL PIC24EP64GP203-I/TL
PIC24EP64GP203T-I/TL PIC24EP64GP204-E/ML PIC24EP64GP204-E/PT PIC24EP64GP204-E/TL
PIC24EP64GP204-I/ML PIC24EP64GP204-I/PT PIC24EP64GP204-I/TL PIC24EP64GP204T-I/ML
PIC24EP64GP204T-I/PT PIC24EP64GP204T-I/TL PIC24EP64GP206-E/MR PIC24EP64GP206-E/PT
PIC24EP64GP206-I/MR PIC24EP64GP206-I/PT PIC24EP64GP206T-I/MR PIC24EP64GP206T-I/PT
PIC24EP64MC202-E/MM PIC24EP64MC202-E/SO PIC24EP64MC202-E/SP PIC24EP64MC202-I/MM
PIC24EP64MC202-I/SO PIC24EP64MC202-I/SP PIC24EP64MC202T-I/MM PIC24EP64MC202T-I/SO
PIC24EP64MC203-E/TL PIC24EP64MC203-I/TL PIC24EP64MC203T-I/TL PIC24EP64MC204-E/ML
PIC24EP64MC204-E/PT PIC24EP64MC204-I/ML PIC24EP64MC204-I/PT PIC24EP64MC204-I/TL
PIC24EP64MC204T-I/ML PIC24EP64MC204T-I/PT PIC24EP64MC204T-I/TL PIC24EP64MC206-E/MR
PIC24EP64MC206-E/PT PIC24EP64MC206-I/MR PIC24EP64MC206-I/PT PIC24EP64MC206T-I/MR
PIC24EP64MC206T-I/PT PIC24EP64MC204-E/TL PIC24EP64GP202T-E/MM PIC24EP64GP202T-E/SO
PIC24EP64GP203T-E/TL PIC24EP64GP204T-E/ML PIC24EP64GP204T-E/PT PIC24EP64GP204T-E/TL
PIC24EP64GP206T-E/MR PIC24EP64GP206T-E/PT PIC24EP64MC202T-E/MM PIC24EP64MC202T-E/SO
PIC24EP64MC203T-E/TL PIC24EP64MC204T-E/ML PIC24EP64MC204T-E/PT PIC24EP64MC204T-E/TL
PIC24EP64MC206T-E/MR PIC24EP64MC206T-E/PT PIC24EP256GP206-I/PT PIC24EP256GP202-I/SS
PIC24EP256GP202-I/SP PIC24EP256MC202-I/SO PIC24EP256GP204-I/PT PIC24EP256MC204-I/TL
PIC24EP256MC202-I/MM PIC24EP256GP206-I/MR PIC24EP256GP202-I/MM PIC24EP256GP204-I/ML
PIC24EP256GP202-I/SO PIC24EP256MC206-I/PT PIC24EP256MC202-I/SS PIC24EP256MC202-I/SP
PIC24EP256MC204-I/PT PIC24EP256MC206-I/MR PIC24EP256GP204-I/TL PIC24EP256MC204-I/ML
PIC24EP32GP203-I/TL PIC24EP32MC204-E/PT PIC24EP128MC204T-I/PT PIC24EP128GP202T-I/MM
PIC24EP128GP206-I/MR PIC24EP128GP204T-I/PT PIC24EP32MC202-I/MM PIC24EP32GP202T-I/SO