Digital System Design

KEC302

Unit-2
Combinational Circuits

Deepak Sigroha
Electronics Engineering Department
Rajkiya Engineering College Sonbhadra
deepak.sigroha@recsonbhadra.ac.in
+91-9478856526
 Outline
Looping
• Combinational Circuits
o Analysis & Design
• Arithmetic Circuits
o Adder, Subtractor, & Multiplier
• Non-arithmetic Circuits
o Magnitude Comparator, Code Convertors & Parity Generator/Checker
• Encoder & Decoder
• Multiplexer & De-Multiplexer
• ALU
• Barrel Shifter
 Combinational Circuit
(Decoders & Encoders)
 Decoders
 Discrete quantities of information are represented in digital systems by binary codes. A binary
code of n bits is capable of representing up to distinct elements of coded information.

 A decoder is a logic circuit that accepts a set of inputs which represents a binary number and
activates the only output that corresponds to the input number.

 A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines. If the n -bit coded information has unused combinations, the
decoder may have fewer than 2n outputs (i.e. .

 In other words, a decoder circuit looks at its inputs, determines which binary number is present
there, and activates the specific output which corresponds to that number; all other outputs remain
inactive.
Unit 2 – Combinational Circuits 4
 Decoders
 The general diagram shown in Figure with n inputs and m outputs. Because each of the n inputs
can be 0 or 1, there are possible input combinations or codes. For each of these input
combinations, only one of the m outputs will be active (HIGH); all the other outputs are
inactive (LOW).
 Many decoders are designed to produce active-LOW outputs, where only the selected output is
LOW while all others are HIGH. This situation is indicated by the presence of small circles on
the output lines in the decoder diagram.

I0 O0
I1 O1
I2 O2
n inputs
.
. Decoder
.
.
m outputs m=2n
. .
In-2 Om-2
In-1 Om-1

Unit 2 – Combinational Circuits 5

 Decoders
 The decoders presented here are called n-to-m line decoders, where . Their purpose is to
generate the 2n (or fewer) minterms of n input variables.
 Some decoders do not utilize all of the 2n possible input codes but only certain ones.
 For example, a BCD-to-decimal decoder has a four-bit input code and ten output lines that correspond to the
ten BCD code groups 0000 through 1001.
 Decoders of this type are often designed so that if any of one of the unused codes are applied to the input,
none of the outputs will be activated.
 The name decoder is also used in conjunction with other code converters, such as a BCD-to-
seven-segment decoder.

Unit 2 – Combinational Circuits 6

 Decoders
 Decoders are used to identify or convert a particular code for example:
1. Binary to Octal (3-8 line decoders)
2. Binary to Hexadecimal (4-16 line decoders)
3. BCD to decimal (4-10 line decoders)
4. BCD to 7-segment display decoders
 Decoders are widely used in memory system of computers.

Unit 2 – Combinational Circuits 7

 3-Line-to-8-Line (Binary to Octal) Decoder
 The three inputs are decoded into eight outputs, each representing one of the minterms of the eight
variables.
 The operation of the decoder is clarified in the truth table:
Inputs Outputs • For each possible
input combination,
there are seven
A B C outputs that are equal
to 0 and only one that
0 0 0 1 0 0 0 0 0 0 0 is equal to 1.
• The output whose
0 0 1 0 1 0 0 0 0 0 0
value is equal to 1
0 1 0 0 0 1 0 0 0 0 0 represents the
minterm equivalent of
0 1 1 0 0 0 1 0 0 0 0 the binary number
1 0 0 0 0 0 0 1 0 0 0 currently available in
the input lines.
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Unit 2 – Combinational Circuits 8
A A′ B B′ C C ’ 3-Line-to-8-Line Decoder

D 7=ABC

D 6= ABC′
• 3 to 8 line decoder can be
D 5= AB ′ C implemented using AND
gates to achieve active-
D 4= AB ′ C ′ HIGH output.
• For active-LOW outputs,
NAND gates are used.
D 3=A ′ BC

D 2= A ′ BC ′

D 1= A ′ B ′ C

D 0= A ′ B ′ C ′
Unit 2 – Combinational Circuits 9
 3-Line-to-8-Line (Binary to Octal) Decoder
 The three inputs are decoded into eight outputs, each representing one of the minterms of the
three input variables.

 The three inverters provide the complement of the inputs, and each one of the eight AND gates
generates one of the minterms.

 Also called 1-of-8 decoder only 1 of the 8 outputs is activated at one time.

 It uses all AND gates, and therefore, the outputs are active-HIGH. For active-LOW outputs,
NAND gates are used.

Unit 2 – Combinational Circuits 10

 3-Line-to-8-Line (Binary to Octal) Decoder
 A particular application of this decoder is binary-to-octal conversion. The input variables
represent a binary number, and the outputs represent the eight digits of a number in the octal
number system.

 However, a three-to-eight-line decoder can be used for decoding any three-bit code to provide
eight outputs, one for each element of the code.

Unit 2 – Combinational Circuits 11

 Active Low Decoders & Enable inputs
 Some decoders are constructed with NAND gates. Since a NAND gate produces the AND
operation with an inverted output, it becomes more economical to generate the decoder
minterms in their complemented form.

 Furthermore, decoders include one or more enable inputs to control the circuit operation.

 For example, in the 3-line to 8-line decoder, if a common ENABLE line is connected to the
fourth input of each gate.

 A particular output as determined by the input code will go HIGH only when the ENABLE line
is held HIGH. When the ENABLE is held LOW, however, all the outputs will be forced to the
LOW state regardless of the levels at the and inputs.

Unit 2 – Combinational Circuits 12

 3-Line to 8-Line Decoder with Active High Enable
Inputs Outputs

E A B C

0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1

Unit 2 – Combinational Circuits 13

A A′ B B′ C C ’ E 3-Line-to-8-Line Decoder with Active High Enable

D 7=E ABC

D 6=E ABC ′

D 5= E AB ′ C

D 4= E AB ′ C ′

D 3=E A′ BC

D 2= E A ′ BC ′

D 1=E A ′ B′ C

D 0=E A′ B′ C ′
Unit 2 – Combinational Circuits 14
 2-Line-to-4-Line Decoder with NAND Gates & Enable Input
 A two-to-four-line decoder with an enable input constructed with NAND gates is shown in Fig. The circuit
operates with complemented outputs and a complement enable input.

Inputs Outputs
From Truth Table
1 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 0 1 1 1 0

Unit 2 – Combinational Circuits 15

 Working of a 2-Line-to-4-Line Decoder with NAND Gates & Enable Input
 The decoder is enabled when E is equal to 0 (i.e., active-low enable).
 Only one output can be equal to 0 at any given time; all other outputs are equal to 1.

 The output whose value is equal to 0 represents the minterm selected by inputs A and B.

 The circuit is disabled when E is equal to 1, regardless of the values of the other two inputs.
 When the circuit is disabled, none of the outputs are equal to 0 and none of the minterms are selected.

Unit 2 – Combinational Circuits 16

 Decoders
 In general, a decoder may operate with complemented or uncomplemented outputs.
 The enable input may be activated with a 0 or with a 1 signal.
 Some decoders have two or more enable inputs that must satisfy a given logic condition in
order to enable the circuit.

Unit 2 – Combinational Circuits 17

 Decoders
 A decoder with enable input can function as a demultiplexer.
 A circuit that receives information from a single line and directs it to one of possible output lines.
The selection of a specific output is controlled by the bit combination of n selection lines.
 The 2-line-to-4-line decoder can function as a one-to-four-line demultiplexer when E is taken
as a data input line and A and B are taken as the selection inputs.
 The single input variable E has a path to all four outputs, but the input information is directed to
only one of the output lines, as specified by the binary combination of the two selection lines A and
B.
 Because decoder and demultiplexer operations are obtained from the same circuit, a decoder with
an enable input is referred to as a decoder – demultiplexer.

Unit 2 – Combinational Circuits 18

The 74ALS138 decoder (Multiple Enable)

ENABLE
inputs

Unit 2 – Combinational Circuits 19

 BCD-to-Decimal Decoder
 The BCD-to-Decimal Decoder is also called a 4-line to 10-line or 4-to-10 decoder or 1-of-10 decoder.

7442
BCD-to-decimal
decoder.

This decoder does not have

an enable input.

Unit 2 – Combinational Circuits 20

 Design: BCD-to-Decimal Decoder
 Design a BCD-to-decimal decoder using the unused combinations of the BCD code as don’t-
care conditions.

Inputs Outputs
A B C D
0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 0 0 0 0 0 0 1
Unit 2 – Combinational Circuits 21
 Design: BCD-to-Decimal Decoder

AB
00 01 11 10
CD
0 4 12 8
00
1 5 13 9
01
3 7 15 11
11
2 6 14 10
10

Unit 2 – Combinational Circuits 22

 The 4-bit Decoder
 In order to decode all possible combinations of four bits, sixteen decoding gates are required ().
 This type of decoder is commonly called either a 4-line-to-16-line decoder because there are four inputs and sixteen outputs or
a 1-of-16 decoder because for any given code on the inputs, one of the sixteen outputs is activated.

Unit 2 – Combinational Circuits 23

 The 4-bit Decoder
 If an active-LOW output is required for each decoded number, the entire decoder can be
implemented with NAND gates and inverters.
 In order to decode each of the sixteen binary codes, sixteen NAND gates are required (AND
gates can be used to produce active-HIGH outputs).

The BIN/DEC label indicates that a binary input makes the

corresponding decimal output active. The input labels and represent
the binary weights of the input bits

Unit 2 – Combinational Circuits 24

The 4-bit Decoder (74HC154)

Unit 2 – Combinational Circuits 25

 Implementation of Decoder using Decoder
 Decoders with enable inputs can be connected together to form a larger decoder circuit. Figure shows the
arrangement for using two 74138s, 3-to-8 decoders, to obtain a 4-to-16 decoder.

Unit 2 – Combinational Circuits 26

 Implementation of Decoder using Decoder

 The most significant input bit is connected through an inverter to on the upper decoder (for
through ) and directly to E on the lower decoder (for through ).

 When is LOW, the upper decoder is enabled and the lower decoder is disabled. The bottom
decoder outputs all 0s, and top 8 outputs generate minterms.

 When A3 is HIGH, the lower decoder is enabled and the upper decoder is disabled. The bottom
decoder outputs generate minterms 1000 to 1111 while the outputs of the top decoder are all 0s.

 In general, enable inputs are a convenient feature for interconnecting two or more standard
components for the purpose of expanding the component into a similar function with more
inputs and outputs.

Unit 2 – Combinational Circuits 27

 Decoder Design
 Implementation of Higher Order decoder using lower Order decoder

Given Decoder To be Implemented Required no. of decoders

(2 4) lines (4 16) lines 1 + 4 =5

(2 4) lines (3 8) lines 1 NOT gate + 2

(4 16) lines (8 256) lines 1 + 16 = 17

Unit 2 – Combinational Circuits 28

 Decoder Design
 Construct a 4-to-16-line decoder with five 2-to-4-line decoders with enable.

Unit 2 – Combinational Circuits 29

 Decoder Design
 Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to-4-line decoder. Use block
diagrams for the components.

Unit 2 – Combinational Circuits 30

 Decoder Design
 Design of a 10 1k Decoder Using Chips of 8 256 Decoder and Additional Logic.

Unit 2 – Combinational Circuits 31

 Decoder Design
 Draw the logic diagram of a 2-to-4-line decoder (Active High) using NOR gates only. Include an enable input
(active high).

0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

Unit 2 – Combinational Circuits 32

 Boolean Function Implementation using Decoder
 A decoder provides the 2n minterms of n input variables. Each asserted output of the decoder is
associated with a unique pattern of input bits.

 Since any Boolean function can be expressed in sum-of-minterms form, a decoder that generates the
minterms of the function, together with an external OR gate that forms their logical sum, provides a
hardware implementation of the function. In this way, any combinational circuit with n inputs and m
outputs can be implemented with an n-to-2n-line decoder and m OR gate.

 The procedure for implementing a combinational circuit by means of a decoder and OR gates requires
that the Boolean function for the circuit be expressed as a sum of minterms.
 A decoder is then chosen that generates all the minterms of the input variables. The inputs to each OR gate
are selected from the decoder outputs according to the list of minterms of each function.

Unit 2 – Combinational Circuits 33

 Full Adder Implementation
 From the truth table of the full adder ,we obtain the functions for the combinational circuit in sum-of-minterms form:

 Since there are three inputs and a total of eight minterms, we need a three-to-eight-line decoder. The implementation is shown
in Figure.

 The decoder generates the eight minterms for , , and .

 The OR gate for output S forms the logical sum of minterms , and .
 The OR gate for output C forms the logical sum of minterms and .
Unit 2 – Combinational Circuits 34
 Boolean Function Implementation using Decoder

 If NAND gates are used for the decoder, then the external gates must be NAND gates instead of OR
gates.
 This is because a two-level NAND gate circuit implements a sum-of-minterms function and is
equivalent to a two-level AND–OR circuit.

 A function with a long list of minterms requires an OR gate with a large number of inputs.
 A function having a list of k minterms can be expressed in its complemented form with minterms.

 If the number of minterms in the function is greater than , then can be expressed with fewer minterms.

 In such a case, it is advantageous to use a NOR gate to sum the minterms of . The output of the NOR gate
complements this sum and generates the normal output F .

Unit 2 – Combinational Circuits 35

 Boolean Function Implementation (1)
 A combinational circuit is specified by the following three Boolean functions:

Implement the circuit with a decoder constructed with NAND gates and NAND or AND gates connected to the
decoder outputs. Use a block diagram for the decoder. Minimize the number of inputs in the external gates.

Unit 2 – Combinational Circuits 36

 Boolean Function Implementation (2)
 Using a decoder and external gates, design the combinational circuit defined by the following three Boolean
functions:

 Solution

Unit 2 – Combinational Circuits 37

 Boolean Function Implementation (3)
 Implement the following multiple output combinational logic circuit using a 4-line to 16-line
decoder.



Unit 2 – Combinational Circuits 38

 BCD-to-Seven Segment Decoder/Driver
 Most digital equipment has some means for displaying information in a form that can be understood
readily by the user or operator. This information is often numerical data but can also be alphanumeric
(numbers and letters).
 The 7-segment display is a common way to display decimal or hexadecimal characters. One common
arrangement uses light emitting diodes (LEDs) for each segment.

Diodes allow current to flow in one direction,

but block flow in the other direction.

When the LED anode is more positive than the cathode by approximately 2 V, the LED

will light up.

Unit 2 – Combinational Circuits 39

 BCD-to-Seven Segment Decoder/Driver

By controlling current through each LED, some segments are turned on & emit light, while others are turned off, which generates the desired character

pattern.

Unit 2 – Combinational Circuits 40

 Common-Anode vs Common-Cathode LED Displays
 Two types of LED display—the common-anode and the common-cathode types.

 In the common-anode type, a low voltage applied to an LED cathode allows current to flow
through the diode, which causes it to emit light.
 In the common-cathode type, a high voltage applied to an LED anode causes the current to flow
and produces the resulting light emission.
Unit 2 – Combinational Circuits 41
 BCD-to-Seven Segment Decoder/Driver

 A BCD-to-7-segment decoder/driver is used to take a four-bit BCD input and provide the
outputs that will pass current through the appropriate segments to display the decimal digit.

 The logic for this decoder is more complicated than the logic of decoders that we have looked
at previously because each output is activated for more than one combination of inputs.
 For example, the segment must be activated for any of the digits and , which means whenever any
of the codes or occurs.

Unit 2 – Combinational Circuits 42

 BCD-to-Seven Segment Decoder/Driver
 An 8-4-2-1 BCD-to-seven segment decoder is a logic circuit as shown in Figure (a).

Unit 2 – Combinational Circuits 43

 BCD-to-Seven Segment Decoder/Driver (Common Cathode)
 The function table for such a decoder is shown in Figure. Since a 1 (HIGH) on any output line activates that line,
we assume that the display is of the common-cathode type.

Unit 2 – Combinational Circuits 44

 BCD-to-Seven Segment Decoder/Driver (Common Cathode)
 The K-map used to simplify the logic expression for driving segment is shown in Figure (c). Entries 10–15
are don’t cares as usual.

 Since LEDs require considerable power, decoders often contain output drivers capable of supplying sufficient
power
Unit 2 – Combinational Circuits 45
 BCD-to-Seven Segment Decoder/Driver
 After using K-map, the simplified minimum Boolean expression are given by

The output of display has AND-OR logic, so it can be implemented by “24” NAND gates

Unit 2 – Combinational Circuits 46

 BCD-to-7 Segment Decoder/Driver (Common Anode)

The 7446/47 activates

specific segment
patterns
in response to
input codes

The 7446/47 decoder/drivers are designed to activate specific segments even for non-BCD input
codes (greater than 1001). Figure shows the activated segment patterns for all possible input
codes from 0000 to 1111. Note that an input code of 1111 (15) will blank out all the segments.

Unit 2 – Combinational Circuits 47

 Encoders
 An encoder is a digital circuit that performs the inverse operation of a decoder.

 It has (or fewer) input lines and N-output lines. Out of input lines only one is activated at a
given time and produces an output code, depending upon which input is activated.

 Encoding is a process of converting familiar numbers or symbols into coded format.

Unit 2 – Combinational Circuits 48

 Encoders
 Figure shows the block diagram of an encoder with M inputs and N outputs. Here the inputs are
active-High, which means normally LOW.

where,

Unit 2 – Combinational Circuits 49

 Encoders
 Encoders are used to convert other codes to binary such as
1. Octal to Binary Encoder (8 x 3 lines)
2. Decimal to BCD Encoder (10 x 4 lines)
3. Hexadecimal to Binary Encoder (16 x 4 lines)

Unit 2 – Combinational Circuits 50

 Octal to Binary Encoder
 An octal-to-binary encoder (8-line to 3-line encoder) accepts 8 input lines and produces a 3-bit
output code corresponding to the activated input. Figure shows the truth table an octal-to-binary
encoder with active HIGH inputs.
 It is assumed that only one input has a value 1 at any given time.

Unit 2 – Combinational Circuits 51

 Octal to Binary Encoder
 The Encoder can be Implemented with OR gates whose inputs are directly determined from the truth
table.
 Output is equal to when the input octal digit is or .
 Output is 1 for octal digits or .
 output is 1 for digits 4, 5, 6, or 7.
 These conditions can be expressed by the following Boolean output functions:

The Encoder can be implemented with

three OR gates

Unit 2 – Combinational Circuits 52

 Decimal-to-BCD Encoder
 It has 10 inputs—one for each decimal digit, and 4 outputs corresponding to the BCD code as shown in
Figure (a). The BCD code is listed in truth table Figure(b)

Unit 2 – Combinational Circuits 53

 Decimal-to-BCD Encoder
 The relationship between each BCD bit and the decimal digits are:

There is no explicit input for a decimal

0. The BCD output is
0000 when the decimal inputs 1– 9 are
all 0.

Unit 2 – Combinational Circuits 54

 Limitation of Encoder
 Octal to Binary encoder defined in table will operate correctly, provided that one and only one decimal input is
HIGH at any given time.
 In some practical systems, two or more decimal inputs may inadvertently become HIGH at the same time. For
example, a person operating a keyboard might press a second key before releasing the first. Let us say he presses
key 3 before releasing key 6. In such a case the output will be 7 10 (0111) instead of being or .

• To resolve this ambiguity, encoder circuits must establish an input priority to ensure that only one input is encoded.
• If we establish a higher priority for inputs with higher subscript numbers, and if both D 3 and D6 are 1 at the same time,
the output will be 110 because D6 has higher priority than D3.

Unit 2 – Combinational Circuits 55

 Limitation of Encoder
 Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated
when all the inputs are 0; but this output is the same as when is equal to 1.

The discrepancy can be resolved by providing one more output to indicate

whether at least one input is equal to 1.

 In some practical applications, priority encoders may have several inputs that are routinely
HIGH at the same time, and the principal function of the encoder in those cases is to select the
input with the highest priority. This function is called arbitration. A common example is found
in computer systems, where there are numerous input devices and several of which may attempt
to supply data to the computer at the same time.
 A priority encoder is used to enable that input device which has the highest priority among
those competing for access to the computer at the same time.

Unit 2 – Combinational Circuits 56

 4-Input Priority Encoder
 A priority encoder is an encoder circuit that includes the priority function. The operation of the
priority encoder is such that if two or more inputs are equal to 1 at the same time, the input
having the highest priority will take precedence.

Unit 2 – Combinational Circuits 57

 4-Input Priority Encoder
 A priority encoder is a logic circuit that responds to just one input in accordance with some
priority system, among all those that may be simultaneously HIGH.
 The most common priority system is based on the relative magnitudes of the inputs; whichever
decimal input is the largest, is the one that is encoded.
 For example, if both decimal 3 and decimal 4 are activated simultaneously, then a priority encoder
would encode decimal 4.

Inputs Outputs A=∑ ( 1 , 2 ,3 ,5 ,6 ,7 , 9 ,10 ,11 , 13 ,14 , 15 ) +d (0)

m
0 0 0 0 0 B=∑ ( 1 ,3 , 4 , 5 , 7 , 9 , 11 ,12 , 13 , 15 ) +d (0)
1 0 0 0 0 0 1 m

1 0 0 0 1 1 V =∑ (1 , 2 , 3 , 4 ,5 ,6 ,7 , 8 , 9 ,10 ,11 , 12 ,13 , 14 ,15)

m
1 0 1 0 1
1 1 1 1
Unit 2 – Combinational Circuits 58
 Priority Encoder
 In addition to the two outputs A and B, the circuit has a third output designated by V.
 This is a valid bit indicator that is set to 1 when one or more inputs are equal to 1.

 If all inputs are 0, there is no valid input and V is equal to 0. The other two outputs are not inspected when V
equals 0 and are specified as don’t-care conditions.

 Note that whereas in output columns represent don’t-care conditions, the in the input columns
are useful for representing a truth table in condensed form. Instead of listing all 16 minterms of
four variables, the truth table uses an to represent either 1 or 0. For example, represents the two
minterms and .

Unit 2 – Combinational Circuits 59

 Priority Encoder
A=∑ ( 1 , 2 ,3 ,5 ,6 ,7 , 9 ,10 ,11 , 13 ,14 , 15 ) +d (0) B=∑ ( 1 ,3 , 4 , 5 , 7 , 9 , 11 ,12 , 13 , 15 ) +d (0)
m m

𝐷0 𝐷1 𝐷0 𝐷1
00 01 11 10 00 01 11 10
𝐷2 𝐷3 0 4 12 8 𝐷2 𝐷3 0 4 12 8
00 X 00 X 1 1
1 5 13 9 1 5 13 9
01 1 1 1 1 01 1 1 1 1
3 7 15 11 3 7 15 11
11 1 1 1 1 11 1
1 1 1
2 6 14 10 2 6 14 10
10 1 1 1 1 10

A=D 3+ D 2 B= D 3 + D ′2 D 1
Unit 2 – Combinational Circuits 60
 Priority Encoder
V =∑ (1 , 2 , 3 , 4 ,5 ,6 ,7 , 8 , 9 ,10 ,11 , 12 ,13 , 14 ,15)
m

D0 D100 01 11 10 D3 B= D3 + D ′2 D1
D2 D3 0 4 12 8 D2
00 0 1 1 1 D1
1 5 13 9
01 1 1 1 1
A=D 3+D 2
3 7 15 11
11 1 1 1 1
D0
2 6 14 10
10 1 1 1 1 V = D 3+D 2+D 1+D 0

V = D 3+D 2+ D 1+ D 0
Unit 2 – Combinational Circuits 61
 References
1. T. L. Floyd, “Digital Fundamental”, 11th Ed., USA : Prentice-Hall.
2. R.J. Tocci, N. S. Widmer and G. L. Moss “Digital Systems: Principles and Applications”,
11th Ed., USA : Prentice-Hall.,
3. M. Morris Mano, M. D. Ciletti, “Digital Design” 6th Ed., USA : Prentice-Hall.
4. A. Anand Kumar, “Fundamentals of Digital Circuits” 4th Ed., PHI.

Unit 2 – Combinational Circuits 62

Thank You