THE 8284 CLOCK GENERATOR

BY JOSHUA KAREGI AND MAX OMINDI

CONTENT
• Introduction
• Function
• Pin Diagram
• Logic Diagram
• Interfacing with 8086
 INTRODUCTION
• The 8284 clock generator is an IC developed by Intel to provide
clock frequency, READY and RESET signals to the 8086 and 8088
microprocessors.
• The READY and RESET signals provided by the 8284 are
synchronized with the clock signal.
• The 8284 contains a clock generator capable of providing a third the
frequency of the input clock with sources selectable between an
external crystal and clock input.
• 5 or 8MHz with the 8284A
• 10MHz with the 8284A-1
THE 8284A CLOCK GENERATOR
• The commercial version of the
chip is available as:
• 18-pin Dual In-Line (DIL) package
• 20-pin Plastic-Leaded chip carrier
(PLCC)
PIN DIAGRAMS

DIL PIN CONFIGURATION PLCC PIN CONFIGURATION

WHY DO WE NEED THE 8284A CLOCK GENERATOR?
• It generates a stable clock to
the processor and peripherals
CLK GEN.
• It provides READY
synchronization
• It provides RESET READY
synchronization

RESET
LOGIC DIAGRAM
OPERATION OF THE CLOCK SECTION
• The section generates 3 output signals:
• Oscillator output (OSC)
• Clock (CLK)
• Peripheral clock (PCLK)
• It has 5 inputs:
• X1
• X2
• Frequency/Crystal Selection pin (F/C’)
• External Frequency Input (EFI)
• Clock synchronization (CSYNC)
OPERATION OF THE CLOCK SECTION
• The crystal oscillator generates square wave signals at the same
frequency as the crystal. The square wave is applied to AND gate and an
inverter that provides an OSC output signal. The OSC signal is used as an
EFI input to other 8284 clock generators.
• The AND gate applies the oscillator output to the divide by 3 counter
when F/C’ is low. When F/C’ is high, EFI is passed through the counter.
The output of the divide by three generates the timing for the READY
and RESET signals in their respective sections.
• In a system with more than one 8284’s such that the timers receive the
inputs from the EFI, CSYNC is used to synchronize the clocks. Otherwise,
it is grounded.
OPERATION OF THE CLOCK SECTION
• The peripheral clock (PCLK) frequency signal is used to provide
required clock for supporting peripheral chips. It is acquired by
dividing clock frequency by 2.
OPERATION OF THE RESET SECTION
• Consists of: Schmitt trigger, D Flipflop
• The section applies a RESET when the microprocessor is powered to
ensure its starts operating in a known state.
• An RC circuit provides a low to the RES when power is first applied to
the system. The RE input becomes a 1 when the capacitor charges
towards +5V through the resistor.
• Correct RESET timing requires input becomes high 4 clocks after
power is applied and held high for 50 microseconds. The FF ensures
RESET goes high after 4 clocks and RC ensures it remains high for at
least 50 microseconds.
OPERATION OF THE READY SECTION
• The section has 5 inputs and 1 output:
• RDY1 and RDY2 that provide signals from devices present on the bus showing
the availability or reception of the data.
• AEN1 and AEN2 (Address Enable) that qualify the bus ready signals.
• ASYNC gives the information regarding the synchronization provided to the
inputs.
• The READY output produces the READY signals.
• This gives information regarding whether the processor is ready for
operation or not. If the READY signal is low, the microprocessor
introduces a wait state between T3 and T4 states of the machine cycle.
OPERATION OF THE READY SECTION
• The section has 5 inputs and 1 output:
• RDY1 and RDY2 that provide signals from devices present on the bus showing
the availability or reception of the data.
• AEN1 and AEN2 (Address Enable) that qualify the bus ready signals.
• ASYNC gives the information regarding the synchronization provided to the
inputs.
• The READY output produces the READY signals.
• This gives information regarding whether the processor is ready for
operation or not. If the READY signal is low, the microprocessor
introduces a wait state between T3 and T4 states of the machine cycle.
PIN CONFIGURATION DIAGRAM
PIN CONFIGURATION OF CLOCK GENERATOR
• RES(RESET IN)
It is an active low input signal used in generating RESET IN signal for
8284.
It is normally connected to the power supply of the microprocessor
At the instance the microprocessor ‘wake up’, a low signal is
generated on the RES pin. The 8284 activates the RESET pin which in
turn resets the microprocessor and the processor boots from this
state. A type of booting referred to as cold booting.
PIN CONFIGURATION OF CLOCK GENERATOR
• X1 & X2 (CRYSTAL IN)
They are the two inputs used in attaching a crystal oscillator in order
to generate the desired frequency.
The crystal frequency should be three times the desired frequency of
the microprocessor.
The maximum crystal oscillations for the 8284A is 24Mhz and 30Mhz
for 8284A-1.
PIN CONFIGURATION OF CLOCK GENERATOR
• F/C ̅(FREQUENCY/ CRYSTAL SELECTION PIN)
In the 8284, the pin is used in selecting whether a clock signal is
generated internally using the help of an internal crystal oscillator or
an external clock.
When low, clock signal is generated by 8284 and if high clock signal is
generated by an external source and is applied through EFI.
PIN CONFIGURATION OF CLOCK GENERATOR
• EFI(EXTERNAL FREQUENCY INPUT)
The pin is used in the case where F/C ̅ is high through which an
external clock frequency is applied.
When using microprocessors the pin is not used because
microprocessors generate an internal clock frequency.
PIN CONFIGURATION OF CLOCK GENERATOR
• CSYNC(CLOCK SYNCHRONIZATION)
The pin is an active high input.
The pin is used in synchronizing multiple 8284 clock generators used in a
system.
It remains low when a single 8284 is used with the 8086 microprocessor.
PIN CONFIGURATION OF CLOCK GENERATOR
• and
These are input signals to the 8284 chip.
(READY) is an active high pin. It is provided by devices on the data bus showing an
availability and reception of data.
(address enable) is an active low pin. It also qualifies the bus ready signals().
READY is used in the synchronization of the microprocessor with slower peripherals.
PIN CONFIGURATION OF CLOCK GENERATOR
• and
These are additional pins for the READY and address enable signals
and have similar functions to and
The additional RDY and AEN are used in multiprocessing.
PIN CONFIGURATION OF CLOCK GENERATOR
• RESET
It is an active high output signal connected to RESET signal of
8088/8086 microprocessor.
PIN CONFIGURATION OF CLOCK GENERATOR
• OSC(oscillator)
It an output signal that has the same clock frequency as that
produced by the crystal oscillator.
PIN CONFIGURATION OF CLOCK GENERATOR
• CLK(CLOCK)
This output pin provides an output signal with a third of the crystal oscillator frequency as the
clock frequency.
The output is connected to the clock input of the microprocessor.
It also provides the clock frequency to all devices in the system to be synchronized with the
microprocessor.
PIN CONFIGURATION OF CLOCK GENERATOR
• PCLK(peripheral clock)
The output signal from this pin provides the clock signal to peripherals like the 8254.
The frequency is half of the CLK(a sixth of the crystal) with a 50% duty cycle.
PIN CONFIGURATION OF CLOCK GENERATOR
• READY
It is an output pin that connects the ready signal of the clock
generator to the processor.
PIN CONFIGURATION OF CLOCK GENERATOR

It gives information towards synchronization provided to inputs. This

different synchronizations create two modes of operation.
For an active low signal, it shows that two stage synchronization is provided.
For an active high signal, single stage synchronization is provided.
PIN CONFIGURATION OF CLOCK GENERATOR
• VCC
The supply input of +5V is provided at this pin.
• GND
The pin is used for ground connection.
INTERFACING THE 8284 CLOCK GENERAATOR WITH
THE 8086 MICROPROCESSOR
 INTERFACING THE 8284 CLOCK GENERAATOR WITH
THE 8086 MICROPROCESSOR

• CLK of the 8284 is connected to the clock input of the 8086 in order to generate
clock signals for the microprocessor and its system.
• RESET output pin of the 8284 is connected to the RESET pin of the 8086 to
ensure it starts executing from a known state.
• READY output pin is connected to the READY pin of the 8086 to ensure. It is used
to indicate to the microprocessor that the memory or I/O devices are ready to
send or receive data. When the Ready is high the microprocessor waits for the
data to be READY.
• GND of both 8086and 8084 are connected together to provide a similar
reference point.
• VCC of both the 8086and 8084 are connected to the same power source.
REFERENCES
• Mathur, S. (2011). Microprocessor 8086: Architecture, Programming
and Interfacing, PHI Learning Private Limited, 2011.
• Y, R. (2021, January 9). 8284 clock generator - logic circuit, working
and pin description of 8284 clock generator. Electronics Desk.
Retrieved April 19, 2023, from https://electronicsdesk.com/8284-
clock-generator.html
• Eeeguide. (2022, June 13). Clock generator 8284a - Block diagram,
operations and pin diagram. Retrieved from
https://www.eeeguide.com/clock-generator-8284a/
THE END