Microcontroller & Applications (EC511)

(Part-II)

by: Dr. Mitesh Limachia

 Computer System

• CPU
- Determines operations that computer can perform
- Process data by performing digital operations on it.
- Controls flow of information among various components of
computer.
 Memory
0
1

N-1

• The memory is used to store data and binary instructions.

• It contains several memory locations.
• Each location can store data or instruction.
• CPU reads (fetches) the instructions from the memory and
performs operations (indicated by instructions) on data.
 Contd.
• Memory module consists of N memory locations of equal length. Each
memory location is assigned unique address (0 to A N-1).

• Address inputs\lines (A0 to AN-1) used to identify one memory location

out of N locations.

• Number of address lines determines capacity of memory chip

10 address lines indicates 210 = 1024 memory locations.

• Data lines transfers data to or from memory devices.

• Control signals used to enable memory device and control operation
like read or write.

Code/Program Memory (ROM) holds instructions

Data Memory (RAM) holds data
 Contd.
• 128 bytes RAM
• Address lines? Data lines? Control lines?

• 64KB of RAM
• Address lines? Data lines? Control lines?

• 4KB of ROM
• Address lines? Data lines? Control lines?
 I/O Unit
• I/O device (Peripherals):
The device that gives information to computer - input device.
Keyboard, mouse, A/D converters are all input devices.
The device that receives information from computer called
output devices. LED, LCD, Printer..

• I/O port:
The hardware in a computer that allows information transfer
between external world and computer.

• I/O interfacing circuits:

The circuits that are used to interconnect I/O devices with a
CPU or I/O ports are called I/O interfacing circuits. For
example, buffers, latches etc.
 Contd.
• Address bus
- It is group of wires (Address lines) used by CPU to identify
specific memory location within a memory chip or to identify I/O
devices.
- Each memory location or I/O device have unique address.

- Addresses are always generated by CPU, address bus is always

unidirectional.
- Size of address bus determines maximum number of memory
locations that can be addressed uniquely.

- i.e. 16-bit address bus can address 216 = 65536 (64KB) bytes of
memory.
 Contd.
• Control bus
- Read (RD), write (WR) and CS’ (chip select) are most common
control signals.
- It is used to enable memory and I/O devices to perform read or
write operations.
- It regulates all activities on the bus and direction of the data transfer.

• Data bus
- It transfers data or instructions between CPU and memory or I/O
devices.
- It is bidirectional because data can be transferred in both directions
i.e. from CPU to memory (or output devices) or from memory or
input devices to CPU.
- i.e. 8-bit, 16-bit, 32-bit,, 64-bit….
- Wider data bus supports higher rate of data transfer.
 Microprocessor vs. Microcontroller
• Microprocessor is a central processing unit (CPU) built into a
single semiconductor chip. The structure of microprocessor is
same as CPU.

• Microprocessors are general purpose and programmable

devices suitable for applications like word processing,
computing, gaming etc.

• The Microprocessor is not sufficient to make functional

system. Other peripherals including memory and I/O devices
are required to connect externally.
Often referred as processor, CPU or Microprocessor Unit (MPU).
Contd.
 Microcontroller
• Microcontroller is an small computer built into a single
semiconductor chip. Micro + Controller.

• Includes all major component on single chip.

• Limited data and code memory, various on-chip peripherals like

timers/counters, serial port, A/D converters, D/A converters etc,
interface controllers, and general purpose I/O ports.

• MCU based products are generally physically smaller, more

reliable and cheaper then MPU based products like personal
computers.
Contd.
 Contd.
• More suitable for applications where cost, size and power
requirements are important factors.

• Microcontrollers are designed to perform a specific control

oriented operations.

• It includes all resources within a chip to satisfy need of an

small or average application or project.
 Comparison
MPU MCU
Complete functional CPU ---- x86 Circuitry of CPU, limited On-chip
family Pentium i3,i5, i7 Memory, and peripherals devices
Designed to interact with humans and Designed to interact with machines
more flexible to design and less flexible
Usually bulkier, costly, consume Cheaper and consume less power
more power
x86 family, Pentium. I3, i5,i7… 8051 family (MCS51), PIC from
Microchip…..
 Choosing a MCU
• Computational Requirements : Enough speed and processing capability
to handle all operations of an application in a real time. i.e. Airbags
used in recent cars must operate in real time. Higher operational speeds
than required will unnecessarily increase power consumption.

• Hardware Resources requirement: It should have sufficient program

and data memory to store and execute an application program. It
should have maximum on-chip peripherals to make product as compact
and reliable as possible. Enough I/O pins

• Low power consumption: Suitable for portable and battery powered

products.

• Software and Hardware Development Tools and family:

Complier/assembler, debuggers emulators or IDE.
• Cost: Cheapest MCU that satisfy applications need.
 Applications of MCU
• Household appliances: Microwave oven, washing machine,
Office and commercial appliances: Fax machine, photocopier.
• Telecommunication: Mobile phones, Telephones, phone
answering machines,.
• Entertainment and gaming: Televisions, Music players.
• Automotive industry: Fuel injection, ABS Industrial
automation and manufacturing: Motor control systems, data
acquisition and supervisory systems, industrial robots.
• Electronic measurement instruments: Digital Multimeters,
logic analyzers
• Biomedical systems: ECG recorder, blood cell analyzers,
Military weapons, guidance and positioning System.
History of the 8051 Microcontroller Family
 Features of 8051 (MCS-51)
Various features of 8051 microcontroller are given as follows.
• 8-bit CPU with Boolean processing capability
• 8-bit internal data bus (D0 to D7), 16-bit address bus (A0-A15).
• 4KB of on-chip Program memory
• 128 bytes of on-chip RAM memory
• 64 Kbytes of external program and data address space
• 32 I/O pins arranged as four 8-bit ports (P0 - P3)
• Two 16-bit timer/counters : T0 and T1
• Two external and three internal vectored interrupts
• One full duplex serial Port- UART
• Hardware multiply and divide operations
Block Diagram of 8051 MCU
Time Specific Activates

I/O Devices Serial Communication

Comparison of H/W resources of MCS51
 8051 Variants & Enhancement
Variants -- 8051 compatible (code compatible) MCUS.
1000 of variants with more than 20 semiconductor companies.
• Amount of on-chip memory: ROM and RAM
• Type of memory: SRAM, DRAM, ROM, E2PROM, Flash
• On-chip peripherals and oscillator sources
• Operating speed
• Operating voltage
• Power consumption
• Number of pins
• Implementation technology

• Atmel Corporation, Dallas Semiconductors and Philips (NXP),

Microchip….
Pinout Diagram of 8051
8051 Pin Diagram
 Contd.
• 8051 MCUs are 40-pin chips available in different packages.

• Four 8-bit I/O ports (P0 to P3).

• Each port pin except P1 can be used for two different functions.

• The function of the pin is determined by an instruction used to

access that pin or physical connection to it.

• VCC = 5V with respect to GND

 Oscillator Pins
• 8051 has on-chip oscillator (partial circuit), generates clock
pulses to synchronize internal operations.

• External Resonant circuit (Quartz crystal with capacitors) is

connected with oscillator to make complete oscillator.

• We can observe the frequency on the XTAL2 pin.

 Contd.
• The clock frequency of the microcontroller chip is
determined by crystal frequency.

• The maximum speed of MCU refers to the maximum crystal

frequency that can be applied to XTAL pins.

• 12 MHz chip should be connected with a maximum 12 MHz

crystal.
 External Clock Source Connection
• Possible to use clock signal from external
oscillator.
• XTAL2 is unconnected.
 Machine Cycle

• In 8051 one machine cycle consists of 12 clock pulses.

• It is the time required to completely execute a simple

instruction (or partially execute a complex instruction).

• The number of machine cycles is fixed for a given instruction

but varies from one instruction to another
 Contd.
• In 8051 inst. may require one, two or four machine cycles.

• MOV A, #15H --- 1 Machine Cycle

• MOV 10H, #15H --- 2 Machine Cycle

• One machine cycle contains 6 states.

• State is time required to perform subdivision of basic

operation.
 Opcode Fetching
03 .org 0000H
80 MOV R7,#10h; -- 7F 10
MOV R3,A; -- FB
75
MOV R3,#30h; -- 7B 30
03 MOV A,R2; -- EA
Address BUs
80 MOV 80h,#03h; -- 75 80 03
75 end
30

CPU 7B
Data BUs
FB MOV A, R3

0x0001 10
MOV R7, #10H
0x0000 7F

Code Memory
 Case Study
• Connected crystal of 12 MHz. Period of 1 M/C = 1 µs.

• Assume that One program consists of all simple instructions.

Executed in 1 M/C.

• How many such instructions can be executed by 8051 in 1 second?

• If clock frequency is increased to 24 MHz.

• How many such instructions can be executed by 8051 in 1 second?

• MIPS
 RESET Pin of 8051

• RST （ pin 9 ）：
– input pin and active high （ normally low ） .
• High pulse is applied to this pin, microcontroller
terminates all activities and contents of all registers
will be lost.
• RESET signal must be high for 2 machine cycles.

(1) Power-On Reset

RST remains high for some time depending on RC time
constant.

(2) External reset – Press push-button switch

Power-On RESET
RESET Value of Some 8051 Registers:

Register Reset Value (H)

PC 0000H

ACC 00H

B 00H

PSW 00H

SP 0007

DPTR 0000

P0- P3 FFH

R0-R7 00H 
Content of on-chip RAMs are non deterministic.
ALE (Address Latch Enable)
Multiplexed Address
& Data bus

ALE 74LS373
G
AD0
P0.0 A0
D
P0.7 A7 Demultiplexed
AD7 Address & Data
bus
8051
D0
D7

P2.0 A8
P2.7 A15

8051
 Contd.
• P0 provides lower 8-bit address A0-A7, and data D0- D7.
• P0 ->AD0-AD7 (Address/Data time Multiplexing)-A0 to A7,
D0-D7
• P2 provides upper 8-bit address A8-15.

• Multiplexed address and data lines must be separated to access

memory.
• ALE– Output pin for demultiplexing Address lines with Data
lines

• ALE=1, 8051 uses P0 for address path

– Latch addresses
• ALE=0, 8051 uses P0 for data path
 RD’
ALE G 74LS373
AD0 A0
P0.0 D
P0.7 A7
AD7
D0
CPU
D7

P2.0 A8
P2.7 A15
8051
Code/Program Memory

MOV R0, #23H 74H, 23H - 1 M/C

0000H - 74H
0001H - 23H
To execute such simple instructions in one machine cycle, ALE
pulses are generated twice per every machine cycle.
ALE pulse is generated at constant rate of 1/6 oscillator frequency.
• Memory Interfacing
 Need of Memory Interfacing
• Available on-chip RAM and ROM are not sufficient, we need
to add an external memory to the system.

• When the programs are developed in a high-level language,

the program size may exceed the available on-chip program
memory, we need to add ROM externally.

• When the 8051 microcontroller is used in a data acquisition

system, internal RAM will not be sufficient and external
RAM is added.
 Contd.
Decoding Logic

A0-A15 A0-A13
Address Decoder using Logic Gates

Using simple logic gates

‘1’ A12
‘1’ A13
‘0’ A14
‘0’ A15
 Contd.
• A15 A14 A13 A12 A11----A0
0 0 1 1 0-------0 = 3000H
0 0 1 1 1-------1 = 3FFFH
‘1’
‘1’
‘1’
‘0’

• A15 A14 A13 A12 A11----A0

0 1 1 1 0-------0 = 7000H
0 1 1 1 1-------1 = 7FFFH
Address Decoder using Decoder Chip

74LS138

‘0’
‘0’
‘1’
‘0’
 Contd.
(a) The address range for Y4 is calculated as follows.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
The above shows that the range for Y4 is 4000H to 4FFFH.

(b) The address range for Y2 is 2000H to 2FFFH.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1

(c) The address range for Y7 is 7000H to 7FFFH.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
 0
0
1

Chip 1 is enabled when the address is between

2000H to 3FFFH
(A15A14A13 = 001).
Chip 2 address range 4000H to 5FFFH
(A15A14A13 = 010).
Chip 3 for address range 6000H to 7FFFH
(A15A14A13 = 011).
 Chip-1 Addressing Range
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000H
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH
External RAM Interfacing

0xBFFF

0x8000
 Contd.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BFFFH
Addressing range: 8000H to BFFFH

• To bring data into the CPU from externally RA M address 9000H.

MOV DPTR,#9000H (1001 0000 0000 0000)
MOVX A,@DPTR

• To transfer the data from CPU `to externally RA M address 9000H.

MOV DPTR,#9000H
MOVX @DPTR,A
 Contd.
• The 16K Byte chip requires 14 address lines (A13–A0).

• Chip 1 selected when A15=0 and A14=1

• The address range for Chip 1 is 4000H to 7FFFH
0100 0000 0000 0000 =4000H
0111 1111 1111 1111 = 7FFFH

• Chip 2 selected when A15=1 and A14=1

• The address range for for the second chip, it is C000H to
FFFFH.
 Ext. DATA ROM Interfacing
• Data memory as RAM only.
• Store data into ROM, for example, look-up tables are
examples of data and are required to be stored in ROM
because they have to remain permanently in the memory.

• Table of 7-segment codes for BCD numbers,

• ASCII code for various keys.
• Any group of pre-calculated values like square of given no,
etc.
1FFFH

0000H
 Contd.
• Addressing range: 0000H to 1FFFH
• Only RD’ Signal used
• To bring data into the CPU from address 1000H
(memory read operation).

MOV A, #00H
MOV DPTR, #1000H (0001 0000 0000 0000)
MOVC A, @A+DPTR
Interface 4Kbyte of ROM (2732-EPROM) as data
memory starting at the memory location 0000H.
Interface two 4K bytes of Data ROM with 8051. The starting
address for the first chip will be from 0000H and the second chip
will be from 1000H..

0000H 1000H
 Contd.
• Since each chip capacity is 4K bytes, the address range for the
first will be from 0000H to 0FFFH and for the second chip, it
will be 1000H to 1FFFH.
 Program/Code Memory Interfacing (EA’
Pin)

EA’ pin – i/p pin, External Access

Many members of 8051 family have on-chip ROM.
Used by 8051 for selection of on-chip or off-chip ROM.
GND, fetch all program code from off-chip ROM
VCC, fetch all program code fetches from on-chip ROM

if program address outside the range of on-chip memory will

automatically access external ROM.
 PSEN’ (Output) Pin

• ROM– Program, Data

• Program Strobe Enable (active low signal)
• Op-code fetch from external ROM will
activate the signal.
• Used as a read strobe (or output enable) to
external Program memory.
• Connected to OE’ pin of external ROM
DATA ROM and Program ROM

Prog.
Data
Code

MOVC A, @A+DPTR Opcode Fetching

 Contd.
• For Program ROM, PSEN’ used to activate OE’.

• For Data ROM, RD’ used to activate OE’.

• PSEN’ also be connected with CE’ of the memory chip if

only one ROM chip is present in a system.

• Note that A13 to A15 are left unconnected to Program

ROM.

• Each memory location have multiple addresses.

 Single ROM - Data & Program Memory

• Some part of ROM may be used to store the program

code while the other part may be used to store the
data.
• PSEN’ is used to access the program code and
RD’ is used to read the data space.
• So OE’ of ROM must be activated for both code and
data access.
8000H to BFFFH 0000H to 3FFFH
 Problem Statement
Interface one 16k*8 program ROM and four 8k*8 data RAM
with single 8051 chip using following addressing range.
• Program ROM – starts from an address 0000H.
• First data RAM – starts from an address 2000H.
• Second data RAM – starts from an address 4000H.
• Third data RAM – starts from an address 8000H.
• Fourth data RAM – starts from an address C000H

Y1,Y2,Y4,Y6
• Input/Output Ports
 Ports
• 32 I/O pins configured as four 8-bit parallel ports

• P0,P1,P2,P3.

• Used as an input or as an output port to connect I/O

devices

• Ports are Software Controlled.

• I/O pins can be accessed directly by an instruction.

8051 Pin Diagram
 Port 1 Structure

“Read latch” Vcc

TB2
Load(L1)
P1.0

Internal CPU D Q P1.X

bus P1.X pin

:Write to Clk Q M1
latch”

TB1
“Read pin”

Circuit is only for one pin. There will be 8 such circuits, one for each pin of the port.
 Hardware Structure of I/O Pin
• Each pin of I/O ports -Internally connected to CPU bus

– Data from internal data bus written to D latch

Write to latch ＝ 1
- Q output of latch copied to internal data bus
Read latch ＝ 1

– 2 Tri-state buffer ：
• TB1: controlled by “Read pin”
– Read pin ＝ 1 ： read the data present at the pin
• TB2: controlled by “Read latch”
– Read latch ＝ 1 ： read value from internal latch
– A transistor M1 – Output Driver
 Writing “1” to Output Pin P1.X

Read latch Vcc Output pin is

TB2 Connected to
Load(L1)
Vcc
Write a ‘1’
Internal CPU D Q
1 P1.X
bus P1.X pin

Clk Q 0 M1
Output “1”
Write to latch

TB1
Read pin

MOV P1, #0FFH

 Writing “0” to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2. output pin is
Write a 0 to the pin ground
Internal CPU D Q
0 P1.X
bus P1.X pin

Clk Q 1 M1
Output 0
Write to latch

TB1
Read pin

MOV P1, #00H

 Configuring Port as Input
• Port pin is configured as input pin
by writing ‘1’ on it.
• MOV P1, #0FFH; configure as input port
• MOV A, P1; read values from port pins
 Reading “High” at Input Pin

Read latch Vcc

TB2
Write a 1 , MOV P1,#0FFH Load(L1)

Internal CPU bus D Q

1 “1” P1.X pin

P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1
MOV P1, #0FFH
MOV A, P1
 Reading “Low” at Input Pin

Read latch Vcc

TB2
1. write a 1 to the pin Load(L1)
MOV P1,#0FFH
1 “0” P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 MOV P1, #0FFH
MOV A, P1
 Port Protection
• All the port pins are configured as an input after reset because the
8051 writes 1s to all port latches after reset.

• Never write “0” to the port that was configured as input port
because it may damage the port.

• Writing ‘0’ grounds the input pin. This will short VCC connected
to a pin, and a high current will flow through M1 and may damage
it.

• To avoid it, use current limiting resistor between input signal and
port pin.
 Port-0 Structure

Port 0  I/O port or AD0-AD7

CONTROL acting as a selection line.
CONTROL =1”, gate of T1 connected to ADDR/DATA bits.
CONTROL =“0”, Q’ to gate of FET connected to ports
 Contd.
• Pull-up resistors are required to be connected
externally to Port 0 pins to provide VCC path (write
“1” on port pin).
 MOV A, #55H
Back: MOV P0, A
Delay routine; Identify the
CPL A; functionality
SJMP Back
Assume that eight LEDs are connected to Port 1. Write a
program to sequentially glow all LEDs one by one (P0.0 to
P0.7) with delay between each.

ORG 0000H
MOV A, #01H // only 1 LED is on at a time
BACK: MOV P0, A // send to Port 1
Delay routine// delay between each glowing LED
RLA // rotate to glow next LED
SJMP BACK // repeat the pattern forever
END
 Read-Modify-Write Feature

“Read latch” Vcc

TB2
Load(L1)

‘1’ ‘1’ P1.X

Internal CPU D Q
bus P1.X ‘1’ pin

:Write to Clk Q M1
latch”

TB1
“Read pin”

Read-modify-write instructions are directed to the latch rather

than the pin is to avoid a possible misinterpretation of the voltage
level at the pin.
 Contd.
• When ‘1’ is written to the port latch, the transistor will be
turned on, resulting in the base voltage of 0.7 volts.

• If the microcontroller reads the port pin, it will read the base
voltage of the transistor and interpret it as logic 0 (0.7 is
treated as logic level ‘0’) even though port latch contains ‘1’.

• Therefore, reading the latch rather than the pin will read
correct value of ‘1’. The same problem will occur whenever
the port pin is heavily loaded.
 Contd.
• Read-modify-write instructions read a port will read the
latch and rather than pin.

• Instructions read a latch value, possibly change it, and

then rewrite it to the latch. These are called “read-
modify-write” instructions.

• When the destination operand is a port, or a Port bit,

these instructions read the latch rather than the pin:
 Example
• ANL (logicalAND, e.g., ANL P1, A)
• ORL (logicalOR, e.g., ORL P2, A)
• XRL (logical EXOR, e.g., XRL P3, A)
• CPL (complement bit, e.g., CPL P3.0)
• INC (increment, e.g., INC P2)
• DEC (decrement, e.g., DEC P2)
 Example
MOV P1,#55H MOV P1,#55H
Again : XRL P1,#0FFH MOV A, P1
delay routine Again: XRL A, #0FFH
SJMP Again MOV P1, A
delay routine
SJMP Again