Vivado Basic Tutorial
Vivado Basic Tutorial
Vivado Basic Tutorial
Dr. Vasudeva
ECE Dpt.
MREC (A), Hyderabad
e-mail: [email protected]
August 2023
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1. Starting Vivado
Open Vivado via the start menu or desktop shortcut
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2. The Start Page
This is the screen Vivado's start-up screen. The different options available are described
below using the image as a guide.
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Create New Project: This button will open the New Project wizard. This wizard steps
the user through creating a new project.
Open Project: This button will open a file browser. Navigate to the desired Xilinx
Project (.xpr) file and click Open to open the project in Vivado.
Open Example Project: This will guide the user through creating a new project based
on an example project. These projects will not work on all devices. Many Digilent
example projects are instead released on Github, and linked to through the target
FPGA System Board's Resource Center, which can be found through the list of List of
Digilent FPGA System Boards.
Open Hardware Manager: This will open the Hardware Manager without an
associated project. If connecting to and programming a device is all that the user
wants to do, then this is the button to use.
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3. Creating a New Project
3.1
From the start page, click the Create New Project button to start the New Project Wizard.
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3.2
The text in this dialog describes the steps that will be taken to create a project. Click Next to continue.
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3.3
The first page is used to set the name of the project. Vivado will use this name when generating its folder
structure. Do NOT use spaces in the project name or location path. This will cause problems with Vivado.
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3.4
Now that the project has a name and a place to save its files we need to select the type of project we will be
creating. Select RTL Project and make sure to check the Do not specify sources at this time box. Source files
will be added and created after the project has been created.
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3.5. The target device choosing (xc7100csg324-1)
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3.6
The next section gives a summary of the options selected throughout the wizard. Verify that the
information looks correct and click Finish
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Getting Started with Vivado_V
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4. The Flow Navigator
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5. The Project Manager
This tool is where most development will occur and is the initial tool open after creating a new project.
The Project Manager consists of four panes, Sources, Properties, Results, and the Workspace, described
below.
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Sources Pane
The Sources pane contains the project hierarchy and is used for opening up files. The folder structure is
organized such that the HDL files are kept under the Design Sources folder, constraints are kept under the
Constraints folder, and simulation files are kept under the Simulation Sources folder. Files can be opened
in the Workspace by double-clicking on the corresponding entry in the Sources pane. Sources can also be
added by either right clicking the folder to add the file to and selecting Add Sources or by clicking the Add
Sources button ( ).
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The Properties pane allows for viewing and editing of file properties. When a file is
selected in the Sources pane its properties are shown in here. This pane can usually
be ignored.
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TCL Console Tab
The Tcl Console is a tool that allows running commands directly without the use of
the main graphical user interface.
Messages Tab
The Messages tab displays warnings (critical or otherwise) and errors that may occur
during the process of building a project. If anything goes wrong while designing and
building a project, check the Messages first. Solutions for many errors and warning can
be found by right clicking on the message and selecting “Search for Answer Record”.
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Reports Tab
The Reports tool is useful for quickly jumping to any one of the many reports that
Vivado generates on a design. These include power, timing, and utilization reports just
to name a few.
Log Tab
The Log displays the output from the latest Synthesis, Implementation, and
Simulation runs. Digging into this is usually not necessary as the reports and
messages view store the information in the log in a more readable format.
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Workspace Pane
The most important pane in the Project Manager is the Workspace. The Workspace is
where reports are opened for viewing and source files are opened for editing. Initially the
Workspace displays the Project Summary which show some basic information from some
of the reports.
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6. Creating a VHDL Source File
6.1 In the Project Manager section of the Flow Navigator, click the button again. Select Add or create design
sources then click Next.
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8. Synthesis, Implementation, and Bitstream Generation
In order to create a file that can be used to program the target board, each stage of the
“compilation pipeline” needs to be run.
This starts with Synthesis. Synthesis turns HDL files into a transistor level description
based on timing and I/O constraints. To run Synthesis click either in the toolbar or in
the Flow Navigator. The output of Synthesis is then passed to Implementation.
Implementation has several steps. The steps that are always run are Opt Design
(Optimize the design to fit on the target FPGA), Place Design (Lay out the design in the
target FPGA fabric), and Route Design (Route signals through the fabric). To run
Implementation click either in the toolbar or in the Flow Navigator. This output is then
passed on to the Bitstream Generator.
The Bitstream Generator generates the final outputs needed for programming the
FPGA. To run Bitstream Generation click either in the toolbar or in the Flow Navigator.
With no settings changed, the generator will create a '.bit' file, which can be used to
program the design onto the target FPGA system board.
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Bitstream Generation Completed Pop-Up
Once the bitstream has been generated, a pop-up will appear asking what Vivado
should do next. The options in this pop-up allow the user to do several different
things:
Open Implemented Design takes the user to a tool where they can view how the
project will be programmed into the fabric of the target FPGA chip.
View Reports takes the user to a list of many different reports and statistics about
how the project was laid out, including information about how fast the design can
potentially be run, and how much of the FPGA will be used to run the design.
Open Hardware Manager takes the user to a tool that can be used to program the
generated bitstream onto a connected FPGA board.
Generate Memory Configuration File lets the user create a file that can be used to
program a non-volatile memory part on an FPGA system board, so that the FPGA
can be automatically programmed each time that the board is powered on.
For the purposes of this guide, select Open Hardware Manager, then click OK.
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