+

William Stallings
Computer Organization
and Architecture
9th Edition
+
Chapter 10
Computer Arithmetic
+
Arithmetic & Logic Unit (ALU)

 Part of the computer that actually performs arithmetic and logical

operations on data

 All of the other elements of the computer system are there mainly to
bring data into the ALU for it to process and then to take the results
back out

 Based on the use of simple digital logic devices that can store binary
digits and perform simple Boolean logic operations
ALU Inputs and Outputs
+
Integer Representation

 In the binary number system arbitrary numbers can be represented

with:
 The digits zero and one
 The minus sign (for negative numbers)
 The period, or radix point (for numbers with a fractional component)

 For purposes of computer storage and processing we do not have the

benefit of special symbols for the minus sign and radix point

 Only binary digits (0,1) may be used to represent numbers

Sign-Magnitude Representation
+
Twos Complement Representation
 Uses the most significant bit as a sign bit
 Differs from sign-magnitude representation in the way that the other
bits are interpreted

Table 10.1 Characteristics of Twos Complement Representation and Arithmetic

 Table 10.2
Alternative Representations for 4-Bit Integers
+
Range Extension

 Range of numbers that can be expressed is extended by increasing the

bit length

 In sign-magnitude notation this is accomplished by moving the sign

bit to the new leftmost position and fill in with zeros

 This procedure will not work for twos complement negative integers
 Rule is to move the sign bit to the new leftmost position and fill in with
copies of the sign bit
 For positive numbers, fill in with zeros, and for negative numbers, fill in
with ones
 This is called sign extension
Fixed-Point Representation
+
Negation

 Twos complement operation

 Take the Boolean complement of each bit of the integer (including the sign
bit)
 Treating the result as an unsigned binary integer, add 1

+18 = 00010010 (twos complement)

bitwise complement = 11101101
+ 1
11101110 = -18

 The negative of the negative of that number is itself:

-18 = 11101110 (twos complement)
bitwise complement = 00010001
+ 1
00010010 = +18
+
Negation Special Case 1

0 = 00000000 (twos complement)

Bitwise complement = 11111111

Add 1 to LSB + 1

Result 100000000

Overflow is ignored, so:

-0=0
+
Negation Special Case 2

-128 = 10000000 (twos complement)

Bitwise complement = 01111111

Add 1 to LSB + 1

Result 10000000

So:

-(-128) = -128 X

Monitor MSB (sign bit)

It should change during negation

Addition
 Overflow

OVERFLOW RULE:

If two numbers are added,

Rule
and they are both positive or
both negative, then overflow
+ occurs if and only if the result
has the opposite sign.
 Subtraction

SUBTRACTION RULE:

To subtract one number

(subtrahend) from another Rule

(minuend), take the twos

+
complement (negation) of the
subtrahend and add it
to the minuend.
Subtraction
Geometric Depiction of Twos
Complement Integers
Hardware for Addition and Subtraction
Multiplication
+

Hardware
Implementation of
Unsigned Binary
Multiplication
+

Flowchart for
Unsigned Binary
Multiplication
+
Twos Complement Multiplication
+
Comparison
 Booth’s

Algorithm

+
Example of Booth’s Algorithm
Examples Using Booth’s Algorithm
Division
+

Flowchart for
Unsigned
Binary Division
+
Example of Restoring Twos
Complement Division
+
Floating-Point Representation
Principles
 With a fixed-point notation it is possible to represent a range of
positive and negative integers centered on or near 0

 By assuming a fixed binary or radix point, this format allows the

representation of numbers with a fractional component as well

 Limitations:
 Very large numbers cannot be represented nor can very small fractions
 The fractional part of the quotient in a division of two large numbers could
be lost
Typical 32-Bit Floating-Point Format
+
Floating-Point
Significand
 The final portion of the word

 Any floating-point number can be expressed in many ways

The following are equivalent, where the significand is expressed

in binary form:
0.110 * 25
110 * 22
0.0110 * 26

 Normal number
 The most significant digit of the significand is nonzero
+
Expressible Numbers
+
Density of Floating-Point Numbers
IEEE Standard 754
+
IEEE 754-2008

 Defines the following different types of floating-point formats:

 Arithmetic format
 All the mandatory operations defined by the standard are supported by the
format. The format may be used to represent floating-point operands or
results for the operations described in the standard.

 Basic format
 This format covers five floating-point representations, three binary and two
decimal, whose encodings are specified by the standard, and which can be
used for arithmetic. At least one of the basic formats is implemented in any
conforming implementation.

 Interchange format
 A fully specified, fixed-length binary encoding that allows data interchange
between different platforms and that can be used for storage.
IEEE 754
Formats
 Table 10.3

IEEE 754

Format
Parameters

* not including implied bit and not including sign bit

+
Additional Formats

Extended Precision Formats Extendable Precision Format

 Provide additional bits in the exponent  Precision and range are defined
(extended range) and in the significand under user control
(extended precision)
 May be used for intermediate
 Lessens the chance of a final result that has
calculations but the standard
been contaminated by excessive roundoff
error
places no constraint or format or
length
 Lessens the chance of an intermediate
overflow aborting a computation whose final
result would have been representable in a
basic format

 Affords some of the benefits of a larger basic

format without incurring the time penalty
usually associated with higher precision
 Table 10.4
IEEE Formats

Table 10.4 IEEE Formats

Interpretation of
IEEE 754
Floating-Point (a) binary 32 format
Numbers

Table 10.5 Interpretation of IEEE 754 Floating-Point Numbers (page 1 of 3)

Interpretation of
IEEE 754
Floating-Point (b) binary 64 format
Numbers

Table 10.5 Interpretation of IEEE 754 Floating-Point Numbers (page 2 of 3)

Interpretation of
IEEE 754
Floating-Point (c) binary 128 format
Numbers

Table 10.5 Interpretation of IEEE 754 Floating-Point Numbers (page 3 of 3)

Table 10.6  Floating-Point Numbers
and Arithmetic Operations
Floating-Point Addition and Subtraction
+

Floating-Point
Multiplication
+

Floating-Point
Division
+
Precision Considerations
Guard Bits
+
Precision Considerations
Rounding
 IEEE standard approaches:
 Round to nearest:
 The result is rounded to the nearest representable number.
 Round toward +∞ :
 The result is rounded up toward plus infinity.
 Round toward -∞:
 The result is rounded down toward negative infinity.
 Round toward 0:
 The result is rounded toward zero.
+
Interval Arithmetic
 Provides an efficient method for  Minus infinity and rounding to
monitoring and controlling errors in plus are useful in
floating-point computations by implementing interval
producing two values for each result
arithmetic
 The two values correspond to the lower
and upper endpoints of an interval that
contains the true result Truncation
 The width of the interval indicates the  Round toward zero
accuracy of the result
 Extra bits are ignored
 If the endpoints are not representable
then the interval endpoints are rounded  Simplest technique
down and up respectively
 A consistent bias toward zero in the
 If the range between the upper and operation
lower bounds is sufficiently narrow  Serious bias because it affects every
then a sufficiently accurate result has
operation for which there are
been obtained
nonzero extra bits
+
IEEE Standard for Binary Floating-Point Arithmetic
Infinity

Is treated as the limiting case of real arithmetic, with the infinity values
given the following interpretation:

- ∞ < (every finite number) < + ∞

For example:
5 + (+ ∞ ) = + ∞ 5÷ (+ ∞ ) = +0
5 - (+ ∞ ) = - ∞ (+ ∞ ) + (+ ∞ ) =+∞
5 + (- ∞ ) = - ∞ (- ∞ ) + (- ∞) =-∞
5 - (- ∞ ) =+∞ (- ∞ ) - (+ ∞ ) =-∞
5 * (+ ∞ ) = + ∞ (+ ∞ ) - (- ∞ ) =+∞
+IEEE Standard for Binary Floating-Point Arithmetic
Quiet and Signaling NaNs
 Signaling NaN signals an invalid operation exception whenever it
appears as an operand

 Quiet NaN propagates through almost every arithmetic operation

without signaling an exception

Table 10.7

Operations that Produce a

Quiet NaN
+IEEE Standard for Binary Floating-Point Arithmetic
Subnormal Numbers
+ Summary Computer
Arithmetic
Chapter 10
 Integer arithmetic
 ALU  Negation
 Integer representation  Addition and subtraction
 Sign-magnitude representation  Multiplication
 Twos complement  Division
representation
 Floating-point arithmetic
 Range extension
 Addition and subtraction
 Fixed-point representation
 Multiplication and division
 Floating-point representation
 Precision consideration
 Principles
 IEEE standard for binary floating-
 IEEE standard for binary
point arithmetic
floating-point representation