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Metal Mumps

The MetalMUMPs process uses electroplated nickel as the primary structural material and electrical interconnect layer. Doped polysilicon can be used for resistors, additional mechanical structures, and electrical routing. Silicon nitride is used as an electrical isolation layer, while deposited oxide is used for sacrificial layers. The process involves depositing and patterning various layers including oxide, nitride, polysilicon, and metal using lithography and etching to build MEMS devices that are later released using an HF etch of the sacrificial oxide layers.

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0% found this document useful (0 votes)
569 views27 pages

Metal Mumps

The MetalMUMPs process uses electroplated nickel as the primary structural material and electrical interconnect layer. Doped polysilicon can be used for resistors, additional mechanical structures, and electrical routing. Silicon nitride is used as an electrical isolation layer, while deposited oxide is used for sacrificial layers. The process involves depositing and patterning various layers including oxide, nitride, polysilicon, and metal using lithography and etching to build MEMS devices that are later released using an HF etch of the sacrificial oxide layers.

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© Attribution Non-Commercial (BY-NC)
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MetalMUMPs

Process Flow

Stafford Johnson
Advanced Development
Engineering Manager
MetalMUMPs Process

(1) Electroplated nickel is used as the primary structural material and electrical
interconnect layer
(2) Doped polysilicon can be used for resistors, additional mechanical
structures, and/or cross-over electrical routing.
(3) Silicon nitride is used as an electrical isolation layer
(4) Deposited oxide (PSG) is used for the sacrificial layers
(5) A trench layer in the silicon substrate can be incorporated for additional
thermal and electrical isolation

2
MetalMUMPs Process

Oxide 1 Deposited

FIGURE 1.2. A 2µm thick oxide (Isolation Oxide) is grown on the surface of the
starting n-type (100) silicon wafer. This is followed by deposition of a 0.5µm
thick sacrificial phosphosilicate glass (PSG) layer (Oxide 1).

3
MetalMUMPs Process

Oxide 1 Patterned
Mask Level: OXIDE1

FIGURE 1.3 The wafers are coated with UV-sensitive photoresist and
lithographically patterned by exposing to UV light through the first level mask
(OXIDE1), and then developing it. The photoresist in exposed areas is
removed, leaving behind a patterned photoresist mask for etching. Wet
chemical etching is used to remove the unwanted sacrificial PSG. After the
etch, the photoresist is chemically stripped.

4
MetalMUMPs Process

Nitride 1 and Poly Deposited


Mask Level: OXIDE1

FIGURE 1.4. A 0.35µm layer of silicon nitride (Nitride 1) is deposited, followed


immediately by the deposition of a 0.7µm layer of polysilicon (Poly).

5
MetalMUMPs Process

Poly Patterned
Mask Level: POLY

FIGURE 1.5. The wafers are coated with photoresist and the second level
(POLY) is lithographically patterned. Reactive ion etching (RIE) is used to
remove the unwanted polysilicon. After the etch is completed, the photoresist is
removed.

6
MetalMUMPs Process

Nitride 2 Deposited

FIGURE 1.6. A second 0.35µm layer of silicon nitride (Nitride 2) is deposited.

7
MetalMUMPs Process

Nitride(s) Patterned
Mask Level: NITRHOLE

FIGURE 1.7. The wafers are coated with photoresist and the third level
(NITRHOLE) is lithographically patterned. RIE etching is performed to remove
both Nitride 2 and Nitride 1 from the patterned areas. After the etch is complete,
the photoresist is removed. Note: Nitride 1 will remain anywhere NITRHOLE is
patterned over Poly.

8
MetalMUMPs Process

Oxide 2 Deposited

FIGURE 1.8. A second sacrificial layer (Oxide 2), 1.1µm of PSG, is deposited
and annealed at 1050°C for 1 hour.

9
MetalMUMPs Process

Oxide 2 Patterned and Anchor Metal Dep


Mask Level: METANCH

FIGURE 1.9. The wafer is coated with photoresist and the fourth mask level
(METANCH) is lithographically patterned. The Oxide 2 is wet etched and a thin
metal layer (Anchor Metal) consisting of 10nm Cr + 25nm Pt is deposited. A liftoff
process is used to remove the photoresist and leave Anchor Metal only in the
bottom of the Oxide 2 openings formed from the METANCH mask level.

10
MetalMUMPs Process

Plating Base Dep and Plating Stencil Patterned


Mask Level: METAL

FIGURE 1.10 The Plating base layer, consisting of 500nm Cu + 50nm Ti is


deposited. (Not shown). The wafers are coated with a thick layer of photoresist
and patterned with the fifth mask level (METAL). This process forms a
patterned stencil for the electroplated Metal layer.

11
MetalMUMPs Process

Metal Plated

FIGURE 1.11. Nickel is electroplated to a nominal thickness of 20µm into the


patterned resist stencil. A 0.5µm gold layer is then immediately electroplated on
top of the nickel layer. This forms the Metal layer.

12
MetalMUMPs Process

Plating Stencil Removed

FIGURE 1.12. The photoresist stencil is then chemically removed.

13
MetalMUMPs Process
Gold Over Plating Stencil Patterned
Mask Level: GOLDOVP

FIGURE 1.13. The wafers are coated with photoresist and patterned with a
“bloated” version of the sixth mask level (GOLDOVP) to remove Plating Base in
the regions where Sidewall Metal is desired. The Plating Base is chemically
removed from the unpatterned regions, and the photoresist is stripped. The
wafers are coated with photoresist and patterned with an “un-bloated” version of
the sixth mask level (GOLDOVP) to define a resist stencil in the regions of Metal
where electroplated Sidewall Metal is desired.

14
MetalMUMPs Process

Gold Over Plating

FIGURE 1.14. A 1-3µm gold layer (Sidewall Metal) is electroplated using the
GOLDOVP photoresist mask as a stencil.

15
MetalMUMPs Process

Gold Over Plating Stencil Removed

FIGURE 1.15. The GOLDOVP resist stencil is stripped.

16
MetalMUMPs Process

Plating Base and Sacrificial Oxides Removed

FIGURE 1.16. Plating Base is chemically stripped in the first step of the release
process. In the second step of the release process, a 49% HF solution is used
to remove the PSG sacrificial layers (Oxide 1 and Oxide 2) and the Isolation
Oxide layer over the trench areas.

17
MetalMUMPs Process

Trench Formed – Silicon Etched

FIGURE 1.17. In the final step of the release process, a KOH silicon etch is
used to form a 25µm deep trench in the silicon substrate in the areas defined
by the OXIDE1 and NITRHOLE mask levels. A protective coating is applied,
wafers are diced, cleane, sorted and shipped to customer.

18
MetalMUMPs Published Paper

• Two Movable Plate Nitride


Loaded MEMS Variable
Capacitor
– Maher Bakri- Kassem and
Raafat R. Mansour
University of Waterloo
– A MEMS variable capacitor having two
movable plates loaded with a Nitride
layer is proposed. A trench in the silicon
substrate underneath the capacitor is
used to decrease the parasitic
capacitance. The use of an insulation
dielectric layer on the bottom plate of
the MEMS capacitor increases the
capacitor’s tuning range and eliminates
sticktion. The tuning range was
measured and found to be 280% at 1
GHz. The achievable tuning range far
exceeds that of the traditional parallel
plate MEMS variable capacitors. The
proposed MEMS variable capacitor is
built using the MetalMUMPs process.

19
MetalMUMPs Published Paper

• Two Movable Plate Nitride Loaded MEMS


Variable Capacitor
– Maher Bakri- Kassem and Raafat R. Mansour
University of Waterloo

20
Poly/Nickel powered gripper

• Tethering 0%
effective as
indicated previously
by JDSU
• Same tether as other
grippers and parts –
placement along
bottom only was
ineffective

21
Parts for assembly

• 100% successful
tethering
• 0% success parts
removal with gripper
• 100% successful
tether break with
probe and part
release
• No successful
assembly yet

22
Parts for assembly

• Nitride with poly


rib tether was
100% effective
– Poly rib
– Nitride hole

23
MetalMUMPs Bistable Relay

Contacts
Disengage actuators

Engage actuators

24
Thermal actuator

• Structural layers can be electrically insulated


from thermal heaters
Electroplated 
nickel actuator

Polysilicon heater

25
Shuttle Motion

26
What Can You Make in MetalMUMPs?
Copper Cross Connect Switch

27

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