ECE 211 Digital Electronics

UNIT - II

Combinational Circuits

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Syllabus
• Introduction
• Half Adder & Full Adder
• Half Subtractor & Full Subtractor
• Binary Parallel Adder - Carry look ahead adder
• BCD Adder
• Encoder
• Priority Encoder
• Decoder
• Multiplexer
• Demultiplexer
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Magnitude Comparator. Fall 2020 - ECE 211 Digital Electronics 2
 Introduction

A combinational circuit consists of input variables, logic gates, and output

variables.

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 Design Procedure:

1. The number of available input variables and output variables are

determined.
2. The input and output variables are assigned letter symbols.
3. The truth table that defines the relationships between inputs and outputs
is derived.
4. The simplified Boolean function for each output is obtained.
5. Finally, we draw the logic diagram.

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 Adders

1.The most basic arithmetic operation in digital systems is

addition of two binary digits.
2.The four possible operations are 0+0=0, 0+1=1, 1+0=1, and
1+1=10.
3.The most significant bit in the 4th operation is called as carry.
4.A combinational circuit that performs the addition of two bits is
called a half-adder.
5.A combinational circuit that performs the addition of three bits
is called a full adder.

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Half-Adder
Truth Table
x y Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Logic Diagram
The simplified Boolean expressions for sum and carry expressions are

𝑆=𝑥 𝑦 + 𝑥 𝑦
𝐶=𝑥𝑦
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 Full-Adder
Truth Table
x y z Carry Sum
0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0 𝐶 =𝑥𝑦 +𝑥𝑧+𝑦𝑧
1 0 0 0 1
1 0 1 1 0

1 1 0 1 0
1 1 1 1 1

03/11/2023 𝑆=𝑥 𝑧 𝑦 +𝑥 𝑦 𝑧 +𝑦 𝑥 𝑧+𝑥𝑦𝑧

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 Logic Diagram for Full Adder

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 Implementation of Full Adder Using Two Half-Adders

𝑆=𝑥 ⊕ 𝑦 ⊕ 𝑧
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𝐶 =𝑧 ( 𝑥 ⊕ 𝑦 )+ 𝑥𝑦
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Subtractor
1.A half subtractor is a combinational circuit that subtracts two
binary bits and produces the difference.
2.The half subtractor has two outputs. One output generates
difference and second output borrow.
3.A full subtractor is a combinational circuit that performs a
subtraction between two bits and one bit may be borrowed
by a lower significant stage.
4.A full subtractor has three inputs and two outputs.

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 Half-Subtractor
Truth Table

x y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

The simplified Boolean expressions for sum and carry expressions are

D =𝑥 𝑦 + 𝑥 𝑦
B=𝑥 𝑦
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Full-Subtractor
Truth Table
x y z B D
0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 1 0 B  xy  xz  yz
1 0 0 0 1
1 0 1 0 0

1 1 0 0 0
1 1 1 1 1

03/11/2023 D  xzy  xyz  yxz  xyz

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Surprise Test

Q1. Design a logical circuit which will do the following

1. Binary to Gray Code conversion (consider 4 bits) [10 marks]
2. BCD to Seven Segment Display [10 marks]
3. BCD to XS-3 Code conversion [10 marks]
Please note: Don’t copy anything from anywhere

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Binary Parallel Adder
1.A binary parallel
adder is a digital
circuit computes
the arithmetic sum
of two binary
numbers parallel.
2.A n-bit parallel
adder consists of
n-full adders.

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Binary-Parallel Adder

𝑃 𝑖= 𝐴𝑖 ⊕ 𝐵𝑖
𝐺𝑖= 𝐴 𝑖 𝐵𝑖
𝑆 𝑖= 𝑃 𝑖 ⊕ 𝐶 𝑖
𝐶 𝑖 +1= 𝐺𝑖 + 𝑃 𝑖 𝐶 𝑖
Full Adder Circuit
𝑃𝑖 is Carry Propagate
𝐺𝑖 is Carry Generate
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 Carry Look Ahead Generator

𝐶 2=𝐺1 + 𝑃 1 𝐶 1
𝐶 3 =𝐺2 + 𝑃 2 𝐶 2=𝐺2 + 𝑃 2 𝐺1 + 𝑃 2 𝑃1 𝐶 1
03/11/2023𝐶 4 =𝐺 3 + 𝑃 3 𝐶 3 =𝐺 3 +Fall𝑃 3 -𝐺
2020 𝑃 Electronics
2+Digital
ECE 211 3 𝑃 2 𝐺1 + 𝑃 3 𝑃 2 𝑃 1 𝐶 1 17
4-bit Full Adders with Carry Look-Ahead

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 10
9
1
8 C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1C0
7

6
1
2 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
5
4
2
3 3
C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
2
3
4
1
C1 = G0 + P0C0
4

C0
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BCD Adder
1. If we apply two BCD
digits to a 4-bit binary
adder, Then adder will
form the sum in binary
and produce a result that
range from 0 to 19.
2. These numbers are
labelled by symbols
K, , 𝑍 1𝑍 𝑍, 8.
, 2

3. K is the carry and the

subscripts under the letter
Z represents the weights
8,4,2,1.
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 BCD Adder
1. When the binary sum is greater than 1001, we obtain a non- valid BCD
representation.

2. The addition of binary 6(0110) to the binary sum converts it to the correct BCD
representation and produces an output carry.
3. The condition for a correction and output carry can be expressed
by the Boolean function

4. When C=1, it is necessary to add 0110 to the binary sum and pass a output
carry for the next stage.
5. A BCD adder is a circuit that adds two BCD digits in parallel and produces a
sum digit in BCD.
6. A decimal parallel adder adds n decimal digits needs n BCD adder stages. The
output carry from one stage must be connected to the input carry of the next
higher order stage
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 BCD Adder

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 4-bit Magnitude Comparator
1. A magnitude comparator is a combinational circuit that
compares two numbers, A and B and determines their relative
magnitudes.
2. The comparison will be based on A>B, A=B, A<B.
3. If we consider the comparison of two binary numbers with 4
digits 𝑨= 𝑨 𝟑 𝑨 𝟐 𝑨𝟏 𝑨𝟎
𝑩= 𝑩𝟑 𝑩 𝟐 𝑩 𝟏 𝑩𝟎
4. Then Logical Expressions of 4-bit comparator will be
( 𝑨=𝑩 ¿ ¿ 𝒙 𝟑 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎
( 𝑨>𝑩 ¿ ¿ 𝑨 𝟑 𝑩𝟑 +𝒙 𝟑 𝑨 𝟐 𝑩𝟐+ 𝒙𝟑 𝒙𝟐 𝑨𝟏 𝑩𝟏+𝒙 𝟑 𝒙 𝟐 𝒙 𝟏 𝑨 𝟎 𝑩𝟎
( 𝑨<𝑩 ¿ ¿ 𝑨 𝟑 𝑩𝟑 +𝒙 𝟑 𝑨 𝟐 𝑩𝟐+ 𝒙𝟑 𝒙𝟐 𝑨𝟏 𝑩𝟏+𝒙 𝟑 𝒙 𝟐 𝒙 𝟏 𝑨 𝟎 𝑩𝟎
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 Magnitude Comparator Logic Diagram

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 3 to 8 Line Decoder
Truth Table

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3 to 8 Line Decoder Logic Diagram

1. A binary code of n bits is

capable of representing upto
distinct elements of coded
information.
2. A decoder is a
combinational circuit that
converts binary information
from n-input lines to a
maximum of unique output
lines.
3. Any combinational circuit
with n inputs and m outputs
can be implemented with an
n to line decoder and m or
gates.
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 8 to 3 Line Encoder
Truth Table
An encoder is a digital circuit that has
input elements and n output elements.

Logical Expressions

𝒛= 𝑫𝟏 + 𝑫 𝟑 + 𝑫 𝟓+ 𝑫𝟕
𝒚 = 𝑫 𝟐 + 𝑫𝟑 + 𝑫 𝟔 + 𝑫 𝟕
𝒙 = 𝑫 𝟒 + 𝑫𝟓 + 𝑫 𝟔 + 𝑫 𝟕

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 8 to 3 Line Encoder Logic Diagram

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Priority Encoder
Truth Table
1. A priority encoder is an
encoder circuit that
implements the priority
function.
2. In this circuit, if two or
more inputs are equal to 1 at
the same time, then the input
having the highest priority
will take precedence.

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 Karnaugh Maps for Priority Encoder

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Logic Diagram for 4-input Priority Encoder

Logical Expressions
𝑥= 𝐷 2+ 𝐷3
′
𝑦= 𝐷 3 + 𝐷1 𝐷 2
𝑉 = 𝐷 0 + 𝐷1 + 𝐷 2 + 𝐷3

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 Multiplexer
1. A digital multiplexer is a
combinational circuit that
Function Table Block Diagram selects binary information from
one of many input lines and
directs it to a single output line.

2. The selection of a particular input

line is controlled by a set of
selection lines.

3. Generally, there are input lines

and n selection lines.

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4 to 1 Line Multiplexer Logic Diagram

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 Demultiplexer

Truth Table

Logic Expressions

Block Diagram

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Demultiplexer
A demultiplexer is a circuit that
receives information on a single
line and transmits information
on one of possible output lines.

The selection of a specific

output line is controlled by the n
selection lines.

A decoder with a enable input

functions as a demultiplexer.

1-to-4 Demultiplexer Logic Diagram

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Classification

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References
1. Digital Design 5th Edition by M Morris Mano, PEARSON INDIA.

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XS3 Addition
• Step 1
We have to convert the numbers (which are to be added) into excess 3 forms by
adding 0011 with each of the four bit groups them or simply increasing them by 3.
Step 2
Now the two numbers are added using the basic laws of binary addition, there is
no exception for this method.
Step 3
Now which of the four groups have produced a carry we have to add 0011 with
them and subtract 0011 from the groups which have not produced a carry during
the addition.
Step 4
The result which we have obtained after this operation is in Excess 3 form and this
is our desired result
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0011 0101 0110 and 0101 0111 1001 are the two binary numbers. Now following
the first step we take the excess 3 form of these two numbers which are 0110 1000
1001 and 1000 1010 1100, now these numbers are added following the basic rules
of addition.

Now adding 0011 to the groups which produces a carry and subtracting
zero from the groups which did not produced carry we get the result as
1100 0110 1000 is the result of the addition in excess 3 code and the BCD
answer is 1001 0011 0101.

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