Chapter
Chapter
Chapter
Input/Output
Organization
Computer Architecture and
Organization
1
Overview
Computer has ability to exchange data with
other devices.
Human-computer communication
Computer-computer communication
Computer-device communication
…
2
Accessing I/O Devices
3
Single Bus
Processor Memory
Bus
Input device
6
Program-Controlled I/O
I/O devices operate at speeds that are very
much different from that of the processor.
Keyboard, for example, is very slow.
It needs to make sure that only after a
character is available in the input buffer of the
keyboard interface; also, this character must
be read only once.
7
Three Major Mechanisms
Program-controlled I/O – processor polls the
device.
Interrupt
Direct Memory Access (DMA)
8
Interrupts
9
Overview
In program-controlled I/O, the program enters
a wait loop in which it repeatedly tests the
device status. During the period, the
processor is not performing any useful
computation.
However, in many situations other tasks can
be performed while waiting for an I/O device
to become ready.
Let the device alert the processor.
10
Enabling and Disabling
Interrupts
Since the interrupt request can come at any
time, it may alter the sequence of events from
that envisaged by the programmer.
Interrupts must be controlled.
11
Enabling and Disabling
Interrupts
The interrupt request signal will be active
until it learns that the processor has
responded to its request. This must be
handled to avoid successive interruptions.
Let the interrupt be disabled/enabled in the interrupt-
service routine.
Let the processor automatically disable interrupts before
starting the execution of the interrupt-service routine.
12
Handling Multiple Devices
How can the processor recognize the device requesting an
interrupt?
Given that different devices are likely to require different
interrupt-service routines, how can the processor obtain the
starting address of the appropriate routine in each case?
(Vectored interrupts)
Should a device be allowed to interrupt the processor while
another interrupt is being serviced?
(Interrupt nesting)
How should two or more simultaneous interrupt requests be
handled?
(Daisy-chain)
13
Vectored Interrupts
A device requesting an interrupt can identify
itself by sending a special code to the
processor over the bus.
Interrupt vector
Avoid bus collision
14
Interrupt Nesting
Simple solution: only accept one interrupt at a time, then disable
all others.
Problem: some interrupts cannot be held too long.
Priority structure
INTR 1 I NTR p
Processor
INTA1 INTA p
Priority arbitration
circuit
Processor
Device 1 Device 2 Device n
INTA
I NTR 1
Device Device
INTA1
Processor
INTR p
Device Device
INTA p
Priority arbitration
circuit
16
18
Use of Interrupts in Operating
Systems
The OS and the application program pass
control back and forth using software
interrupts.
Supervisor mode / user mode
Multitasking (time-slicing)
Process – running, runnable, blocked
Program state
19
Processor Examples
20
15 13 10 8 4 3 2 1 0
T S X N Z V C
Trace
Condition
Interrupt Codes
Supervisor
Priority
21
Main program
MOVE.L #LINE,PNTR Initialize buffer pointer.
CLR EOL Clear end-of-line indicator.
ORI.B #4,CONTROL Set bit KEN.
MOVE #$100,SR Set pro cessor priority to 1.
..
.
Interrupt-service routine
READ MOVEM.L A0/D0, – (A7) Save registers A0, D0 on stack.
MOVEA.L PNTR,A0 Load address pointer.
MOVE.B DATAIN,D0 Get input character.
MOVE.B D0,(A0)+ Store it in memory buffer.
MOVE.L A0,PNTR Update pointer.
CMPI.B #$0D,D0 Check if Carriage Return.
BNE RTRN
MOVE #1,EOL Indicate end of line.
ANDI.B #$FB,CONTROL Clear bit KEN.
RTRN MOVEM.L (A7)+,A0/D0 Restore registers D0, A0.
RTE
Figure 4.15. A 68000 interrupt-service routine to read an input line from a keyboard based on Figure 4.9.
22
Direct Memory Access
23
DMA
Think about the overhead in both polling and
interrupting mechanisms when a large block of data
need to be transferred between the processor and
the I/O device.
A special control unit may be provided to allow
transfer of a block of data directly between an
external device and the main memory, without
continuous intervention by the processor – direct
memory access (DMA).
The DMA controller provides the memory address
and all the bus signals needed for data transfer,
increment the memory address for successive
words, and keep track of the number of transfers.
24
DMA Procedure
Processor sends the starting address, the number of
data, and the direction of transfer to DMA controller.
Processor suspends the application program
requesting DMA, starts DMA transfer, and starts
another program.
After the DMA transfer is done, DMA controller
sends an interrupt signal to the processor.
The processor puts the suspended program in the
Runnable state.
25
DMA Register
31 30 1 0
IRQ Done
IE R/ W
Starting address
Word count
26
System
Main
Processor
memory
System bus
Disk/DMA DMA
controller controller Printer Keyboard
B BS Y
BR
Processor
DMA DMA
controller controller
BG1 1 BG2 2
Figure 4.20. A simple arrangement for bus arbitration using a daisy chain.
30
Centralized Arbitration
Time
BR
BG1
BG2
B BS Y
Bus
master
Processor DMA controller 2 Processor
31
Distributed Arbitration
Vcc
ARB 3
ARB 2
ARB 1
ARB 0
Start-Arbitration
O.C.
0 1 0 1 0 1 1 1
Interface circuit
for device A
33
Overview
The primary function of a bus is to provide a
communications path for the transfer of data.
A bus protocol is the set of rules that govern the
behavior of various devices connected to the bus as
to when to place information on the bus, assert
control signals, etc.
Three types of bus lines: data, address, control
The bus control signals also carry timing
information.
Bus master (initiator) / slave (target)
34
Synchronous Bus Timing
Time
Bus clock
Address and
command
Data
t0 t1 t2
Bus cycle
35
Synchronous Bus Detailed
Timing Time
Bus clock
Seen by master t AM
Address and
command
Data
t DM
Seen by slave
tAS
Address and
command
Data
tDS
t0 t1 t2
36
Figure 4.24. A detailed timing diagram for the input transfer of Figure 4.23.
Multiple-Cycle Transfers
Time
1 2 3 4
Clock
Address
Command
Data
Slave-ready
Address
and command
Master-ready
Slave-ready
Data
t0 t1 t2 t3 t4 t5
Bus cycle
Address
and command
Data
Master-ready
Slave-ready
t0 t1 t2 t3 t4 t5
Bus cycle
41
Function of I/O Interface
Provide a storage buffer for at least one word of
data;
Contain status flags that can be accessed by the
processor to determine whether the buffer is full or
empty;
Contain address-decoding circuitry to determine
when it is being addressed by the processor;
Generate the appropriate timing signals required by
the bus control scheme;
Perform any format conversion that may be
necessary to transfer data between the bus and the
I/O device.
42
Parallel Port
A parallel port transfers data in the form of a
number of bits, typically 8 or 16,
simultaneously to or from the device.
For faster communications
43
Parallel Port – Input Interface (Keyboard
to Processor Connection)
Data
Address
DATAIN Data
Encoder
R /W and Keyboard
Processor SIN
debouncing switches
Master-ready circuit
Valid
Input
Slave-ready
interface
44
DATAIN
D7 Q7 D7
Keyboard
data
D0 Q0 D0
SIN
Status Valid
flag
Slave-
ready 1
Read-
status
Read-
data
R/ W
Master-
ready
A31
Address
decoder
A1
A0
46
Parallel Port – Output Interface
(Printer to Processor Connection)
Data
Processor
CPU R /W SOUT Printer
Valid
Master-eady
Output Idle
Slave-ready interface
DATAIN
D1
D0 PA0
SIN
Input
status CA
PB7
DATAOUT
PB0
SOUT
Handshake CB1
control CB2
Slave-
Ready 1
Master-
Ready
R/ W
A31
Address My-address
decoder
A2
RS1
A1
RS0
A0
49
DATAIN
D0 P0
DATAOUT
Data
Direction
Register
My-address
RS2
RS1 Status C1
Register
RS0 and
select control
R /W C2
Ready
Accept
INTR
50
Figure 4.34. A general 8-bit parallel interface.
Recall the Timing Protocol
Time
1 2 3 4
Clock
Address
Command
Data
Slave-ready
D7 D7 Q7
Printer
data
D0 D1 Q1
D0 D0 Q0
SOUT
Handshake Idle
control Valid
Read Load
status data
R/W
Slav e-
ready
Go
A31
Address My-address Timing
decoder Logic
A1
A0
Clock
My-address
Idle Respond
Go=1
52
Figure 4.35. A parallel point interface for the bus of Figure 4.25,
with a state-diagram for the timing logic.
Serial Port
A serial port is used to connect the processor
to I/O devices that require transmission of
data one bit at a time.
The key feature of an interface circuit for a
serial port is that it is capable of
communicating in bit-serial fashion on the
device side and in a bit-parallel fashion on
the bus side.
Capable of longer distance communication
than parallel transmission.
53
Serial
Input shift register input
DATAIN
D7
D0
DATAOUT
My-address
RS1
RS0 Chip and
register Serial
R /W Output shift register output
select
Ready
Accept
Receiving clock
Status
I NTR and
control
Transmission clock
54
Figure 4.37. A serial interface.
Standard I/O
Interfaces
55
Overview
The needs for standardized interface signals
and protocols.
Motherboard
Bridge: circuit to connect two buses
Expansion bus
ISA, PCI, SCSI, USB,…
56
Main
Processor
memory
Processor bus
Bridge
PCI bus
SCSI bus
IDE
disk
Video
Disk CD-ROM
controller controller
CD-
Disk 1 Disk 2 ROM K eyboard Game
57