ENCS 3310

Advanced Digital Design

RTL coding
Introduction

 RTL coding examples

 Flip-Flops and Latches
//D flip-flop //D flip-flop with asynchronous
module D_FF reset.
(Q,D,CLK); module DFF (Q,D,CLK,RST);
output Q; output Q;
input D,CLK;
input D,CLK,RST;
reg Q;
reg Q;
always @(posedge
CLK) always @(posedge CLK or
Q = D;
negedge RST)
endmodule if (~RST) Q = 1'b0; // Same
as: if (RST = 0)
else Q = D;
endmodule
T & J-K Flip-Flops
//T flip-flop from D flip-flop //JK flip-flop from D flip-flop
and gates and gates
module TFF module JKFF
(Q,T,CLK,RST); (Q,J,K,CLK,RST);
output Q; output Q;
input T,CLK,RST; input J,K,CLK,RST;
wire DT; wire JK;
assign DT = Q ^ T ; assign JK = (J & ~Q) | (~K
& Q);
//Instantiate the D flip-flop
//Instantiate D flipflop
DFF TF1
(Q,DT,CLK,RST); DFF JK1 (Q,JK,CLK,RST);
endmodule endmodule
Characteristic equations of the flip-
Q (t  1)  Q  T
flops: for a T flip - flop
Q(t  1)  JQ' K ' Q for a JK flip - flop
J-K Flip-Flop
// Functional description of JK //
flip-flop
module JK_FF (J,K,CLK,Q,Qnot);
output Q,Qnot;
input J,K,CLK;
reg Q;
assign Qnot = ~ Q ;
always @(posedge CLK)
case({J,K})
2'b00: Q = Q;
2'b01: Q = 1'b0;
2'b10: Q = 1'b1;
2'b11: Q = ~ Q;
endcase
endmodule
Sequential Circuit – Ex1
Sequential Circuit – Ex1 Behavioral Code

//Mealy state diagram for the circuit

module Mealy_mdl (x,y,CLK,RST);
input x,CLK,RST;
output y;
reg y;
reg [1:0] Prstate,Nxtstate;
parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11;
always@(posedge CLK or negedge RST)
if (~RST) Prstate = S0; //Initialize to
state S0
else Prstate = Nxtstate; //Clock operations
Code…
always @(Prstate or x) //Determine next state
case (Prstate)
S0: if (x) Nxtstate = S1;
S1: if (x) Nxtstate = S3;
else Nxtstate = S0;
S2: if (~x)Nxtstate = S0;
S3: if (x) Nxtstate = S2;
else Nxtstate = S0;
endcase
always @(Prstate or x) //Evaluate output
case (Prstate)
S0: y = 0;
S1: if (x) y = 1'b0; else y = 1'b1;
S2: if (x) y = 1'b0; else y = 1'b1;
S3: if (x) y = 1'b0; else y = 1'b1;
endcase
Sequential Circuit-Ex2
Ex2 – Behavioral code
//Moore state diagram
module Moore_mdl (x,AB,CLK,RST);
input x,CLK,RST;
output [1:0]AB;
reg [1:0] state;
parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11;
always @(posedge CLK or negedge RST)
if (~RST) state = S0; //Initialize to state S0
else
case(state)
S0: if (~x) state = S1;
S1: if (x) state = S2; else state = S3;

S2: if (~x) state = S3;

S3: if (~x) state = S0;
endcase
assign AB = state; //Output of flip-flops
Sequential Circuit Ex3
 Ex3 – Structural Code
//Structural description of sequential circuit
module Tcircuit (x,y,A,B,CLK,RST);
input x,CLK,RST;
output y,A,B;
wire TA,TB;
//Flip-flip input equations
assign TB = x,
TA = x & B;
//Output equation
assign y = A & B;
//Instantiate T flip-flops
T_FF BF (B,TB,CLK,RST);
T_FF AF (A,TA,CLK,RST);
endmodule
Structural Code… //Stimulus for testing seq. ci
module testTcircuit;
//T flip-flop reg x,CLK,RST; //inputs for
circuit
module T_FF
(Q,T,CLK,RST); wire y,A,B; //output from
circuit
output Q;
Tcircuit TC(x,y,A,B,CLK,RST)
input T,CLK,RST;
initial begin
reg Q;
always@(posedge RST = 0; CLK = 0;
CLK or #5 RST = 1;
repeat (16)
negedge RST)
if(~RST) Q=1'b0; #5 CLK = ~CLK;
else Q=Q^T; end
endmodule initial begin
x = 0; #15 x = 1;
repeat (8)
#10 x = ~ x;
end
HDL for Registers and Counters

 Registers and counters can be described in HDL at either the

behavioral or the structural level.
 In the behavioral, the register is specified by a description of the
various operations that it performs similar to a function table.
 A structural level description shows the circuit in terms of a
collection of components such as gates, flip-flops and
multiplexers.
 The various components are instantiated to form a hierarchical
description of the design similar to a representation of a logic
diagram.
Universal Shift Register Example-1

HDL for Registers and Counters (2)

 Universal Shift Register Example-2

Clear CLK Load Count Function 4-bit

0 X X X Clear to 0
binary
counter
1 +ve 1 X Load inputs
with
1 +ve 0 1 Count next
binary state
parallel
load
1 +ve 0 0 No change

Mode Control Function

S1 S0 Register Operation table for
0 0 No Change 4-bit
0 1 Shift Right Universa
1 0 Shift Left l Shift
1 1 Parallel Load
Register
Universal Shift Register Example-3
//Behavioral description of Universal shift register
module shftreg (s1,s0,Pin,lfin,rtin,A,CLK,Clr);
input s1,s0; //Select inputs
input lfin, rtin; //Serial inputs
input CLK,Clr; //Clock and Clear
input [3:0] Pin; //Parallel input
output [3:0] A; //Register output
reg [3:0] A;
always @ (posedge CLK or negedge Clr)
if (~Clr) A = 4'b0000;
else
case ({s1,s0})
2'b00: A = A; //No change
2'b01: A = {rtin,A[3:1]}; //Shift right
2'b10: A = {A[2:0],lfin}; //Shift left
//Parallel load input
2'b11: A = Pin;
endcase
endmodule
Universal Shift Register Example-4
//Structural description of Universal shift register
module SHFTREG (I,select,lfin,rtin,A,CLK,Clr);
input [3:0] I; //Parallel input
input [1:0] select; //Mode select
input lfin,rtin,CLK,Clr; //Serial input,clock,clear
output [3:0] A; //Parallel output
//Instantiate the four stages
stage ST0 (A[0],A[1],lfin,I[0],A[0],select,CLK,Clr);
stage ST1 (A[1],A[2],A[0],I[1],A[1],select,CLK,Clr);
stage ST2 (A[2],A[3],A[1],I[2],A[2],select,CLK,Clr);
stage ST3 (A[3],rtin,A[2],I[3],A[3],select,CLK,Clr);
endmodule
 Universal Shift Register Example -5
//One stage of shift register
module stage(i0,i1,i2,i3,Q,select,CLK,Clr);
input i0,i1,i2,i3,CLK,Clr;
input [1:0] select;
output Q;
reg Q,D;
//4x1 multiplexer
always @ (i0 or i1 or i2 or i3 or select)
case (select)
2'b00: D = i0; //Continue - D flip-flop
2'b01: D = i1; always@(posedge CLK or negedge
Clr)
2'b10: D = i2;
if (~Clr) Q = 1'b0;
2'b11: D = i3;
endcase else Q = D;
endmodule
Counter with parallel load –Ex1

4 bit
Binary
Counter
with
Parallel
Load
Counter with Parallel Load Ex2
//Binary counter with parallel load
module counter (Count,Load,IN,CLK,Clr,A,CO);
input Count,Load,CLK,Clr;
input [3:0] IN; //Data input
output CO; //Output carry
output [3:0] A; //Data output
reg [3:0] A;
assign CO = Count & ~Load & (A == 4'b1111);
always @(posedge CLK or negedge Clr)
if (~Clr) A = 4'b0000;
else if (Load) A = IN;
else if (Count) A = A + 1'b1;
else A = A; // no change, default condition
endmodule
Ripple Counter Example-1
4-bit
Binary
Ripple
Counter
 Ripple Counter Example-2
//Ripple counter
module ripplecounter(A0,A1,A2,A3,Count,Reset);
output A0,A1,A2,A3;
input Count,Reset;
//Instantiate complementing flip-flop
CF F0 (A0,Count,Reset);
CF F1 (A1,A0,Reset); //Complementing flip-flop
CF F2 (A2,A1,Reset); //Input to D flip-flop = Q'
CF F3 (A3,A2,Reset); module CF (Q,CLK,Reset);
endmodule output Q;
input CLK,Reset;
reg Q;
always@(negedge CLK or posedge Reset)
if(Reset) Q=1'b0;
else Q=#2 (~Q);
endmodule
 Ripple Counter Example-3
//Stimulus for testing ripple counter
module testcounter;
reg Count;
reg Reset;
wire A0,A1,A2,A3;
//Instantiate ripple counter
ripplecounter RC (A0,A1,A2,A3,Count,Reset);
always
#5 Count = ~Count;
initial
begin
Count = 1'b0;
Reset = 1'b1;
#4 Reset = 1'b0;
#165 $finish;
end
endmodule
Summary
 Shift registers and RTL coding
 Behavioural and Structual Description for
Sequential Circuits