Course Name: Embedded System

• Topic Name: Instruction set Architecture (ISA)

By:
Dr. Karmjit Singh Sandha
Assistant Professor, ECED
Reference Books:

• Steve Furber, “ARM System-on-Chip Architecture, Second Edition, PEARSON,

2013.
• Stephen Welsh, Peter Knaggs, “ARM: Assembly Language Programming”, Bourne
Mouth University Publication, 2003.
• Andrew N. Sloss, Dominic Symes, Chris Wright “ARM System Developers Guide,
Designing and Optimizing System Software”, ELSEVIER Publication.
 Instruction Set of ARM
The ARM Instruction set can be divided
into six broad classes of instruction
1. Data Movement
2. Arithmetic
3. Memory Access
4. Logical and bit manipulation
5. Flow Control
6. System Control/ Privileged
Instruction Mnemonic
Condition code (cc) Mnemonic
 ARM instructions
Type of operation:

Arithmetic
Branch
Load and Store
Logical
Move
Arithmetic Instructions
ADD Add

ADC Add with carry

SUB Subtract

SBC Subtract with carry

RSB Reverse subtract

RSC Reverse subtract with carry

MUL Multiply

MLA Multiply and accumulate

UMULL Multiply - unsigned long

UMLAL Multiply and accumulate - unsigned long

SMULL Multiply - signed long

SMLAL Multiply and accumulate - signed long

CMP Compare

CMN Compare negative

 Branch Instructions:

B Branch
BL Branch with link
 Load and Store Instructions
LDR Load word
LDRB Load byte
LDRSB Load signed byte
LDRH Load half word
LDRSH Load signed half word
LDM Load multiple
LDM sp! Pop
STR Store word
STRB Store byte
STRH Store half word
STM Store multiple
STM sp! Push
Logical Instructions:

AND AND
EOR Exclusive OR
ORR OR
BIC Bit clear
TST Test
TEQ Test equivalence
 Move Instructions
MOV Move
MVN Move and negate
SWP Swap
SWPB Swap byte
MRS Move program status register to register
MSR Move register to program status register
 Arithmetic Instruction
Add
Syntax: ADD{cond}{S} Rd, Rn, Operand2

Elements inside curly brackets are optional.

Usage: Adds the value in Rn to Operand2 and places the sum in Rd.

Condition flags: If S is specified then all flags are updated according to the result.

Examples:

ADD r7, r4, #99 ;adds 99 to the value in r4 and places the sum in r7

ADD r1, r2, r3 ;adds the value in r3 to the value in r2 and places the sum in r1
 Add with carry
Syntax: ADC{cond}{S} Rd, Rn, Operand2
Elements inside curly brackets are optional.
Usage: Adds the value in Rn to Operand2 and adds another 1 if the carry flag is
set. The sum is placed in Rd.
Condition flags: If S is specified then all flags are updated according to the result.
Examples:
ADC r7, r4, #99 ;adds 99 to the value in r4 and adds another 1 if the carry flag is
set. Places the sum in r7
ADC r1, r2, r3 ;adds the value in r3 to the value in r2 and adds 1 if the carry flag
is set. Places the sum in r1
ADCCSS r1, r2, r3
 Subtract
Syntax: SUB{cond}{S} Rd, Rn, Operand2

Elements inside curly brackets are optional.

Usage: Subtracts Operand2 from the value in Rn and places the difference in
Rd.

Condition flags: If S is specified then all flags are updated according to the
result.

Examples:

SUB r7, r4, #99 ;subtracts 99 from the value in r4 and places the result in r7

SUB r1, r2, r3 ;subtracts the value in r3 from the value in r2 and places the
difference in r1
 Subtract with carry

Syntax: SBC{cond}{S} Rd, Rn, Operand2

Elements inside curly brackets are optional.

Usage: Subtracts Operand2 from the value in Rn and subtracts another 1 if the
carry flag is clear. Places the difference in Rd.

Condition flags: If S is specified then all flags are updated according to the result.

Examples:

SBC r7, r4, #99;

SBC r1, r2, r3;

 Reverse subtract
Syntax: RSB{cond}{S} Rd, Rn, Operand2

Elements inside curly brackets are optional.

Usage: Subtracts the value in Rn from Operand2 and places the difference in
Rd.

Condition flags: If S is specified then all flags are updated according to the
result.

Examples:

RSB r7, r4, #99 ;subtracts the value in r4 from 99 and places the result in r7

RSB r1, r2, r3 ;subtracts the value in r2 from the value in r3 and places the
difference in r1
 Reverse subtract with carry
Syntax: RSC{cond}{S} Rd, Rn, Operand2

Elements inside curly brackets are optional.

Usage: Subtracts the value in Rn from Operand2 and subtracts another 1 if the
carry flag is clear. Places the difference in Rd.

Condition flags: If S is specified then all flags are updated according to the
result.

Examples:

RSC r7, r4, #99

RSC r1, r2, r3

 Multiply
Syntax: MUL{cond}{S} Rd, Rm, Rs : Rd = Rm * Rs
Elements inside curly brackets are optional.
Usage: Multiples the values in registers Rm and Rs and places the least
significant 32 bits of the product in register Rd.
Condition flags: If S is specified then the N and Z flags are updated
according to the result, the V flag is not affected and the C flag is
unpredictable for the ARM7 and earlier processors.
Example:
MUL r5, r3, r9 ;multiply the values in r3 and r9 and places the result in r5
 Multiply and accumulate
Syntax: MLA{cond}{S} Rd, Rm, Rs, Rn : Rd = (Rm * Rs) + Rn

Elements inside curly brackets are optional.

Usage: Adds the value in Rn to the product of the values in Rm and Rs and places the

least significant 32 bits of the result in register Rd.

Condition flags: If S is specified then the N and Z flags are updated according to the

result, the V flag is not affected and the C flag is unpredictable for the ARM7 and earlier

processors.

Example:

MLA r5, r3, r9, r6 ;multiply the values in r3 and r9, add the product to the value in r6

and places the result in r5

 Multiply - unsigned long
Syntax: UMULL{cond}{S} RdLo, RdHi, Rm, Rs

Elements inside curly brackets are optional.

Usage: Multiples the values (as unsigned integers) in registers Rm and Rs

and places the least significant 32 bits of the product in register RdLo and
the most significant 32 bits of the product in register RdHi.

Condition flags: If S is specified then the N and Z flags are updated

according to the result and the V and C flags are unpredictable for the
ARM7 and earlier processors.

Example:

UMULL r6, r5, r3, r9 ;multiply the values in r3 and r9 and places the result
in r5 and r6
 Multiply and accumulate - unsigned long
Syntax: UMLAL{cond}{S} RdLo, RdHi, Rm, Rs
Elements inside curly brackets are optional.
Usage: Multiples the values (as unsigned integers) in registers Rm and Rs and
adds the 64 bit product to the unsigned 64 bit value in registers RdLo (least
significant 32 bits) and RdHi (most significant 32 bits).
Condition flags: If S is specified then the N and Z flags are updated according
to the result and the V and C flags are unpredictable for the ARM7 and earlier
processors.
Example:
UMLAL r6, r5, r3, r9 ;multiply the values in r3 and r9 and add the product to
the values in r5 and r6
 Multiply - signed long
Syntax: SMULL{cond}{S} RdLo, RdHi, Rm, Rs

Elements inside curly brackets are optional.

Usage: Multiples the values (as two's complement signed integers) in registers
Rm and Rs and places the least significant 32 bits of the product in register
RdLo and the most significant 32 bits of the product in register RdHi.

Condition flags: If S is specified then the N and Z flags are updated according to
the result and the V and C flags are unpredictable for the ARM7 and earlier
processors.

Example:

SMULL r6, r5, r3, r9 ;multiply the values in r3 and r9 and places the result in r5
and r6
 Multiply and accumulate - signed long

Syntax: SMLAL{cond}{S} RdLo, RdHi, Rm, Rs

Elements inside curly brackets are optional.

Usage: Multiples the values (as two's complement signed integers) in registers Rm
and Rs and adds the 64 bit product to the two's complement signed 64 bit value in
registers RdLo (least significant 32 bits) and RdHi (most significant 32 bits).

Condition flags: If S is specified then the N and Z flags are updated according to the
result and the V and C flags are unpredictable for the ARM7 and earlier processors.

Example:

SMLAL r6, r5, r3, r9 ;multiply the values in r3 and r9 and add the product to the
values in r5 and r6
 Compare
Syntax: CMP{cond} Rn, Operand2

Elements inside curly brackets are optional.

Usage: Subtracts Operand2 from the value in Rn and updates the flags

accordingly. The result is discarded.

Condition flags: All flags are updated according to the result.

Examples:

CMP r1, #9 ;set the flags as if 9 was subtracted from the value in r1.

CMP r6, r2 ;set the flags for the result of (r6 - r2) but discard the result
 Compare negative
Syntax: CMN{cond} Rn, Operand2

Elements inside curly brackets are optional.

Usage: Add Operand2 to the value in Rn and updates the flags accordingly.
The result is discarded.

Condition flags: All flags are updated according to the result.

Examples:

CMN r1, #9 ;set the flags as if 9 was added to the value in r1.

CMN r6, r2 ;set the flags for the result of (r6 + r2) but discard the result
 Data Movement
• Operations are:

– MOV{cond}{S} Rn, Operand2

– MVN {cond}{S} Rn, operand2

(move the NOT of the 32-bit value into a register)

Note that these make no use of operand1.

• Syntax:

– <Operation>{<cond>}{S} Rd, Operand2

• Find the value in r0, r1, r2:

– MVNEQ r1,#02 r1=

– MOV r0, r1 r0=

– MOVS r2, #10 r2=

 Data Movement
• Operations are:
– MOV{cond}{S} Rn, Operand2

– MVN {cond}{S} Rn, operand2

(move the NOT of the 32-bit value into a register)

Note that these make no use of operand1.
• Syntax:
– <Operation>{<cond>}{S} Rd, Operand2

• Find the value in r0, r1, r2:

– MVNEQ r1,#02 r1=
– MOV r0, r1 r0=
– MOVS r2, #10 r2=
 Data Movement
• Operations are:
– MOV{cond}{S} Rn, Operand2

– MVN {cond}{S} Rn, operand2

(move the NOT of the 32-bit value into a register)

Note that these make no use of operand1.
• Syntax:
– <Operation>{<cond>}{S} Rd, Operand2

• Find the value in r0, r1, r2:

– MVNEQ r1,#02 r1= 0xfffffffd
– MOV r0, r1 r0=0xfffffffd
– MOVS r2, #10 r2=0x00000010
 Barrel Shifter - Left Shift
• Shifts left by the specified amount (multiplies
by powers of two) e.g.
LSL #5 = multiply by 32
MOV R0, R1, LSL #2
MOV R0, R1, LSL R2

CF Destination 0

Logical Shift Left (LSL)

 Barrel Shifter - Right Shifts
Logical Shift Right
• Shifts right by the specified
amount (divides by powers of Logical Shift Right
two) e.g.
LSR #5 = divide by 32 ...0 Destination CF
MOV R0, R1, LSR #2
MOV R0, R1, LSR R2
Arithmetic Shift Right
• Shifts right (divides by powers of Arithmetic Shift Right
two) and preserves the sign bit,
for 2's complement operations.
e.g. Destination CF

ASR #5 = divide by 32
MOV R0, R1, LSR #2 Sign bit shifted in
MOV R0, R1, LSR R2
 Barrel Shifter - Rotations
Rotate Right (ROR) Rotate Right
• Similar to an ASR
but the bits wrap around as CF
they leave the LSB and Destination
appear as the MSB.
e.g. ROR #5
• Note the last bit rotated is
also used as the Carry Out.

Rotate Right Extended (RRX)

Rotate Right through Carry
• This operation uses the
CPSR C flag as a 33rd bit.
• Rotates right by 1 bit. Destination CF
Encoded as RRX #0.
 Logical Instructions
• Logical instructions perform bitwise logical
operations on the two source registers.
• Syntax: <instruction>{<cond>}{S} Rd, Rn, N
• Elements inside curly brackets are optional
 Example
• This example shows a logical OR operation between registers
r1 and r2. r0 holds the result.

• ORR R0, R1, R2

• Pre-execution
• r0 = 0x00000000 , r1 = 0x02040608, r2 = 0x10305070
• Post-execution
• r0 = ?
 Example
• This example shows a more complicated logical
instruction called BIC, which carries out a logical bit clear.
• PRE
r1 = 0b1111
r2 = 0b0101
BIC r0, r1, r2
• POST
r0 = 0b1010
• This is equivalent to
Rd = Rn AND NOT(N)
 Example
• This example shows a logical OR operation between registers
r1 and r2. r0 holds the result.

• ORR R0, R1, R2

• Pre-execution
• r0 = 0x00000000 , r1 = 0x02040608, r2 = 0x10305070
• Post-execution
• r0 = 0x12345678
 Branch Instructions
• A branch instruction changes the flow of execution or is used to call a routine. This
type of instruction allows programs to have subroutines, if-then-else structures,
and loops.
• Syntax:
• B{<cond>} label
• BL{<cond>} label
• BX{<cond>} Rm
• BLX{<cond>} label | Rm
 Branch Instructions
Example of forward and backward unconditional branch

B forward
ADD r1, r2, #4
ADD r0, r6, #2
ADD r3, r7, #4
forward
SUB r1, r2, #4
backward
ADD r1, r2, #4
SUB r1, r2, #4
ADD r4, r6, r7
B backward
 Branch Instructions
The branch with link, or BL, instruction is similar to the B instruction but overwrites the
link register lr with a return address. It performs a subroutine call. This example shows
a simple fragment of code that branches to a subroutine using the BL instruction. To
return from a subroutine, you copy the link register to the pc.

BL subroutine ; branch to subroutine

CMP r1, #5 ; compare r1 with 5
MOVEQ r1, #0 ; if (r1==5) then r1 = 0
:
subroutine
<subroutine code>
MOV pc, lr ; return by moving pc = lr
 Load-Store Instructions
• Load-store instructions transfer data between
memory and processor registers. There are
three types of load-store instructions:
• Single-register transfer
• Multiple-register transfer,
• and Swap.
Single-Register Transfer
 Single-Register Transfer
• These instructions are used for moving a single
data item in and out of a register. The data types
supported are signed and unsigned words (32-
bit), half words (16-bit), and bytes.
• Here are the various load-store single-register
transfer instructions.
• Syntax: <LDR|STR>{<cond>}{B} Rd,addressing1
LDR{<cond>}SB/H/SH Rd, addressing2
STR{<cond>}H Rd, addressing2
 Single-Register Transfer
• LDR r0, [r1] ;r0 [r1, #0]
• LDR R0, [R1, #4] ; R0 [R1+ #4]
• LDR R0, [R1, R2] ;R0 [R1+R2]
• LDR R0, [R1, R2, LSL #2]
• Load the data from memory with address
[Sum of R1 and R2 with shift left by 2]
 Single-Register Transfer
• STR r0, [r1] ; r0 [r1, #0]
• STR r0, [r1] ; r0 [r1, #0]
• STR R0, [R1, #4] ; R0 [R1+ #4]
• STR R0, [R1, R2] ;R0 [R1+R2]
• STR R0, [R1, R2, LSL #2] ;
• Store to memory with address [Sum of R1 and
R2 with shift left by 2]
 Single-Register Transfer Examples
PRE:
r0 = 0x00000000
r1 = 0x00090000
mem32[0x00009000] = 0x01010101
mem32[0x00009004] = 0x02020202
• LDR r0, [r1, #4]!
Pre-indexing with write back:
• POST:
r0 =
r1 =
 Single-Register Transfer Examples
PRE:
r0 = 0x00000000
r1 = 0x00090000
mem32[0x00009000] = 0x01010101
mem32[0x00009004] = 0x02020202
• LDR r0, [r1, #4]!
Preindexing with writeback:
• POST:
r0 = 0x02020202
r1 = 0x00009004
 Single-Register Transfer Examples
PRE:
r0 = 0x00000000
r1 = 0x00090000
mem32[0x00009000] = 0x01010101
mem32[0x00009004] = 0x02020202
Preindexing:
LDR r0, [r1, #4]
• POST:
r0 = 0x02020202
r1 = 0x00009000
 Single-Register Transfer Examples
PRE:
r0 = 0x00000000
r1 = 0x00090000
mem32[0x00009000] = 0x01010101
mem32[0x00009004] = 0x02020202
LDR r0, [r1], #4
Postindexing:
• POST:
r0 = 0x01010101
r1 = 0x00009004
 Multiple-Register Transfer
• Load-store multiple instructions can transfer multiple
registers between memory and the processor in a single
instruction. The transfer occurs from a base address
register Rn pointing into memory. Multiple-register transfer
instructions are more efficient from single-register transfers
for moving blocks of data around memory and saving and
restoring context.
• Syntax: <LDM|STM>{<cond>}<addressing mode> Rn{!},<registers>{ˆ}
• LDMIA r0!, (r1-r3)
• STMIB r0!, (r1-r3)
Multiple-Register Transfer
Multiple-Register Transfer
Multiple-Register Transfer
 LDM<mode> R0!, {R1-R3}

Mode Start Address End Address Data Word Rn!=2010

IA 2010 2018 2010:R1 201C
2014: R2
2018: R3
IB 2010 201C 2014:R1 201C
2018: R2
201C: R3
IA 2008 2010 2008: R1 2004
200C: R2
2010: R3
IA 2004 20oC 2004: R1 2004
2008: R2
200C: R3
 Addressing Modes
• Immediate Addressing Mode
• Register Addressing Mode
• Offset Addressing
• Pre-Index Addressing
• Post-Index Addressing
 Immediate Addressing Mode
• When an immediate constant value is the part
of instruction.
• Example:
• MOV R0, #05
• ADD R0,R0, #07
• SUB R0,R0, #06
 Register Addressing Mode
• When the address of the data is specified by
the registers of processor.
• Example:
• MOV R0, R2
• ADD R0,R1, R2
• SUB R0,R1, R2
 Offset Addressing
• In this the data is to read/write to/from memory
and the offset addressing of the memory address
is formed by adding (or subtracting) an offset to or
from the value held in a base register.
• Examples:
1. LDR R0, [R1] (Constant Value)
2. LDR R0, [R1, #4] (Constant Value)
3. LDR R0, [R1, R2] (Register)
4. LDR R0, [R1, R2, LSL #2] (Scaled)
 Pre-Index Addressing
• In pre-index addressing the memory address if formed in the same way as
for offset addressing. The address is not only used to access memory, but
the base register is also modified to hold the new value. In the ARM
system this is known as a write-back and is denoted by placing a
exclamation mark after at the end of the (op2) code.

1. LDR R0, [R1, #4]! (Constant Value)

2. LDR R0, [R1, R2]! (Register)
3. LDR R0, [R1, R2, LSL #2]! (Scaled)
 Post-Index Addressing
• In post-index address the memory address is the base register
value. As a side-effect, an offset is added to or subtracted
from the base register value and the result is written back to
the base register.
• Example:
• LDR R0, [R1], #4
• LDR R0, [R1], R2
• LDR R0, [R1], R2, LSL #2
Find the one's compliment (inverse) of a
number
 Find the one's compliment (inverse) of a
number
AREA Program, CODE, READONLY
ENTRY
Main
LDR R1, Value ; Load the number to be complimented
MVN R1, R1 ; NOT the contents of R1
STR R1, Result ; Store the result
SWI &11

Value DCD &C123 ; Value to be complemented

Result DCD 0 ; Storage for result
END
Add two numbers
 Add two numbers
AREA Program, CODE, READONLY
ENTRY
Main
LDR R1, Value1 ; Load the first number
LDR R2, Value2 ; Load the second number
ADD R1, R1, R2 ; ADD them together into R1 (x = x + y)
STR R1, Result ; Store the result
SWI &11
Value1 DCD &37E3C123 ; First value to be added
Value2 DCD &367402AA ; Second value to be added
Result DCD 0 ; Storage for result
END
Add two numbers and store the result
 Add two numbers and store the result
AREA Program, CODE, READONLY
ENTRY
Main
LDR R0, =Value1 ; Load the address of first value
LDR R1, [R0] ; Load what is at that address
ADD R0, R0, #0x4 ; Adjust the pointer
LDR R2, [R0] ; Load what is at the new addr
ADD R1, R1, R2 ; ADD together
LDR R0, =Result ; Load the storage address
STR R1, [R0] ; Store the result
SWI &11 ; All done

Value1 DCD &37E3C123 ; First value

Value2 DCD &367402AA ; Second value
Result DCD 0 ; Space to store result
END
Find the larger of two numbers
 Find the larger of two numbers
AREA Program, CODE, READONLY
ENTRY
Main
LDR R1, Value1 ; Load the first value to be compared
LDR R2, Value2 ; Load the second value to be compared
CMP R1, R2 ; Compare them
BHI Done ; If R1 contains the highest
MOV R1, R2 ; otherwise overwrite R1
Done
STR R1, Result ; Store the result
SWI &11
Value1 DCD &12345678 ; Value to be compared
Value2 DCD &87654321 ; Value to be compared
Result DCD 0 ; Space to store result
END
Program: Addition of Two 64-bit Numbers
 Program: Addition of Two 64-bit Numbers
• Code:
AREA ADD_64BITNOS_PROGRAM, CODE
ENTRY
LDR R1, Value11 ; First number lower 32 bits
LDR R2, Value21 ; First number higher 32 Bits
LDR R3, Value12 ; Second number lower 32 Bits
LDR R4, Value22 ; Second number higher 32 Bits
ADDS R3, R3, R1 ; Add the lower order 32 bits of 2 nos.
ADC R4, R4, R2 ; Add the higher 32 bits along with previous carry.
Value11 DCD &062A7295
Value21 DCD &08594921
Value12 DCD &00101010
Value22 DCD &00010101
END
 64 bit addition with memory
AREA Program, CODE, READONLY
ENTRY
Main
LDR R0, =Value1 ; Pointer to first value
LDR R1, [R0] ; Load first part of value1
LDR R2, [R0, #4] ; Load lower part of value1
LDR R0, =Value2 ; Pointer to second value
LDR R3, [R0] ; Load upper part of value2
LDR R4, [R0, #4] ; Load lower part of value2
ADDS R6, R2, R4 ; Add lower 4 bytes and set carry flag
ADC R5, R1, R3 ; Add upper 4 bytes including carry
LDR R0, =Result ; Pointer to Result
STR R5, [R0] ; Store upper part of result
STR R6, [R0, #4] ; Store lower part of result
SWI &11
Value1 DCD &12A2E640, &F2100123 ; Value to be added
Value2 DCD &001019BF, &40023F51 ; Value to be added
Result DCD 0 ; Space to store result
END
 Add a series of 16 bit numbers
AREA Program, CODE, READONLY
ENTRY
Main
LDR R0, =Data1 ;load the address of the lookup table
EOR R1, R1, R1 ;clear R1 to store sum
LDR R2, Length ;init element count
Loop
LDR R3, [R0] ;get the data
ADD R1, R1, R3 ;add it to r1
ADD R0, R0, #+4 ;increment pointer
SUBS R2, R2, #0x1 ;decrement count with zero set
BNE Loop ;if zero flag is not set, loop
STR R1, Result ;otherwise done - store result
SWI &11

AREA Data1, DATA

Table DCW &2040 ;table of values to be added
ALIGN ;32 bit aligned
DCW &1C22
ALIGN
DCW &0242
ALIGN
TablEnd DCD 0
AREA Data2, DATA
Length DCW (TablEnd - Table) / 4 ;because we're having to align
ALIGN ;gives the loop count
Result DCW 0 ;storage for result
END
Scan a series of 16 bit numbers to find the largest
AREA Program, CODE, READONLY
ENTRY
Main
LDR R0, =Data1 ;load the address of the lookup table
EOR R1, R1, R1 ;clear R1 to store largest
LDR R2, Length ;init element count
CMP R2, #0
BEQ Done ;if table is empty
Loop
LDR R3, [R0] ;get the data
CMP R3, R1 ; bit is 1
BCC Looptest ;skip next line if zero
MOV R1, R3 ;increment -ve number count
Looptest
ADD R0, R0, #+4 ;increment pointer
SUBS R2, R2, #0x1 decrement count with zero set
BNE Loop ;if zero flag is not set, loop
Done
STR R1, Result ;otherwise done - store result
SWI &11

AREA Data1, DATA

Table DCW &A152 ;table of values to be tested
ALIGN DCW &7F61
ALIGN DCW &F123
ALIGN DCW &8000
ALIGN TablEnd DCD 0

• 38 AREA Data2, DATA

Length DCW (TablEnd - Table) / 4 ;because we're having to align
ALIGN ;gives the loop count
 Scan a series of 32 bit numbers to find how many are negative
AREA Program, CODE, READONLY
ENTRY
Main
LDR R0, =Data1 ; load the address of the lookup table
EOR R1, R1, R1 ;clear R1 to store count
LDR R2, Length ;init element count
CMP R2, #0
BEQ Done ;if table is empty
Loop
LDR R3, [R0] get the data
CMP R3, #0
BPL Looptest ;skip next line if +ve or zero
ADD R1, R1, #1 ;increment -ve number count
Looptest
ADD R0, R0, #+4 ;increment pointer
SUBS R2, R2, #0x1 ;decrement count with zero set
BNE Loop ;if zero flag is not set, loop
Done
STR R1, Result ;otherwise done - store result
SWI &11
AREA Data1, DATA
Table DCD &F1522040 ;table of values to be added
DCD &7F611C22
DCD &80000242
TablEnd DCD 0
AREA Data2, DATA
Length DCW (TablEnd - Table) / 4 ;because we're having to align
ALIGN ;gives the loop count
Result DCW 0 ;storage for result
 Scan a series of 16 bit numbers to nd how many are negative
AREA Program, CODE, READONLY
ENTRY
Main
LDR R0, =Data1 ;load the address of the lookup table
EOR R1, R1, R1 ;clear R1 to store count
LDR R2, Length ;init element count
CMP R2, #0
BEQ Done ;if table is empty
Loop
LDR R3, [R0] ;get the data
AND R3, R3, #0x8000 ;bit wise AND to see if the 16th
CMP R3, #0x8000 ;bit is 1
BEQ Looptest ;skip next line if zero
ADD R1, R1, #1 ;increment -ve number count
Looptest
ADD R0, R0, #+4 ;increment pointer
SUBS R2, R2, #0x1 ;decrement count with zero set
BNE Loop ;if zero flag is not set, loop
Done
STR R1, Result ;otherwise done - store result
SWI &11
AREA Data1, DATA
Table DCW &F152 ;table of values to be tested
ALIGN
DCW &7F61
ALIGN
DCW &8000
ALIGN
TablEnd DCD 0
AREA Data2, DATA
Length DCW (TablEnd - Table) / 4 ;because we're having to align
ALIGN ;gives the loop count
Result DCW 0 ;storage for result
END
 ARM Instruction Set Format
31 2827 1615 87 0 Instruction type
Cond 0 0 I Opcode S Rn Rd Operand2 Data processing / PSR Transfer
Cond 0 0 0 0 0 0 A S Rd Rn Rs 1 0 0 1 Rm Multiply
Cond 0 0 0 0 1 U A S RdHi RdLo Rs 1 0 0 1 Rm Long Multiply (v3M / v4 only)

Cond 0 0 0 1 0 B 0 0 Rn Rd 0 0 0 0 1 0 0 1 Rm
Swap
Load/Store Byte/Word
Cond 0 1 I P U B W L Rn Rd
Offset Load/Store Multiple
Cond 1 0 0 P U S W L Rn Register
List Halfword transfer : Immediate offset (v4 only)
Cond 0 0 0 P U 1 W L Rn Rd Offset1 1 S H 1 Offset2
Halfword transfer: Register offset (v4 only)
Cond 0 0 0 P U 0 W L Rn Rd 0 0 0 0 1 S H 1
Rm
Branch
Cond 1 0 1 L Offset Branch Exchange (v4T only)
Cond 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rn Coprocessor data transfer
Cond 1 1 0 P U N W L Rn CRd CPNum Offset Coprocessor data operation
Cond 1 1 1 0 Op1 CRn CRd CPNum Op2 0 CRm Coprocessor register transfer
Cond 1 1 1 0 Op1 L CRn Rd CPNum Op2 1 CRm Software interrupt
Cond 1 1 1 1 SWI Number
 Conditional Execution
• Most instruction sets only allow branches to be executed
conditionally.
• However by reusing the condition evaluation hardware, ARM
effectively increases number of instructions.
– All instructions contain a condition field which determines whether the
CPU will execute them.
– Non-executed instructions soak up 1 cycle.
• This removes the need for many branches, which stall the
pipeline (3 cycles to refill).
– Allows very dense in-line code, without branches.
– The Time penalty of not executing several conditional instructions is
frequently less than overhead of the branch or subroutine call that
would otherwise be needed.
 The Condition Field
31 28 24 20 16 12 8 4 0

Cond

0000 = EQ - Z set (equal) 1001 = LS - C clear or Z (set unsigned

0001 = NE - Z clear (not equal) lower or same)
0010 = HS / CS - C set (unsigned 1010 = GE - N set and V set, or N clear
higher or same) and V clear (>or =)
0011 = LO / CC - C clear (unsigned 1011 = LT - N set and V clear, or N clear
lower) and V set (>)
0100 = MI -N set (negative) 1100 = GT - Z clear, and either N set and
0101 = PL - N clear (positive or V set, or N clear and V set (>)
zero)
1101 = LE - Z set, or N set and V clear,or
0110 = VS - V set (overflow) N clear and V set (<, or =)
0111 = VC - V clear (no overflow) 1110 = AL - always
1000 = HI - C set and Z clear
(unsigned higher) 1111 = NV - reserved.
 Branch instructions
• Branch : B{<cond>} label
• Branch with Link : BL{<cond>} sub_routine_label

31 28 27 25 24 23 0

Cond 1 0 1 L Offset

Link bit 0 = Branch

1 = Branch with link
Condition field

• The offset for branch instructions is calculated by the assembler:

– By taking the difference between the branch instruction and the target
address minus 8 (to allow for the pipeline).
– This gives a 26 bit offset which is right shifted 2 bits (as the bottom two
bits are always zero as instructions are word – aligned) and stored into
the instruction encoding.
– This gives a range of ± 32 Mbytes.
 Data processing instructions
• The ARM data processing instructions are used to modify data values in registers.
The operations that are supported include arithmetic and bit-wise logical
combinations of 32-bit data types. One operand may be shifted or rotated en route
to the ALU, allowing, for example, shift and add in a single instruction.
ADD{cond}{S} Rd, Rn, Operand2
Data processing instructions
 Multiply
• MUL{cond}{S} Rd, Rm, Rs
• MLA{cond}{S} Rd, Rm, Rs, Rn
 Load/Store
• LDR|STR {<cond>}{B} Rd,addressing1
LDR{<cond>}SB/H/SH Rd, addressing2
LDR R0, [R1]
LDR R0, [R1, R2, LSL #2]
 Load/Store Multiple registers
• Syntax: <LDM|STM>{<cond>}<addressing mode> Rn{!},<registers>{ˆ}
• LDMIA r0!, (r1-r3)
• STMIB r0!, (r1-r3)