PowerPoint Slides

Computer Organisation and Architecture

Smruti Ranjan Sarangi,
IIT Delhi

Chapter 4 ARM Assembly Language

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 ARM Assembly Language

* One of the most popular RISC instruction

sets in use today
* Used by licensees of ARM Limited, UK
* ARM processors
* Some processors by Samsung, Qualcomm, and Apple

* Highly versatile instruction set

* Floating-point and vector (multiple operations per
instruction) extensions

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 Outline

* Basic Instructions

* Advanced Instructions

* Branch Instructions

* Memory Instructions

* Instruction Encoding

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 ARM Machine Model
* 16 registers – r0 … r15
* The PC is explicitly visible

* Memory (Von Neumann Architecture)

Register Abbrv. Name

r11 fp frame pointer
r12 ip intra-procedure-call scratch register
r13 sp stack pointer
r14 lr link register
r15 pc program counter

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Data Transfer Instructions

Semantics Example Explanation

mov r1, r2 r1 ← r2
mov reg, (reg/imm)
mov r1, #3 r1 ← 3
mvn r1, r2 r1 ← ∼ r2
mvn reg, (reg/imm)
mvn r1, #3 r1 ← ∼ 3

* mov and mvn (move not)

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 Arithmetic Instructions

Semantics Example Explanation

add reg, reg, (reg/imm) add r1, r2, r3 r1 ← r2 + r3
sub reg, reg, (reg/imm) sub r1, r2, r3 r1 ← r2 - r3
rsb reg, reg, (reg/imm) rsb r1, r2, r3 r1 ← r3 - r2

* add, sub, rsb (reverse subtract)

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 Example

Write an ARM assembly program to compute: 4+5 - 19. Save the result in
r1.

Answer: Simple yet suboptimal solution.

mov r1, #4
mov r2, #5
add r3, r1, r2
mov r4, #19
sub r1, r3, r4

Optimal solution.

mov r1, #4
add r1, r1, #5
sub r1, r1, #19

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 Logical Instructions

Semantics Example Explanation

and reg, reg, (reg/imm) and r1, r2, r3 r1 ← r2 AND r3
eor reg, reg, (reg/imm) eor r1, r2, r3 r1 ← r2 XOR r3
orr reg, reg, (reg/imm) orr r1, r2, r3 r1 ← r2 OR r3
bic reg, reg, (reg/imm) bic r1, r2, r3 r1 ← r2 AND (∼ r3)

* and, eor (exclusive or), orr (or), bic(bit

clear)

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 Example

Write an ARM assembly program to compute:, where A and B are

1 bit Boolean values. Assume that A = 0 and B = 1. Save the result
in r0.

Answer:

mov r0, #0x0

orr r0, r0, #0x1
mvn r0, r0

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 Multiplication Instruction

Semantics Example Explanation

mul reg, reg, (reg/imm) mul r1, r2, r3 r1 ← r2 × r3
mla reg, reg, reg, reg mla r1, r2, r3, r4 r1 ← r2 × r3 + r4
smull reg, reg, reg, reg smull r0, r1, r2, r3 r1 r0← r2 ×signed r3
64
umull reg, reg, reg, reg umull r0, r1, r2, r3 r1 r0← r2 ×unsigned r3
64

* smull and umull instructions can hold a

64 bit operand

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 Example

Compute 123 + 1, and save the result in r3.

Answer:
/* load test values */
mov r0, #12
mov r1, #1

/* perform the logical computation */

mul r4, r0, r0 @ 12*12
mla r3, r4, r0, r1 @ 12*12*12 + 1

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 Outline

* Basic Instructions

* Advanced Instructions

* Branch Instructions

* Memory Instructions

* Instruction Encoding

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 Shifter Operands

Generic format
reg1 lsl #shift_amt
, lsr reg2
asr
ror
Examples

0 1 1 00
lsl #1
1 0 1 10
0 1 0 11
lsr #1
1 0 1 10
1 1 0 11
asr #1
1 0 1 10
0 1 0 11
ror #1
1 0 1 10
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Examples of Shifter Operands
Write ARM assembly code to compute: r1 = r2 / 4.

Answer:
mov r1, r2, asr #2

Write ARM assembly code to compute: r1 = r2 + r3 × 4.

Answer:
add r1, r2, r3, lsl #2

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 Compare Instructions

Semantics Example Explanation

cmp reg, (reg/imm) cmp r1, r2 Set flags after computing (r1 - r2)
cmn reg, (reg/imm) cmn r1, r2 Set flags after computing (r1 + r2)
tst reg, (reg/imm) tst r1, r2 Set flags after computing (r1 AND r2)
teq reg, (reg/imm) teq r1, r2 Set flags after computing (r1 XOR r2)

* Sets the flags of the CPSR register

* CPSR (Current Program Status Register)
* N (negative) , Z (zero), C (carry), F (overflow)
* If we need to borrow a bit in a subtraction, we set C
to 0, otherwise we set it to 1.
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 Instructions with the 's' suffix
* Compare instructions are not the only
instructions that set the flags.
* We can add an s suffix to regular ALU
instructions to set the flags.
* An instruction with the 's' suffix sets the flags in the
CPSR register.
* adds (add and set the flags)
* subs (subtract and set the flags)

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Instructions that use the Flags

Semantics Example Explanation

adc reg, reg, reg adc r1, r2, r3 r1 = r2 + r3 + Carry Flag
sbc reg, reg, reg sbc r1, r2, r3 r1 = r2 - r3 - NOT(Carry Flag)
rsc reg, reg, reg rsc r1, r2, r3 r1 = r3 - r2 - NOT(Carry Flag))

* add and subtract instructions that use the

value of the carry flag

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64 bit addition using 32 bit registers

Add two long values stored in r2,r1 and r4,r3.

Answer:
adds r5, r1, r3
adc r6, r2, r4

The (adds) instruction adds the values in r1 and r3. adc(add with carry) adds
r2, r4, and the value of the carry flag. This is exactly the same as normal
addition.

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 Outline

* Basic Instructions

* Advanced Instructions

* Branch Instructions

* Memory Instructions

* Instruction Encoding

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 Simple Branch Instructions

Semantics Example Explanation

b label b .foo Jump unconditionally to label .foo
beq label beq .foo Branch to .foo if the last flag setting
instruction has resulted in an equality
and (Z flag is 1)
bne label bne .foo Branch to .foo if the last flag setting
instruction has resulted in an inequality
and (Z flag is 0)

* b (unconditional branch)
* b<code> (conditional branch)
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 Branch Conditions
Number Suffix Meaning Flag State
0 eq equal Z=1
1 ne notequal Z=0
2 cs/hs carry set/ unsigned higher or equal C=1
3 cc/lo carry clear/ unsigned lower C=0
4 mi negative/ minus N=1
5 pl positive or zero/ plus N=0
6 vs overflow V=1
7 vc no overflow V=0
8 hi unsigned higher (C = 1) ∧ (Z = 0)
9 ls unsigned lower or equal (C = 0) ∨ (Z = 1)
10 ge signed greater than or equal N=0
11 lt signed less than N=1
12 gt signed greater than (Z = 0) ∧ ( N = 0)
13 le signed less than or equal (Z = 1) ∨ (N = 1)
14 al always
15 – reserved
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 Example
Write an ARM assembly program to compute the factorial of a positive
number (> 1) stored in r0. Save the result in r1.

Answer:

ARM assembly
mov r1, #1 /* prod = 1 */
mov r3, #1 /* idx = 1 */
.loop:
mul r1, r3, r1 /* prod = prod * idx */
cmp r3, r0 /* compare idx, with the input (num) */
add r3, r3, #1 /* idx ++ */
bne .loop /* loop condition */

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 Branch and Link Instruction

Semantics Example Explanation

bl label bl .foo (1) Jump unconditionally to the function at .foo
(2) Save the next PC (PC + 4) in the lr register

* We use the bl instruction for a function call

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 Example

Example of an assembly program with a function call.

ARM assembly
C foo:
int foo() { mov r0, #2
return 2; mov pc, lr
}
void main() { main:
int x = 3; mov r1, #3 /* x = 3 */
int y = x + foo(); bl foo /* invoke foo */
} /* y = x + foo() */
add r2, r0, r1

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 The bx Instruction
Semantics Example Explanation
bx reg bx r2 (1) Jump unconditionally to the address
contained in register, r2

* This is the preferred method to return from

a function.
* Instead of : mov pc, lr
Use : bx lr

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 Example

foo:
mov r0, #2
bx lr

main:
mov r1, #3 /* x = 3 */
bl foo /* invoke foo */
/* y = x + foo() */
add r2, r0, r1

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Conditional Variants of Normal Instructions

* Normal Instruction + <condition>

* Examples : addeq, subne, addmi, subpl

* Also known as predicated instructions

* If the condition is true
* Execute instruction normally

* Otherwise
* Do not execute at all

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Write a program in ARM assembly to count the number of 1s in a 32 bit number stored in r1. Save
the result in r4.
Answer:

mov r2, #1 /* idx = 1 */

mov r4, #0 /* count = 0 */
/* start the iterations */
.loop:
/* extract the LSB and compare */
and r3, r1, #1
cmp r3, #1

/* increment the counter */

addeq r4, r4, #1

/* prepare for the next iteration */

mov r1, r1, lsr #1
add r2, r2, #1

/* loop condition */
cmp r2, #32
ble .loop

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 Outline
* Basic Instructions

* Advanced Instructions

* Branch Instructions

* Memory Instructions

* Instruction Encoding

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 Basic Load Instruction
●
ldr r1, [r0]
ldr r1, [r0]
memory
register
file
r0
r1

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 Basic Store Instruction
●
str r1, [r0]
str r1, [r0]
memory
register
file
r0
r1

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Memory Instructions with an Offset

* ldr r1, [r0, #4]

* r1 ← mem[r0 + 4]

* ldr r1, [r0, r2]

* r1 ← mem[r0 + r2]

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 Table of Load/Store Instructions

Semantics Example Explanation Addressing Mode

ldr reg, [reg] ldr r1, [r0] r1 ← [r0] register-indirect
ldr reg, [reg, imm] ldr r1, [r0, #4] r1 ← [r0 + 4] base-offset
ldr reg, [reg, reg] ldr r1, [r0, r2] r1 ← [r0 + r2] base-index
ldr reg, [reg, reg, shift imm] ldr r1, [r0, r2, lsl #2] r1 ← [r0 + r2 << 2] base-scaled-index
str reg, [reg] str r1, [r0] [r0] ← r1 register-indirect
str reg, [reg, imm] str r1, [r0, #4] [r0 + 4] ← r1 base-offset
str reg, [reg, reg] str r1, [r0, r2] [r0 + r2] ← r1 base-index
str reg, [reg, reg, shift imm] str r1, [r0, r2, lsl #2] [r0 + r2 << 2] ← r1 base-scaled-index

* Note the base-scaled-index addressing mode

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 Example with Arrays
C
void addNumbers(int a[100]) {
int idx;
int sum = 0;
for (idx = 0; idx < 100; idx++){
sum = sum + a[idx];
}
}
Answer:
ARM assembly
/* base address of array a in r0 */
mov r1, #0 /* sum = 0 */
mov r2, #0 /* idx = 0 */

.loop:
ldr r3, [r0, r2, lsl #2]
add r2, r2, #1 /* idx ++ */
add r1, r1, r3 /* sum += a[idx] */
cmp r2, #100 /* loop condition */
bne .loop
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Advanced Memory Instructions

* Consider an array access again

* ldr r3, [r0, r2, lsl #2] /* access array */
* add r2, r2, #1 /* increment index */
* Can we fuse both into one instruction
* ldr r3, [r0], r2, lsl #2
* Equivalent to :
* r3 = [r0] Post-indexed addressing
mode
* r0 = r0 + r2 << 2

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Pre-Indexed Addressing Mode
* Consider
* ldr r0, [r1, #4]!

* This is equivalent to:

* r0  mem [r1 + 4]
* r1  r1 + 4

Similar to i++ and ++i in Java/C/C++

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 Example with Arrays
C
void addNumbers(int a[100]) {
int idx;
int sum = 0;
for (idx = 0; idx < 100; idx++){
sum = sum + a[idx];
}
}
Answer:
ARM assembly
/* base address of array a in r0 */
mov r1, #0 /* sum = 0 */
add r4, r0, #400 /* set r4 to address of a[100] */

.loop:
ldr r3, [r0], #4
add r1, r1, r3 /* sum += a[idx] */
cmp r0, r4 /* loop condition */
bne .loop

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 Memory Instructions in Functions

Instruction Semantics
ldmfd sp!, {list of registers } Pop the stack and assign values to registers
in ascending order. Update sp.

stmfd sp!, {list of registers } Push the registers on the stack in descending
order. Update sp.

* stmfd → spill a set of registers

* ldmfd → restore a set of registers

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 Example
Write a function in C and implement it in ARM assembly to compute x n,
where x and n are natural numbers. Assume that x is passed through r0, n
through r1, and the return value is passed back to the original program via
r0. Answer:
ARM assembly
power:
cmp r1, #0 /* compare n with 0 */
moveq r0, #1 /* return 1 */
bxeq lr /* return */

stmfd sp!, {r4, lr} /* save r4 and lr */

mov r4, r0 /* save x in r4 */
sub r1, r1, #1 /* n = n - 1 */
bl power /* recursively call power */
mul r0, r4, r0 /* power(x,n) = x * power(x,n-1) */
ldmfd sp!, {r4, pc} /* restore r4 and return */

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 Outline

* Basic Instructions

* Advanced Instructions

* Branch Instructions

* Memory Instructions

* Instruction Encoding

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 Generic Format

* Generic Format
4 2

cond type
32 29 28 27

* cond → instruction condition (eq, ne, … )

* type → instruction type

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 Data Processing Instructions

4 2 4 4 4 12
cond 00 I opcode S rs rd shifter operand/
32 29 28 27 26 25 22 21 20 17 16 13 immediate
12 1

* Data processing instruction type : 00

* I → Immediate bit
* opcode → Instruction code
* S → 'S' suffix bit (for setting the CPSR flags)
* rs, rd → source register, destination register
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Encoding Immediate Values
* ARM has 12 bits for immediates
* 12 bits

* What do we do with 12 bits ?

* It is not 1 byte, nor is it 2 bytes

* Let us divide 12 bits into two parts

* 8 bit payload + 4 bit rot
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 Encoding Immediates - II
* The real value of the immediate is equal
to : payload ror (2 * rot)
4 8

rot payload

* The programmer/ compiler writes an assembly

instruction with an immediate: e.g. 4
* The assembler converts it in to a 12 bit format
(if it is possible to do so)
* The processor expands 12 bits → 32 bits
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 Encoding Immediates - III

* Explanation of encoding the immediate in

lay man's terms
* The payload is an 8 bit quantity
* A number is a 32 bit quantity.
* We can set 8 contiguous bits in the 32 bit number while
specifying an immediate
* The starting point of this sequence of bits needs to be
an even number such as 0, 2, 4, ...

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 Examples
Encode the decimal number 42.

Answer:
42 in the hex format is 0x2A, or alternatively 0x 00
00 00 2A. There is no right rotation involved. Hence,
the immediate field is 0x02A.

Encode the number 0x2A 00 00 00.

Answer:
The number is obtained by right rotating 0x2A by 8
places. Note that we need to right rotate by 4 places
for moving a hex digit one position to the right. We
need to now divide 8 by 2 to get 4. Thus, the
encoding of the immediate: 0x42A

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Encoding the Shifter Operand

5 2 4
shift imm shift type 0 rt
Shift type
12 8 7 6 5 4 1
lsl 00
(a)
4 2 4 lsr 01
asr 10
shift reg shift type 1 rt ror 11
12 9 8 7 6 5 4 1
(b) (c)

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 Load/Store Instructions
4 2 6 4 4 12

cond 0 1 I P UBWL rs rd shifter operand/

32 29 28 27 20 17 16 13 immediate
12 1

* Memory instruction type : 01

* rs, rd, shifter operand
* Connotation remains the same
* Immediates are not in (rot + payload format) :
They are standard 12 bit unsigned numbers

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 I, P, U, B, W, and L bits
Bit Value Semantics
0 last 12 bits represent an immediate value
I
1 last 12 bits represent a shifter operand
0 post-indexed addressing
P
1 pre-indexed addressing
0 subtract offset from base
U
1 add offset to base
0 transfer word
B
1 transfer byte
0 do not use pre or post indexed addressing
W
1 use pre or post indexed addressing
0 store to memory
L
1 load from memory
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 Branch Instructions
4 3 24

cond 101 L offset

32 29 28 26 25 24 1

* L bit → Link bit

* offset → branch offset (in number of
words, similar to SimpleRisc)

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 Branch Instructions - II
* What does the processor do
* Expands the offset to 32 bits (with proper sign
extensions)
* Shifts it to the left by 2 bits (because offset is in
terms of memory words)
* Adds it to PC + 8 to generate the branch target

* Why, PC + 8 ?
* Read chapter 9

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THE END

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