Chapter: Memory Management

Memory
 Memory
Computer has 2 types of memory:

a) Main Memory: temporarily stores data and instructions

executed by the computer. CPU retrieve instructions from
main memory and executes it.

b) Secondary Memory: directly is not accessed by CPU. It is

an external storage.
 Address Binding
Address Binding: Assigning an address to data or
instruction.

Address binding is a process of generating address where the

data/instruction is to be stored in memory.

3 types of address binding:

1. Compile time binding

2. Load time binding
3. Run time binding
 Address Binding
Address Binding: Fixing a physical address to the logical address
of a process address space

Compile time binding: it is known to compiler at compile time

where a program will reside in physical memory (Main Mem.)

Load time binding: if program location in memory is unknown until

run-time.

Execution/Run time binding: If the process can be moved during

its execution from one memory segment to another, then binding
must be delayed until run time. The absolute addresses are
generated by hardware.
 Address Space of process
•Make sure that each process has a separate memory space.

•Separate per-process memory space protects the processes from

each other.

•To separate memory spaces, we need the ability to determine the

range of legal addresses that the process may access and to
ensure that the process can access only these legal addresses.
 Address Space of process
We can provide this protection
by using two registers, usually a
base and a limit

Base register holds the smallest

legal physical memory address

Limit register specifies the size

of the range.
e.g. For example, if the base register
holds 300040 and the limit register is
120900, then the program can legally
access all addresses from 300040
through 420939 (inclusive)
 Protection

Protection of memory space is accomplished by having the

CPU hardware compare every address generated in user mode
with the registers.

Any attempt by a program executing in user mode to access

operating-system memory or other users’ memory results in
a trap to the operating system
 Protection

Base register and limit registers can only be updated by OS in kernel

mode.
 Logical and Physical Address Space
1. Logical Address or Virtual address:
a. The address generated by CPU.
b. Logical address is address of instruction / data as used by
program at some time.

Set of all logical address generated by program is Logical

address space
 Logical and Physical Address Space
2. Physical Address:
a. It is the address used seen by memory management unit
(MMU).
b. It refers to actual location in the main memory.
c. The user can never view physical address of program

Set of all logical address that a process actually occupies is Physical

address space

The logical address is used like a reference, to access the

physical address

MMU is used to map logical and physical addresses.

Logical and Physical Address Space
 Swapping
Technique of removing a process from main memory and storing it
into secondary memory, then bringing it back into main memory
for continued execution.

It is a technique used in multiprogramming environments which

have limited memory capacity.

Action of moving process out of main memory is called Swap Out

Action of moving process into main memory is called Swap In

Area on the disk where swapped out process are stored is

known as Swap Space.
 Swapping
During Swap-Out foll.
Things are checked:
While in Main Memory was
user program modified?
Yes: write it back to Sec.
Memory

No: Sec. Memory already has

a copy of it, no need to
write.
Overwrite J3 with new
program. I.e bring new
program
Contiguous File Allocation

Relocation Register contains base address of the process

Partitions
P1 needs 10mb space
P2 needs 30mb space
P3 needs 20mb space
P1 finishes its execution P4 need 25mb
So space is free

Free
P3 finishes its execution P5 require 25Mb space
So space is free
Partition Allocation
One method of allocating contiguous memory is to divide all available
memory into equal sized partitions, and to assign each process
to their own partition.

Partition Allocation
Algorithms:

a) First Fit:
– Checks all partitions
serially
– When partition with size
= or > encounters, it is
allocated for storage.
Partition Allocation Algorithms
b) Best Fit: This approach will check all the free partitions and
will allocate that free partition to a process which leads to
minimum internal fragmentation.

Disadvantage:
1) Complexity is more
2) Overhead to check all the partitions to find best suitable
space

c) Worst Fit: Allocate the largest memory hole

Memory Allocation - Example

Given 3 free memory partitions of 10KB, 20 KB and 15KB ( in

order) How would each of the first-fit, best- fit and worst fir
algorithms place processes of 15KB, 10KB, 20KB and 5KB (in
order)
Memory Allocation - Example
For 15KB
Memory Allocation - Example
For 10KB
Memory Allocation - Example
For 20KB
Memory Allocation - Example
For 5KB
Memory Allocation - Example
Memory Allocation - Example

Requests from processes are 300K,25K,125K,50K.

Two memory partitions are 150K and 350K.
Which one is best fo this:
(a)First Fit
(b) Best Fit
(c) Worst Fit
Paging / Paged Memory Management
– Paging is a memory management scheme that allows
processe’s physical memory to be discontinuous, and
eliminates problems with fragmentation by allocating
memory in equal sized blocks known as pages.
Paging / Paged Memory Management

– Every process is divided in to number of pages

– Memory is divided into partitions whose size is same as page
size : frames
– Each frame has frame no.
– Page size is same as frame size
– Put any page in any free frame
– Paging allows non-contiguous memory allocation
– Page numbers, frame numbers and frame sizes are
determined by the machine architecture
– Paging leads to Internal Fragmentation
Pages size and Frame size is always in powers of two
Paging / Paged Memory Management

– CPU generates logical address and put the pages into

random frames

– Mapping is required to map which page is stored in which

page number

– From frame no. physical address could be found

Paging / Paged Memory Management

– Physical address space of a process in non- contiguous

– Implementation:
• Frames: Fixed sized blocks of the physical memory
• Pages: Fixed sized slots of the logical memory
– When a process is to be executed, its pages are loaded into
any available memory frames.
– Page Table: is a data structure. Used to translate logical
address to physical address
– CPU generated logical addresses to fetch the instructions.
Address Translation
– Address generated by CPU is divided into:

a) Page Number (p): used as an index into page table, which

contains base address of each page in the physical memory.

b) Page Offset (d): combined with base address to define

physical memory address that is sent to the memory unit.
Actual address of any byte in page or frame (Position of
instruction in page or frame)

• Address of physical memory, where page resides.

• The number of bits in the offset determines the maximum size of
each page, and should correspond to the system frame size.
Address Translation
Address Translation
Address Translation
How to break logical address into page number and page
offset?

Physical Address= frame x page size + offset

Example
Q. Using a page size of 4 bytes and physical memory of 32 bytes,
find the physical address if logical address is:
a) 4
b) 10
Solution:
Example- Page Table
Hardware Support: for Page Table
Implementation
 Each operating system has its own methods for storing page tables.

Some allocate a page table for each process. A pointer to the page
table is stored with the other register values (like the instruction
counter) in the process control block.

When the dispatcher is told to start a process, it must reload the

user registers and define the correct hardware page-table values from
the stored user page table.
Hardware Support: for Page Table
Implementation
Each operating system has its own methods for storing
page tables.
– Some allocate page table for each process
– Pointer to page table is stored with other register values (e.g.
instruction pointer) in PCB.
– When dispatcher starts a process, It:
• Reload user register
• Define correct hardware page table value from stored user table

Page lookups must be done for every memory reference,

and whenever a process gets swapped in or out of the
CPU, its page table must be swapped, along with the
instruction registers.
Hardware Support: for Page Table
Implementation
Hardware implementation of page table: Methods:
1. Use Registers
– One option is to use a set of registers for the page
table
– The use of registers for the page table is satisfactory
if the page table is reasonably small (for example,
256 entries).
– Most contemporary computers, however, allow the page
table to be very large (for example, 1 million entries).
– The use of fast registers to implement the page table is
not feasible.
Hardware Support: for Page Table
Implementation
2. An alternate option is to:

– Store the page table in main memory, and to use a

single register ( called the page-table base register,
PTBR ) to record where in memory the page table is
located.
– Process switching is fast, because only the single
register needs to be changed.
– The address of a page table in memory is pointed by:
page table base register
Hardware Support: for Page Table
Implementation
The problem with this approach is the time required to
access a user memory location.
 If we want to access location i, we must first index into
the page table, using the value in the PTBR offset by the page
number for i.
This task requires a memory access. It provides us with the
frame number, which is combined with the page offset to
produce the actual address.

Two memory accesses

are needed to access a byte (one for the page-table entry, one
for the byte). Thus, memory access is slowed by a factor of 2.
Hardware Support: for Page Table
Implementation
– Solution to two memory accesses:
– Use a very special high-speed memory device called
the translation look-aside buffer, TLB.
– Each entry in the TLB consists of two parts:
– a key (or tag) and a value.
– When the associative memory is presented with an item, the
item is compared with all keys simultaneously.
– If the item is found, the corresponding value field is returned.
– The benefit of the TLB is that it can search an entire table for
a key value in parallel, and if it is found anywhere in the table,
then the corresponding lookup value is returned.
Hardware Support: for Page Table
Implementation

– TLB is not large enough to hold the entire page table.

– So used as a cache device.
– The percentage of time that the desired information is found
in the TLB is termed the hit ratio.
– The percentage of time that the desired information is not
found in the TLB is termed the miss ratio.
Paging hardware with TLB
Example

– 40% slowdown to get the frame

Effective access time = hit ratio x time taken for TLB hit +
miss ratio x time taken for TLB miss
Example

Explanation:
- TLB hit takes 120 nanoseconds total ( 20 to find the
frame number and then another 100 to go get the data )
- TLB miss takes 220 ( 20 to search the TLB, 100 to go
get the frame number, and then another 100 to go get
the data.

- Effective access time = hit ratio x time taken for TLB

hit + miss ratio x time taken for TLB miss
Problem
Memory Protection
• It is accomplished by Protection Bits associated with each frame
→ Valid – Invalid Bit
• These bits are kept in page table
• Every reference to the memory goes through page table and finds
correct frame number.
• When bit is set to valid: indicates that associated page is in
process's logical address space and is valid page.
• When bit is set to invalid: indicates that associated page is not
in process's logical address space and is invalid page.
Memory Protection
Segmentation
• It is a memory management scheme in which the memory
allocated to the process is non contiguous
• Logical address space is divided into number of small blocks
called segments
• Segments are of variable sized.

A C compiler might create separate segments for the following:

1. The code
2. Global variables
3. The heap, from which memory is allocated
4. The stacks used by each thread
5. The standard C library
Segmentation
• Users view memory as a collection of variable size segments.
With no necessary ordering of these segments

• Segmentation is memory-management scheme that supports user

view of memory

• A program is a collection of segments. A segment is a logical unit

such as:
main program, function, object, local variables, global
variables, data structures : stack, symbol table, arrays
User’s View of a Program
Logical View of Segmentation

1
4
1
2

3 2
4
3

user space memory space

Segmentation Architecture
• Each segment has a name and its length.
• Logical address consists of a two tuple:
<segment-number, offset>,
• Segment table – maps physical addresses; each table entry has:
– base – contains the starting physical address where the
segments reside in memory
– limit – specifies the length of the segment
• Segment-table base register (STBR) points to the segment
table’s location in memory
• Segment-table length register (STLR) indicates number of
segments used by a program;
segment number s is legal if s < STLR
Address Translation: Segmentation Hardware
Problems
Q1.if Segment 2 is 400 bytes long and begins at location 4300,
then a reference to byte 53 of segment 2 is mapped onto
location?
Ans: base address: 4300
Limit: 400
53<400 (I.e limit)
4300+53=4353.