UNIT III-Sequential Circuits

Sequential Circuits
• Sequential circuit consists of a combinational circuit
to which storage elements are connected to form a
feedback path.
• The storage elements are devices capable of storing
binary information.
• The binary information stored in these elements at
any given time defines the state of the sequential
circuit at that time.
• The sequential circuit receives binary information
from external inputs that, together with the
present state of the storage elements, determine
the binary value of the outputs.
• These external inputs also determine the condition
for changing the state in the storage elements.
• The outputs in a sequential circuit are a
function not only of the inputs, but
also of the present state of the storage
elements.
• The next state of the storage elements
is also a function of external inputs and
the present state.
• Thus, a sequential circuit is specified by
a time sequence of inputs, outputs,
and internal states.
 Types of Sequential Circuits
Synchronous Sequential Circuits
 employs signals that affect the storage elements at
only discrete instants of time.
 Synchronization is achieved by a timing device called a
clock generator, which provides a clock signal having
the form of a periodic train of clock pulses.
Asynchronous Sequential Circuits
• The behavior of an asynchronous sequential circuit
depends upon the input signals at any instant of time
and the order in which the inputs change.
• The storage elements commonly used in
asynchronous sequential circuits are time-delay
devices
Synchronous clocked sequential circuit
S T O R A G E E L E M E N T S : L AT C H E S
• A storage element in a digital circuit can maintain a binary state
indefinitely (as long as power is delivered to the circuit), until
directed by an input signal to switch states.
• The major differences among various types of storage elements are
in the number of inputs they possess and in the manner in which
the inputs affect the binary state.
• Storage elements that operate with signal levels (rather than signal
transitions) are referred to as latches ; those controlled by a clock
transition are flip-flops.
• Latches are said to be level sensitive devices; flip-flops are edge-
sensitive devices.
• Latches are the basic circuits from which all flip-flops are
constructed.
• Latches are useful for storing binary information in the
asynchronous sequential circuits.
• Flip-flops are used as storage elements in synchronous sequential
 SR Latch
• The SR latch is a circuit with two cross-coupled
NOR gates or two cross-coupled NAND gates,
and two inputs labeled S for set and R for
reset.
• The latch has two useful states. When output
Q=1 and Q’=0, the latch is said to be in the set
state .
• When Q = 0 and Q’ = 1, it is in the reset state.
• Outputs Q and Q’ are normally the
complement of each other.
SR latch with NOR gates
SR latch with NAND gates
SR Latch with Control Input
D Latch (Transparent Latch)
Graphic Symbols for Latches
Clock Response in Latch and Flip-flop
Master–slave D Flip-flop
 Construction of a D flip-flop with two D latches and an inverter is shown.
 The first latch is called the master and the second the slave.
 The circuit samples the D input and changes its output Q only at the negative
edge of the clock pulse (designated as Clk ).
 When the clock is 0, the output of the inverter is 1. The slave latch is
enabled, and its output Q is equal to the master output Y .
 The master latch is disabled because Clk = 0. When the input pulse changes
to the logic-1 level, the data from the external D input are transferred to the
master.
 The slave, however, is disabled as long as the clock remains at the 1 level,
because its enable input is equal to 0.
 Any change in the input changes the master output at Y, but cannot affect
the slave output.
 When the clock pulse returns to 0, the master is disabled and is isolated from
the D input.
 Now, the slave is enabled and the value of Y is transferred to the output of
the flip-flop at Q .
 Thus, a change in the output of the flip-flop can be triggered only during the
transition of the clock from 1 to 0.
D-type Positive-edge-triggered Flip-flop
• Construction of an edge-triggered D flip-flop using three SR
latches.
• Two latches respond to the external D (data) and Clk (clock)
inputs.
• The third latch provides the outputs for the flip-flop.
• The S and R inputs of the output latch are maintained at the logic-
1 level when Clk = 0. This causes the output to remain in its
present state. Input D may be equal to 0 or 1.
• If D = 0, when Clk becomes 1, R changes to 0.
• This causes the flip-flop to go to the reset state, making Q = 0.
• If there is a change in the D input while Clk = 1, terminal R
remains at 0 because Q is 0. Thus, the flip-flop is locked out and is
unresponsive to further changes in the input.
• When the clock returns to 0, R goes to 1, placing the output latch
in the quiescent condition without changing the output.
• Similarly, if D = 1 when Clk goes from 0 to 1, S changes to 0.
• This causes the circuit to go to the set state, making Q = 1.
• Any change in D while Clk = 1 does not affect the output.
Graphic Symbol for Edge-triggered
D Flip-flop
JK Flip-flop
T Flip-flop
Characteristic Tables
Flip-flop with Direct Input
Graphic Symbol and Function Table

R Clk D Q Q’
0 X X 0 1
1 0 0 1
1 1 1 0
 Analysis of Clocked Sequential Circuits
 Analysis describes what a given circuit will do under
certain operating conditions.
 The behavior of a clocked sequential circuit is
determined from the inputs, the outputs, and the
state of its flip-flops.
 The outputs and the next state are both a function of
the inputs and the present state.
 The analysis of a sequential circuit consists of
obtaining a table or a diagram for the time sequence
of inputs, outputs, and internal states.
 The behaviour of a sequential circuit can be
described with a State Equation, State Table and
State Diagram
Example Sequential Circuit
 State Equation
 The behavior of a clocked sequential circuit can
be described algebraically by means of state
equations.
 A state equation (also called a transition
equation ) specifies the next state as a function
of the present state and inputs.

A(t + 1) = Ax + Bx
B(t + 1) = A’x
y = (A + B)x’
 State Table for the
Example Sequential Circuit
 State table
 The time sequence of inputs, outputs, and flip-flop
states can be enumerated in a state table (sometimes
called a transition table ).
 The table consists of four sections labeled present
state, input, next state, and output .
 The present-state section shows the states of flip-
flops A and B at any given time t .
 The input section gives a value of x for each possible
present state.
 The next-state section shows the states of the flip-
flops one clock cycle later, at time t + 1.
 The output section gives the value of y at time t for
each present state and input condition.
 State Diagram
 The information available in a state
table can be represented graphically
in the form of a state diagram.
 In this type of diagram, a state is
represented by a circle, and the
(clock-triggered) transitions between
states are indicated by directed lines
connecting the circles.
 State Diagram for the
Example Sequential Circuit
 State Reduction and Assignment
Reducing the number of flip-flops reduces the
cost of a circuit.
State Reduction: The reduction in the number of
flip-flops in a sequential circuit is referred to as
the state-reduction problem.
State-reduction algorithms are concerned with
procedures for reducing the number of states in
a state table, while keeping the external input–
output requirements unchanged.
 Illustration of state-reduction procedure
with an example
 There are an infinite number of input sequences that may
be applied to the circuit; each results in a unique output
sequence.
 As an example, consider the input sequence 01010110100
starting from the initial state a.
 Each input of 0 or 1 produces an output of 0 or 1 and
causes the circuit to go to the next state.
 For the example circuit in initial state a, an input of 0
produces an output of 0 and the circuit remains in state a.
 With present state a and an input of 1, the output is 0 and
the next state is b.
 With present state b and an input of 0, the output is 0 and
the next state is c.
Complete Sequence
State assignment
 Synchronous Sequential Circuit Design
Procedure
1. From the word description and specifications of
the desired operation, derive a state diagram for
the circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations
and output equations.
7. Draw the logic diagram.
 Excitation Table
Excitation table shows what should be the
values of flip-flop inputs so as to change the
present output to the desired value (next
output)
Excitation Table for JK flip-flop
Excitation Table for D flip-flop
Excitation Table for T flip-flop
Design a circuit that detects a sequence of three or more
consecutive 1’s in a string of bits coming through an input
line
 The state diagram for this type of circuit is derived by
starting with state S0, the reset state.
 If the input is 0, the circuit stays in S 0, but if the input is 1,
it goes to state S1 to indicate that a 1 was detected.
 If the next input is 1, the change is to state S 2 to indicate
the arrival of two consecutive 1’s, but if the input is 0,
the state goes back to S0.
 The third consecutive 1 sends the circuit to state S 3.
 If more 1’s are detected, the circuit stays in S3.
 Any 0 input sends the circuit back to S0.
 In this way, the circuit stays in S3 as long as there are
State Diagram and State Table
for Sequence Detector
K-Maps for Sequence Detector
Logic diagram of sequence detector
Synthesis Using JK Flip-Flops
Maps for J and K Input Equations
Logic diagram for sequential circuit with
JK flip-flops
Synthesis Using T Flip-Flops
3-Bit Binary Counter
REGISTERS
A register consists of a group of flip‐
flops together with gates that affect
their operation. The flip‐flops hold
the binary information, and the gates
determine how the information is
transferred into the register
Simple Four-bit Register
Four-bit Register with Parallel Load
Four-bit Shift Register
Serial Transfer from Reg. A to Reg. B
Serial Adder
 Universal Shift Register
1. A clear control to clear the register to 0.
2. A clock input to synchronize the operations.
3. A shift‐ right control to enable the shift‐ right operation
and the serial input and output lines associated with
the shift right.
4. A shift‐ left control to enable the shift‐ left operation
and the serial input and output lines associated with
the shift left.
5. A parallel‐load control to enable a parallel transfer and
the n input lines associated with the parallel transfer.
6. n parallel output lines.
7. A control state that leaves the information in the
register unchanged in response to the clock
Four-bit Universal Shift Register
Block Diagram of 4-bit Universal Shift Register
Function Table of Universal Shift Register
COUNTERS
 A counter is essentially a register that goes through a
predetermined sequence of binary states. The gates in
the counter are connected in such a way as to produce
the prescribed sequence of states.
 The counter goes through a prescribed sequence of states
upon the application of input pulses.
 The input pulses may be clock pulses, or they may
originate from some external source and may occur at a
fixed interval of time or at random.
 The sequence of states may follow the binary number
sequence or any other sequence of states.
 A counter that follows the binary number sequence is
called a binary counter.
 An n ‐bit binary counter consists of n flip‐flops and can
count in binary from 0 through 2n - 1.
 RIPPLE COUNTERS
 In a ripple counter, a flip‐flop output
transition serves as a source for
triggering other flip‐flops.
 The CLK input of some or all flip‐flops
are triggered, not by the common
clock pulses, but rather by the
transition that occurs in other flip‐flop
outputs.
 SYNCHRONOUS COUNTER

In a synchronous counter, the CLK inputs

of all flip‐flops receive the common
clock.
BINARY RIPPLE COUNTER
 BCD Ripple Counter
 A decimal or BCD counter follows a sequence
of 10 states and returns to 0 after the count of
9.
 Such a counter must have at least four flip‐
flops to represent each decimal digit, since a
decimal digit is represented by a binary code
with at least four bits.
 The sequence of states in a decimal counter is
dictated by the binary code used to represent
a decimal digit.
State Diagram of BCD Ripple Counter
 Block Diagram of 3-decade counters

 The BCD counter is also called a decade counter, since it counts from 0 to 9.
 To count in decimal from 0 to 99, we need a two‐decade counter.
 To count from 0 to 999, we need a three‐decade counter.
 Multiple decade counters can be constructed by connecting BCD counters in
cascade, one for each decade.
 A three‐decade counter is shown above.
 The inputs to the second and third decades come from Q8 of the previous
decade.
 When Q8 in one decade goes from 1 to 0, it triggers the count for the next
higher order decade while its own decade goes from 9 to 0.
 Synchronous Binary Counter
 The design of a synchronous binary counter is so simple that
there is no need to go through a sequential logic design process.
 In a synchronous binary counter, the flip‐flop in the least
significant position is complemented with every pulse.
 A flip‐flop in any other position is complemented when all the
bits in the lower significant positions are equal to 1.
 For example, if the present state of a four‐bit counter is A3A2A1A0
= 0011, the next count is 0100.
 A0 is always complemented.
 A1 is complemented because the present state of A0 = 1.
 A2 is complemented because the present state of A1A0 = 11.
 However, A3 is not complemented, because the present state of
A2A1A0 = 011, which does not give an all‐1’s condition.
4-bit Binary Synchronous Counter
4-bit Up-Down Counter
BCD Synchronous Counters
Binary Counter with Parallel Load
Function Table
Two ways to achieve a BCD counter using
a counter with parallel load
 Non binary Counters
• Counters can be designed to generate any
desired sequence of states.
• A divide‐by‐N counter (also known as a
modulo‐N counter or mod-N counter) is a
counter that goes through a repeated
sequence of N states.
• The sequence may follow the binary count or
may be any other arbitrary sequence.
 Example for Counter with Unused States

• Design a counter with JK flip-flops, that has a

repeated sequence of six states, with flip‐flops
B and C repeating the binary count 00, 01, 10,
and flip‐flop A alternating between 0 and 1
every three counts.
• The count sequence of the counter is not
straight binary, and two states, 011 and 111,
are not included in the count.
State Table with Flip-flop Inputs
Simplified Equations
Logic Diagram
 Ring Counter
• A ring counter is a circular shift
register with only one flip‐flop being
set at any particular time; all others
are cleared.
• The single bit is shifted from one flip‐
flop to the next to produce the
sequence of timing signals.
 Johnson Counter
 To generate 2n timing signals, we need either a shift register
with 2n flip‐flops or an n ‐bit binary counter together with an
n‐to‐2n ‐line decoder.
 For example, 16 timing signals can be generated with a 16‐
bit shift register connected as a ring counter or with a 4 ‐bit
binary counter and a 4‐to‐16‐line decoder.
 In the first case, we need 16 flip‐flops.
 In the second, we need 4 flip‐flops and 16 four ‐input AND
gates for the decoder.
 It is also possible to generate the timing signals with a
combination of a shift register and a decoder.
 That way, the number of flip‐flops is less than that in a ring
counter, and the decoder requires only two‐input gates.
 This combination is called a Johnson counter.
Construction of a Johnson Counter
 The register shifts its contents once to the right with every clock pulse, and at the
same time, the complemented value of the E flip‐flop is transferred into the A flip ‐flop.
 Starting from a cleared state, the switch‐tail ring counter goes through a sequence of
eight states.
 In general, a k ‐bit switch‐tail ring counter will go through a sequence of 2 k states.
Starting from all 0’s, each shift operation inserts 1’s from the left until the register is
filled with all 1’s. In the next sequences, 0’s are inserted from the left until the register
is again filled with all 0’s.
 A Johnson counter is a k ‐bit switch‐tail ring counter with 2 k decoding gates to provide
outputs for 2 k timing signals.
 The eight AND gates listed in the table, when connected to the circuit, will complete
the construction of the Johnson counter.
 Since each gate is enabled during one particular state sequence, the outputs of the
gates generate eight timing signals in succession.
 The decoding of a k ‐bit switch‐tail ring counter to obtain 2k timing signals follows a
regular pattern.
 The all‐0’s state is decoded by taking the complement of the two extreme flip ‐flop
outputs.
 The all‐1’s state is decoded by taking the normal outputs of the two extreme flip ‐flops.
All other states are decoded from an adjacent 1, 0 or 0, 1 pattern in the sequence.
 For example, sequence 7 has an adjacent 0, 1 pattern in flip ‐flops B and C .
 The decoded output is then obtained by taking the complement of B and the normal
output of C, or BC.
 One disadvantage of the above circuit is that if it finds itself in
an unused state, it will persist in moving from one invalid state
to another and never find its way to a valid state.
 The difficulty can be corrected by modifying the circuit to avoid
this undesirable condition.
 One correcting procedure is to disconnect the output from flip‐
flop B that goes to the D input of flip‐flop C and instead enable
the input of flip‐flop C by the function DC = (A + C)B where DC is
the flip‐flop input equation for the D input of flip‐flop C.
 Johnson counters can be constructed for any number of timing
sequences. The number of flip‐flops needed is one‐half the
number of timing signals.
 The number of decoding gates is equal to the number of timing
signals, and only two‐input gates are needed.