Verilog Lab 4

INTERGRATED CIRCUIT SYSTEM
1
DESIGN
SYNCHRONOUS
SEQUENTIAL
SYNCHRONO
CIRCUIT
US
SEQUENTIAL
CIRCUIT
DO TRUNG
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
2
1.OVERVIEW
3
ĐẾM XUNG module Counter

#(parameter N= 26, M = 50000000)
(input wire clk, reset,
output wire q );
// signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body, register
always @(posedge clk, posedge reset)
if (reset) r_reg <= 0;
else r_reg<=r_next;
// next state logic
assign r_next = (r_reg==M)?0:r_reg + 1;
// output logic
assign q=(r_reg<M/2)?0:1;
endmodule
4
MOD N module Chiaxung_1hz

#(parameter N= 26)
( input wire clk,
output wire q );
reg [N-1:0] r_reg;
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic assign
q=r_reg[25];
endmodule
5
BÀI 1: THIẾT KẾ MẠCH CHIA XUNG HỆ

THỐNG 50M THÀNH 25M.
a) Viết code RTL
b) Viết testbench mô phỏng
6
1.BLOCK DIG 2. RTL CODE
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk, output wire q );
3.TESTBENCH reg [N-1:0] r_reg;
initial
begin // body, register
clk = 0; always @(posedge clk)
end r_reg<=r_next;
// next state logic
always assign r_next = r_reg + 1;
begin // output logic
#10;
assign q=r_reg[0];
clk=~clk;
end endmodule
7
BÀI 2: THIẾT KẾ MẠCH CHIA XUNG HỆ

THỐNG 50M THÀNH 1 HZ, HIỂN THỊ LED
ĐƠN.
8
1.BLOCK DIG 2. RTL CODE
module Chiaxung_1hz
#(parameter N= 26)
( input wire clk, output wire q );
3.IMPLEMENT reg [N-1:0] r_reg;
NET "clk" LOC = "C9" | // body, register
IOSTANDARD = LVCMOS33 ; always @(posedge clk)
NET "clk" r_reg<=r_next;
CLOCK_DEDICATED_ROUTE = // next state logic
FALSE; assign r_next = r_reg + 1;
NET "q" LOC = "C11" | // output logic
IOSTANDARD = LVTTL | assign q=r_reg[25];
SLEW = SLOW | DRIVE = 8; endmodule
9
BÀI 3: THIẾT KẾ MẠCH ĐẾM LÊN 4 BIT

TỰ ĐỘNG, HIỂN THỊ LED ĐƠN. CLK LÊN,
RESET CAO.
a) Viết chương trình RTL
b) Viết testbench mô phỏng mạch
c) Thực thi trên board tần số 1 Hz
10
1.BLOCK DIG
1.BLOCK DIG
11
2. RTL CODE 3.TESTBENCH

module SynCounter_4b initial begin
( input wire clk, reset, clk = 0;
output wire [3:0] q ); reset = 0;
// signal declaration #400 ;
reg [3:0] r_reg; reset = 1;
wire [3:0] r_next; #100;
reset = 0;
// body, register
end
always @(posedge clk, posedge reset)
if (reset) r_reg <= 0;
CLOCK GENERATOR
else r_reg<=r_next;
//next state logic always
assign r_next = r_reg + 1; begin
// output logic #10;
assign q=r_reg; clk=~clk;
endmodule end
12
4. RTL CODE
module Chiaxung_1hz module Board_1Hz(
input wire clk_50m, reset,
#(parameter N= 26) output wire [3:0] led,
( input wire clk, output wire q ); output wire clk_1hz );
// signal declaration wire clk_i;
reg [N-1:0] r_reg; Chiaxung_1hz IC1(clk_50m, clk_i);
SynCounter_4b IC2(clk_i, reset, led);
wire [N-1:0] r_next; assign clk_1hz = clk_i;
// body, register endmodule
always @(posedge clk)
r_reg<=r_next;
// next state logic
// output logic
assign q=r_reg[25];
endmodule
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5.IMPLEMENT
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
14
BÀI 3: THIẾT KẾ MẠCH ĐẾM LÊN XUỐNG 4 BIT

TỰ ĐỘNG, LỰA CHỌN BỞI SWITCH UD HIỂN
THỊ LED ĐƠN. CLK LÊN, RESET CAO.
a) Viết chương trình RTL
b) Viết testbench mô phỏng mạch
c) Thực thi trên board tần số 1 Hz
15
1.BLOCK DIG
16
2. RTL CODE 3.TESTBENCH

module Counter_mod10_ud( initial begin
input wire clk, reset, ud, clk=0;
output wire [3:0] q ); reset=1;
// signal declaration ud=0;
reg [3:0] r_reg; #30;
wire [3:0] r_next; reset=0;
// body, register ud=1;
always @(posedge clk, posedge reset) #180;
if (reset) r_reg <= 0; ud=0;
else r_reg<=r_next; #180;
// next state logic ud=1;
assign r_next = (ud==0)?r_reg + 1:r_reg-1; #180;
// output logic ud=0;
assign q=r_reg; #180;
Endmodule reset=1;
end
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4. RTL CODE
module Chiaxung_1hz module Board_1Hz_Mod10(
input wire clk_50m, reset, ud,
#(parameter N= 26) output wire [3:0] led,
( input wire clk, output wire q ); output wire clk_1hz );
// signal declaration wire clk_i;
reg [N-1:0] r_reg; Chia_xung_c2 IC1(clk_50m, clk_i);
Counter_mod10_ud IC2(clk_i, reset,
wire [N-1:0] r_next; ud, led);
// body, register assign clk_1hz = clk_i;
always @(posedge clk) endmodule
r_reg<=r_next;
// next state logic
// output logic
assign q=r_reg[25];
endmodule
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5.IMPLEMENT
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "ud" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

Verilog Lab 4

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INTERGRATED CIRCUIT SYSTEM

ĐẾM XUNG module Counter

MOD N module Chiaxung_1hz

BÀI 1: THIẾT KẾ MẠCH CHIA XUNG HỆ

1.BLOCK DIG 2. RTL CODE

BÀI 2: THIẾT KẾ MẠCH CHIA XUNG HỆ

1.BLOCK DIG 2. RTL CODE

BÀI 3: THIẾT KẾ MẠCH ĐẾM LÊN 4 BIT

2. RTL CODE 3.TESTBENCH

BÀI 3: THIẾT KẾ MẠCH ĐẾM LÊN XUỐNG 4 BIT

2. RTL CODE 3.TESTBENCH

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