DQDB
DQDB
DQDB
6 (MAN)
Random Access Scheme
packet collision => waste resources retry backoff => bus idle
A DQDB MAN
Node
Node ...
Node
Node ...
Bus A
Frame Generators
Bus B
Network Configuration
Two buses with unidirectional structure. All communications on the subnet are synchronous and access is in fixed length packets that repeat continually. It is the function of the controllers at the bus ends to generate all timing signals to ensure synchronization.
AQ = = 0
AQ = 0 RC = 0
IDLE
AQ = = 0
AQ = 0 RC = = 0 CD = 0
COUNT DOWN STAND-BY
AQ = 0 RC = = 0
ACCESS
CD := RC RC := 0
Packet avail
CD == 0
Request Counter (RC) is incremented for each request bit received (REQ bit has been set), indicating the number of packet queued up for transmission on Bus A downstream from Si. RC is decremented for each empty packet that passes Si on bus A.
COUNTDOWN state: when Si has packet for transmission and (AQ 0 and RC 0) [AQ = # of packets queues for transmission]
RC is transferred CD counter and RC is cleared. CD counter is decremented by one for each empty packet that passes on bus A. RC is incremented for each received request bit that has been set. Initiate the transmission of the REQ bit to reserve a free packet (on Bus B).
STANDBY state: when a new packet moves into the first queue position and RC ==0
Attempt access in the next packet. If it is free, then transmit in the packet without sending REQ bit else initiate the sending of a REQ bit and go into WAIT state.