default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVLSI-DAT 2015: Hsinchu, Taiwan
- VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015. IEEE 2015, ISBN 978-1-4799-6275-4
- Yu-Hwa Lo:
Biomedical devices and instruments for point-of-care diagnosis. 1 - Jih Ren Goh, Yen-Long Lee, Soon-Jyh Chang:
A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. 1-4 - Ang-Feng Lin, Kuan-Yu Liao, Kuan-Ying Chiang, James Chien-Mo Li:
TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects. 1-4 - Albert Lee, Chien-Chen Lin, Ting-Chin Yang, Meng-Fan Chang:
An embedded ReRAM using a small-offset sense amplifier for low-voltage operations. 1-4 - Jiun-Liang Lin, Bo-Cheng Charles Lai:
BRAM efficient multi-ported memory on FPGA. 1-4 - Chan-Hsiang Weng, Tzu-An Wei, Tsung-Hsien Lin
:
A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer. 1-4 - Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A hybrid built-in self-test scheme for DRAMs. 1-4 - Jin-Chern Chiou, Shun-Hsi Hsu, Cheng-Kai Kuei, Tsung-Wei Wu:
An addressable UHF EPCGlobal Class1 Gen2 Sensor IC for wireless IOP monitoring on contact lens. 1-4 - Gene Li:
Specialty technology for loT. 1 - Tim Whitfield:
The sum of the parts: Overcoming leading edge design challenges by working in partnership. 1 - Hsien-Hsin S. Lee:
IC design challenges and opportunities for advanced process technology. 1-2 - Wu-Tung Cheng:
Identify problematic layout patterns through volume diagnosis. 1 - Subramani Kengeri:
Design-technology innovations enabling differentiation in emerging applications. 1 - Hong-Son Vu, Kuan-Hung Chen, Shih-Feng Sun, Tien-Mau Fong, Che-Wei Hsu, Lei Wang:
A power-efficient circuit design of feed-forward FxLMS active noise cancellation for in-ear headphones. 1-4 - Bing-Yang Lin, Cheng-Wen Wu, Harry H. Chen:
System-level test coverage prediction by structural stress test data mining. 1-4 - Lih-Yih Chiou, Liang-Ying Lu, Chieh-Yu Lin:
An effective matrix compression method for GPU-accelerated thermal analysis. 1-4 - Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, Ching-Te Chuang, Wei Hwang:
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. 1-4 - Jing-Shiun Lin, Ming-Der Shieh, Chung-Yen Liu, Der-Wei Yang:
Efficient highly-parallel turbo decoder for 3GPP LTE-Advanced. 1-4 - Augusli Kifli, Kun-Cheng Wu:
SoC test integration platform. 1-2 - Huai-Ting Li, Ding-Yuan Lee, Kun-Chih Chen, An-Yeu Andy Wu:
An algorithmic error-resilient scheme for robust LDPC decoding. 1-4 - Xiaokun Zhao, Zheng Song, Baoyong Chi:
A 60-dB DR PGA with DC-offset calibration for short-distance wireless receiver. 1-4 - Chien-Hui Liao, Yu-Ze Lin, Charles H.-P. Wen:
Dynamic voltage assignment for thermal-constrained task scheduler on 3D multi-core processors. 1-4 - David M. Brooks:
Circuit and system design for robotic flying vehicles. 1 - Kai Chen, Young Hwan Kim:
Current source model of combinational logic gates for accurate gate-level circuit analysis and timing analysis. 1-4 - Júlio Costa:
Tunable and reconfigurable solutions using RFSOI-on-HR-Si technologies. 1 - Fernando Silveira, Julian Oreggioni, Pablo Castro-Lisboa:
Constraints and design approaches in analog ICs forlmplantable medical devices. 1-4 - Hong-Yi Wu, Chien-Chih Chen, Hsiang-Jen Tsai, Yin-Chi Peng, Tien-Fu Chen:
Lifetime-aware LRU promotion policy for last-level cache. 1-4 - Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin:
Low-power gated clock tree optimization for three-dimensional integrated circuits. 1-4 - Cheng-Hung Wu, Yi-Da Wang, Kuen-Jong Lee:
Improve transition fault diagnosability via observation point insertion. 1-4 - Shyue-Kung Lu, Shu-Ling Lin, Hao-Wei Lin, Masaki Hashizume:
Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs. 1-4 - Tadaaki Yamauchi:
Prospect of embedded non-volatile memory in the smart society. 1-2 - Anirban Sengupta, Saumya Bhadauria:
Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraints. 1-4 - An-Tia Xiao, Shiang-Ren Yang, Yuan-Hsiang Miao, Ching-Hwa Cheng, Jiun-In Guo:
A power-aware quad-voltage H.264 encoder chip for wireless panoramic endoscope applications. 1-4 - Keh-Jeng Chang, Shih-Hao Lee, Kuo-Fu Lee, Ping-Hung Yuh, Ho-Che Yu, Wen-Cheng Huang, Victor C. Y. Chang:
Accurate 3-D capacitance extractions for advanced nanometer CMOS nodes. 1-4 - Juan Sebastian Rodriguez Estupinan, Alain Vachoux, Joris Pascal:
Electro-thermal modeling of a Rogowski coil sensor system. 1-4 - Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Ipek Baz, Alexandre Schmid, Yusuf Leblebici:
Trinocular adaptive window size disparity estimation algorithm and its real-time hardware. 1-4 - Song Jin, Songwei Pei, Yinhe Han, Huawei Li:
On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island. 1-4 - Hans Stork:
Power and sensor semiconductors driving automotive applications. 1 - Chia-Jung Chang, Yin-Chi Peng, Chien-Chih Chen, Tien-Fu Chen, Pen-Chung Yew:
Adaptive granularity and coordinated management for timely prefetching in multi-core systems. 1-4 - Hsiao-Chin Tuan:
Semiconductor specialty technologies in IOT era. 1 - Shih-Lien Lu:
Evaluation methods of computer memory system. 1-4 - Jheng-Jhan He, Chih-Peng Fan:
Design and VLSI implementation of novel pre-screening and simplified sorting based K-best detection for MIMO systems. 1-4 - Jean-Marc Le Meil, Bernard Aspar, Eric Desbonnets, Jean-Pierre Raskin:
Engineered substrates: The foundation to meet current and future RF requirements. 1-4 - Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, Soon-Jyh Chang:
A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer. 1-4 - Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee:
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. 1-4 - Tsorng-Juu Liang:
The applications of power integrated circuits with energy saving. 1 - Zheng-Wei Huang, Chin-Fong Chiu, Chih-Cheng Hsieh:
An in-pixel equalizer with kTC noise cancellation and FPN reduction for time-of-flight CMOS image sensor. 1-4 - Gabriel A. Rincón-Mora:
Energy-harvesting microsystems. 1 - Kun-Han Tsai, Janusz Rajski:
Clock-domain-aware test for improving pattern compression. 1-4 - Guo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng:
A test-application-count based learning technique for test time reduction. 1-4 - Yi-Hang Chen, Yang Chen, Juinn-Dar Huang:
ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays. 1-4 - Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
An impact of process variation on supply voltage dependence of logic path delay variation. 1-4 - Jia-Ju Liao, Shang-Yi Chuang, Chia-Ching Chou, Chia-Chi Chang, Wai-Chi Fang:
An effective photoplethysmography signal processing system based on EEMD method. 1-4 - Wei-Xiang Tang, Keng-Yu Lin, Po-Han Haung:
Design of near-threshold microcontroller for wireless sensing applications. 1-4 - Jiann-Jong Chen, Ping-Hua Wu, Ta-Wei Chao, Yi-Tsen Ku, Yuh-Shyan Hwang, Cheng-Chieh Yu:
A low-noise high-efficient buck converter with noise-shaping technique. 1-4 - Yanfeng Li, Yutao Liu, Woogeun Rhee, Zhihua Wang:
A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator. 1-4 - Wei-Lung Yang, Hsi-Pin Ma:
A configurable wavelet processor for biomedical applications. 1-4 - Yen-Fu Chen, Kea-Tiong Tang:
A wireless power transmission subsystem with capacitor-less high PSR LDO and thermal protection mechanism for artificial retina application. 1-4 - Wen-Ping Lee, Cheng-Yen Wang:
Reusable and flexible verification methodology from architecture to RTL design. 1-4 - Shushanik Karapetyan, Ulf Schlichtmann:
Integrating aging aware timing analysis into a commercial STA tool. 1-4 - Cheng-Chih Mao:
Low-power IC design challenge. 1 - Bo-Jyun Kuo, Bo-Wei Chen, Chia-Ming Tsai:
A 0.6V, 1.3GHz dynamic comparator with cross-coupled latches. 1-4 - Ting-Yang Wang, Tai-Cheng Lee:
A 84.7-DR wide BW incremental ADC using CT structure. 1-4 - Federico A. Altolaguirre, Ming-Dou Ker:
Active ESD protection for input transistors in a 40-nm CMOS process. 1-4 - Peter Hsieh:
IoT evolution - By crossing application domains. 1 - Ying-Chi Lien, Ching-Mao Lee, Chih-Wei Li, Ban-Han Tsai, Chien-Nan Jimmy Liu:
Low-noise analog synthesis platform for bio-signal acquisition system. 1-4 - Ching-Che Chung, Chi-Tung Chang, Chih-Yu Lin:
A 1 Mb/s-40 Mb/s human body channel communication transceiver. 1-4 - Hugo Cruz, Hong-Yi Huang, Shueen-Yu Lee, Ching-Hsing Luo:
A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS. 1-4 - Po-Yu Chien, Yuan-Hsiang Miao, Jiun-In Guo:
A 3D hand tracking design for gesture control in complex environments. 1-4 - Mu-lee Huang, Chung-Chih Hung:
Full-custom all-digital phase locked loop for clock generation. 1-4 - Ping-Yuan Tsai, Yu-Yun Chang, Shu-Yu Hsu, Chen-Yi Lee:
An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver. 1-4 - Huaxing Tang, Ting-Pu Tai, Wu-Tung Cheng, Brady Benware, Friedrich Hapke:
Diagnosing timing related cell internal defects for FinFET technology. 1-4 - Carl Engblom:
Drivers and aspects of 2.5/3D integration as a potential game-changer. 1 - Che-Min Huang, Tsung-Te Liu, Tzi-Dar Chiueh:
An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction. 1-4 - Yao-Joe Yang:
Hydrogel-based microdevices. 1 - Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang:
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. 1-4 - Yung-Hui Yu, Po-Hao Wang, Shang-Jen Tsai, Tien-Fu Chen:
A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation. 1-4 - Hang Yu, Xinyuan Qian, Menghan Guo, Shoushun Chen, Kay Soon Low:
A time delay integration CMOS image sensor with online deblurring algorithm. 1-4 - Chao-Wen Tzeng, Yin-Yen Chen, Jih-Nung Lee, Shu-Yi Kao:
Case study of process and design performance debugging with Digital Speed Sensor. 1-4 - Liang-Yu Huang, Chia-Yi Wu, Chun-Yi Liu, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou:
A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems. 1-4 - Walden C. Rhines:
Cost challenges on the way to the Internet of Things. 1 - Jai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan:
Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint. 1-4 - Sunil Dutt, Anshu Chauhan, Sukumar Nandi, Gaurav Trivedi:
Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC units. 1-4 - Yu-Lee Yen, Chien-Nan Kuo, Ching-Feng Lee, Kevin Chen:
DC-to-5-GHz variable gain amplifier for high speed DSO. 1-4 - Chun-Chang Wu, W.-C. Kuo, H.-J. Wang, Y.-C. Huang, Y.-H. Chen, Y.-Y. Chou, Shih-An Yu, Shey-Shi Lu:
A pliable and batteryless real-time ECG monitoring system-in-a-patch. 1-4 - Makoto Takamiya:
Energy efficient design and energy harvesting for energy autonomous systems. 1-3
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-03-01 14:59 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
