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2020 – today
- 2024
[j28]Hao-Hsuan Chang
, Ci-Ren Chen, Tai-Cheng Lee:
A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique. IEEE J. Solid State Circuits 59(7): 2199-2208 (2024)- [j27]Yu-Hong Yang, Tai-Cheng Lee:
A Sub-Baud-Rate Wireline Receiver With One-Tap DFE. IEEE J. Solid State Circuits 59(11): 3694-3704 (2024) - 2023
- [j26]Yu-Hong Yang, Mou Tzou, Tai-Cheng Lee:
A 6.0-11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 386-390 (2023) - [j25]Yen-Chun Chan, Che-Wei Chang, Tai-Cheng Lee:
A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC With an Oscillator-Based Integrator. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3263-3267 (2023) - 2022
- [j24]Hao-Hsuan Chang, Tung-Cheng Lin, Tai-Cheng Lee:
A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2021-2025 (2022) - [c40]Cheng-Tang Chen, Yu-Hong Yang, Tai-Cheng Lee:
A Type-3 FMCW Radar Synthesizer with Wide Frequency Modulation Bandwidth. ISCAS 2022: 2750-2753 - [c39]Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I-Ching Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li, Mango C.-T. Chao:
A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction. ISPD 2022: 107-115 - [c38]Li-Wei Chen, Yao-Nien Sui, Tai-Cheng Lee, Yih-Lang Li, Mango C.-T. Chao, I-Ching Tsai, Tai-Wei Kung, En-Cheng Liu, Yun-Chih Chang:
Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs. ISQED 2022: 1-6 - [c37]Yen-Po Lai, Hao-Hsuan Chang, Tai-Cheng Lee:
An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter. VLSI-DAT 2022: 1-4 - 2020
- [c36]Tai-Cheng Lee, Cheng-Yen Yang, Yih-Lang Li:
/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis. ICCAD 2020: 159:1-159:8 - [c35]Kun-Ruei Li, Wei-Sung Chang, Tai-Cheng Lee:
A 5 GHz Outer-Loop Phase Noise Filter with Delay-Sampling Technique. ISCAS 2020: 1-4 - [c34]Hsiu-Hsien Ting, Tai-Cheng Lee:
25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique. ISSCC 2020: 390-392 - [c33]Hsiang-Chun Cheng, Yu-Hong Yang, Tai-Cheng Lee:
Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [j23]Tai-Cheng Lee, Yih-Lang Li:
Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2434-2446 (2019) - [c32]Yu-Lun Hsieh, Tai-Cheng Lee:
A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling. ASICON 2019: 1-4 - 2018
- [j22]Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee:
A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique. IEEE J. Solid State Circuits 53(5): 1508-1517 (2018) - [c31]Venkatesh Srinivasan, Stephane Le Tuai, Tai-Cheng Lee:
F2: FinFETs & FDSOI - A mixed signal circuit designer's perspective. ISSCC 2018: 505-507 - 2017
- [c30]Wei-Sung Chang, Dai-En Jhou, Yu-Hong Yang, Tai-Cheng Lee:
An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique. A-SSCC 2017: 53-56 - [c29]Jui-Cheng Hsiao, Dai-En Jhou, Tai-Cheng Lee:
A 10-Gb/s equalizer with digital adaptation. ISOCC 2017: 38-39 - [c28]Tai-Cheng Lee, Bob Verbruggen, Un-Ku Moon:
Session 28 overview: Hybrid ADCs. ISSCC 2017: 464-465 - [c27]Hsuan-Yun Kao, Cheng-Ting Tsai, Chun-Yen Pong, Shan-Fong Liang, Zu-Kai Weng, Yu-Chieh Chi, Hao-Chung Kuo, Jian Jang Huang, Tai-Cheng Lee, Tien-Tsorng Shih, Jau-Ji Jou, Wood-Hi Cheng, Chao-Hsin Wu, Gong-Ru Lin:
Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link. OFC 2017: 1-3 - 2016
- [j21]Chia-Lun Chang, Tai-Cheng Lee:
A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor-Sharing Technique for Thermoelectric Energy Harvesting Applications. J. Circuits Syst. Comput. 25(1): 1640007:1-1640007:18 (2016) - [j20]Chin-Yu Lin, Tai-Cheng Lee:
A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(7): 929-938 (2016) - [j19]Chin-Yu Lin, Chien-Heng Wong, Chia-Hau Hsu, Yen-Hsin Wei, Tai-Cheng Lee:
A 200-MS/s Phase-Detector-Based Comparator With 400-μVrms Noise. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 813-817 (2016) - [j18]Wei-Sung Chang, Tai-Cheng Lee:
A 5 GHz Fractional-N ADC-Based Digital Phase-Locked Loops With -243.8 dB FOM. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11): 1845-1853 (2016) - [c26]Chun-Ping Wang, Tai-Cheng Lee:
A technique for in-band phase noise reduction in fractional-N frequency synthesizers. A-SSCC 2016: 273-276 - [c25]Venkatesh Srinivasan, Tai-Cheng Lee:
Session 15 overview: Oversampling data converters. ISSCC 2016: 268-269 - [c24]Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee:
27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration. ISSCC 2016: 468-469 - 2015
- [c23]Chen-Kai Hsu, Tai-Cheng Lee:
A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology. A-SSCC 2015: 1-4 - [c22]Ting-Yang Wang, Tai-Cheng Lee:
A 84.7-DR wide BW incremental ADC using CT structure. VLSI-DAT 2015: 1-4 - 2014
- [j17]Wei-Sung Chang, Po-Chun Huang, Tai-Cheng Lee:
A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector. IEEE J. Solid State Circuits 49(12): 2964-2975 (2014) - [j16]Cheng-Jyun Li, Tai-Cheng Lee:
2.4-GHz High-Efficiency Adaptive Power. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 434-438 (2014) - [c21]Li-Hung Chiueh, Tai-Cheng Lee:
A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit. A-SSCC 2014: 289-292 - [c20]Yu-Hsuan Kang, Chin-Yu Lin, Tai-Cheng Lee:
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator. ISCAS 2014: 1328-1331 - [c19]Chia-Lun Chang, Tai-Cheng Lee:
A compact multi-input thermoelectric energy harvesting system with 58.5% power conversion efficiency and 32.4-mW output power capability. ISIC 2014: 1-4 - [c18]Po-Chun Huang, Wei-Sung Chang, Tai-Cheng Lee:
21.2 A 2.3GHz fractional-N dividerless phase-locked loop with -112dBc/Hz in-band phase noise. ISSCC 2014: 362-363 - [c17]Jia-An Jheng, Wei-Sung Chang, Tai-Cheng Lee:
A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth. VLSI-DAT 2014: 1-4 - [c16]Chin-Yu Lin, Tai-Cheng Lee:
A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique. VLSIC 2014: 1-2 - 2013
- [j15]Chien-Heng Wong, Tai-Cheng Lee:
A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(5): 1264-1273 (2013) - [c15]Chin-Yu Lin, Yen-Chuan Huang, Tai-Cheng Lee:
Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies. VLSI-DAT 2013: 1-4 - [c14]Chin-Yu Lin, Tai-Cheng Lee:
Jitter error cancellation technique in digital domain for ADC. VLSI-DAT 2013: 1-4 - 2012
- [c13]Chia-Chi Ho, Tai-Cheng Lee:
A 10-bit 200-MS/s reconfigurable pipelined A/D converter. VLSI-DAT 2012: 1-4 - 2011
- [j14]Zuow-Zun Chen, Tai-Cheng Lee:
The Design and Analysis of Dual-Delay-Path Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(3): 470-478 (2011) - [j13]Zuow-Zun Chen, Tai-Cheng Lee:
The Study of a Dual-Mode Ring Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 210-214 (2011) - [j12]Yen-Chuan Huang, Tai-Cheng Lee:
A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1157-1166 (2011) - 2010
- [j11]Yen-Chuan Huang, Tai-Cheng Lee:
A 0.02-mm 2 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology. IEEE J. Solid State Circuits 45(3): 610-619 (2010) - [j10]Tai-Cheng Lee, Cheng-Hsiao Lin:
Nonlinear R-2R Transistor-Only DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10): 2644-2653 (2010) - [c12]Kevin Fong, Yu-Cheng Hung, Zuow-Zun Chen, Tai-Cheng Lee:
An all-digital de-skew clock generator for arbitrary wide range delay. APCCAS 2010: 112-115 - [c11]Chin-Yu Lin, Chun-Yu Chiang, Tai-Cheng Lee:
An offset phase-locked loop spread spectrum clock generator for SATA III. CICC 2010: 1-4 - [c10]Yen-Chuan Huang, Tai-Cheng Lee:
A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique. ISSCC 2010: 300-301
2000 – 2009
- 2009
- [j9]Keng-Jan Hsiao, Tai-Cheng Lee:
An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation. IEEE J. Solid State Circuits 44(9): 2478-2487 (2009) - [j8]Li-Han Hung, Tai-Cheng Lee:
A Split-Based Digital Background Calibration Technique in Pipelined ADCs. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 855-859 (2009) - 2008
- [j7]Keng-Jan Hsiao, Tai-Cheng Lee:
The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning. IEEE J. Solid State Circuits 43(6): 1427-1435 (2008) - [c9]Keng-Jan Hsiao, Tai-Cheng Lee:
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation. ISSCC 2008: 514-515 - 2007
- [j6]Ding-Lan Shen, Tai-Cheng Lee:
A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers. IEEE J. Solid State Circuits 42(2): 258-268 (2007) - [c8]Hong-Sing Kao, Ming-Jen Yang, Tai-Cheng Lee:
A Delay-Line-Based GFSK Demodulator for Low-IF Receivers. ISSCC 2007: 88-589 - 2006
- [j5]Tai-Cheng Lee, Keng-Jan Hsiao:
The design and analysis of a DLL-based frequency synthesizer for UWB application. IEEE J. Solid State Circuits 41(6): 1245-1252 (2006) - [j4]Tai-Cheng Lee, Yen-Chuan Huang:
The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application. IEEE J. Solid State Circuits 41(6): 1253-1261 (2006) - [j3]Tai-Cheng Lee, Chin-Chi Chen:
A mixed-signal GFSK demodulator for Bluetooth. IEEE Trans. Circuits Syst. II Express Briefs 53-II(3): 197-201 (2006) - [c7]Tai-Cheng Lee, Wei-Liang Lee:
A Spur Suppression Technique for Phase-Locked Frequency Synthesizers. ISSCC 2006: 2432-2441 - 2005
- [c6]Ding-Lan Shen, Tai-Cheng Lee:
A linear-approximation technique for digitally-calibrated pipelined A/D converters. ISCAS (2) 2005: 1382-1385 - [c5]Tai-Cheng Lee, Yen-Chuan Huang:
An optimization technique for RF buffers with active inductors. ISCAS (4) 2005: 3692-3695 - 2004
- [c4]Hung-Chieh Tsai, Jyh-Yih Yeh, Wei-Hsuan Tu, Tai-Cheng Lee, Chorng-Kuang Wang:
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier. ISCAS (4) 2004: 393-396 - 2003
- [j2]Tai-Cheng Lee, Behzad Razavi:
A stabilization technique for phase-locked frequency synthesizers. IEEE J. Solid State Circuits 38(6): 888-894 (2003) - 2002
- [c3]Chih-Chun Tang, Chia-Hsin Wu, Kun-Hsien Li, Tai-Cheng Lee, Shen-Iuan Liu:
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network. ISCAS (3) 2002: 77-80 - 2001
- [j1]Tai-Cheng Lee, Behzad Razavi:
A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. IEEE J. Solid State Circuits 36(3): 366-373 (2001) - [c2]Tai-Cheng Lee, Behzad Razavi:
A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire. CICC 2001: 131-134 - 2000
- [c1]Tai-Cheng Lee, Behzad Razavi:
A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. CICC 2000: 461-464
Coauthor Index
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