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ORCIDJente B. Kuang
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- affiliation: IBM Research-Austin, Austin, TX, USA
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2010 – 2019
- 2015
[j9]Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael P. Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha:
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(10): 1537-1557 (2015)- 2013
- [j8]Xingsheng Wang
, Binjie Cheng, Jente B. Kuang, Andrew R. Brown, Campbell Millar, Asen Asenov:
Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology. IEEE Des. Test 30(6): 18-28 (2013) - [c13]Jente B. Kuang, Keith A. Jenkins, Kevin Stawiasz, Jeremy D. Schaub:
Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators. ESSCIRC 2013: 419-422 - [c12]Xingsheng Wang, Binjie Cheng, Andrew R. Brown, Campbell Millar, Jente B. Kuang, Sani R. Nassif, Asen Asenov:
Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability. ESSDERC 2013: 234-237 - [c11]Binjie Cheng, Xingsheng Wang, Andrew R. Brown, Jente B. Kuang, Dave Reid, Campbell Millar, Sani R. Nassif, Asen Asenov:
SRAM device and cell co-design considerations in a 14nm SOI FinFET technology. ISCAS 2013: 2339-2342 - 2011
- [j7]Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Thomas Fröhnel, Sudesh Saroop, Sani R. Nassif, Kevin J. Nowka:
The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2010-2016 (2011) - 2010
- [c10]Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka:
A 32nm 0.5V-supply dual-read 6T SRAM. CICC 2010: 1-4
2000 – 2009
- 2009
- [j6]Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer:
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits 44(4): 1216-1226 (2009) - [c9]Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka:
Statistical yield analysis of silicon-on-insulator embedded DRAM. ISQED 2009: 190-194 - 2008
- [j5]Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, Fadi H. Gebara, Kevin J. Nowka:
Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1657-1665 (2008) - [c8]Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata:
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. ESSCIRC 2008: 66-69 - [c7]Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif:
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED 2008: 87-92 - 2007
- [c6]Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif:
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED 2007: 33-40 - 2006
- [c5]Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif:
SRAM Local Bit Line Access Failure Analyses. ISQED 2006: 204-209 - 2005
- [c4]Tom Beacom, Timothy C. Buchholtz, D. Bradley, Jack Randolph, Salvatore N. Storino, Mark Veldhuizen, Sherman M. Dance, Jente B. Kuang, Steve Schwinn, Sue Cox, Fred Ziegler, J. Kao, Chuck Li, Christophe Tretz, J. Cabellon, Andrew Freemyer, Matthew Tubbs:
Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor. CICC 2005: 235-238 - [c3]Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi:
A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. ICCD 2005: 574-584 - 2004
- [j4]Jente B. Kuang, Ching-Te Chuang:
Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits. IEEE Trans. Circuits Syst. II Express Briefs 51-II(7): 349-353 (2004) - [c2]Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka:
A low latency and low power dynamic Carry Save Adder. ISCAS (2) 2004: 477-480 - 2001
- [j3]Jente B. Kuang, David H. Allen, Ching-Te Chuang:
Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology. IEEE J. Solid State Circuits 36(4): 597-604 (2001)
1990 – 1999
- 1997
- [j2]Jente B. Kuang, Somnuk Ratanaphanyarat, Mary Jo Saccamango, Louis L.-C. Hsu, Roy C. Flaker, Lawrence F. Wagner, Shao-Fu Sanford Chu, Ghavam G. Shahidi:
SRAM bitline circuits on PD SOI: advantages and concerns. IEEE J. Solid State Circuits 32(6): 837-844 (1997) - [j1]Pong-Fei Lu, Ching-Te Chuang, Jin Ji, Lawrence F. Wagner, Chang-Ming Hsieh, Jente B. Kuang, Louis Lu-Chen Hsu, Mario M. Pelella Jr., Shao-Fu Sanford Chu, Carl J. Anderson:
Floating-body effects in partially depleted SOI CMOS circuits. IEEE J. Solid State Circuits 32(8): 1241-1253 (1997) - 1996
- [c1]Pong-Fei Lu, Jin Ji, Ching-Te Chuang, Lawrence F. Wagner, Chang-Ming Hsieh, Jente Benedict Kuang, L. Hsu, Mario M. Pelella Jr., Shao-Fu Sanford Chu, Carl J. Anderson:
Floating body effects in partially-depleted SOI CMOS circuits. ISLPED 1996: 139-144
Coauthor Index
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