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ORCIDHae-Seung Lee
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- affiliation: Massachusetts Institute of Technology, Cambridge, USA
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2020 – today
- 2024
[j41]Rishabh Mittal
, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee:
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. IEEE J. Solid State Circuits 59(4): 1158-1170 (2024)- [i3]Tanner Andrulis, Ruicong Chen, Hae-Seung Lee, Joel S. Emer, Vivienne Sze:
Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design. CoRR abs/2404.06553 (2024) - 2023
- [c42]Jessica Zheng, Hanrui Wang, Anand Chandrasekhar, Aaron D. Aguirre, Song Han, Hae-Seung Lee, Charles G. Sodini:
Machine Learning for Arterial Blood Pressure Prediction. CHIL 2023: 427-439 - [c41]Ruicong Chen, Anantha P. Chandrakasan, Hae-Seung Lee:
Sniff-SAR: A 9.8fJ/c.-s 12b secure ADC with detectiondriven protection against power and EM side-channel attack. CICC 2023: 1-2 - [c40]Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee:
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c39]Ruicong Chen, H. T. Kung, Anantha P. Chandrakasan, Hae-Seung Lee:
A Bit-level Sparsity-aware SAR ADC with Direct Hybrid Encoding for Signed Expressions for AIoT Applications. ISLPED 2022: 11:1-11:6 - [c38]Ruicong Chen, Hanrui Wang, Anantha P. Chandrakasan, Hae-Seung Lee:
RaM-SAR: A Low Energy and Area Overhead, 11.3fJ/conv.-step 12b 25MS/s Secure Random-Mapping SAR ADC with Power and EM Side-channel Attack Resilience. VLSI Technology and Circuits 2022: 94-95 - 2021
- [j40]Taehoon Jeong, Anantha P. Chandrakasan, Hae-Seung Lee:
S2ADC: A 12-bit, 1.25-MS/s Secure SAR ADC With Power Side-Channel Attack Resistance. IEEE J. Solid State Circuits 56(3): 844-854 (2021) - [j39]Joohyun Seo, Hae-Seung Lee, Charles G. Sodini:
Non-Invasive Evaluation of a Carotid Arterial Pressure Waveform Using Motion-Tolerant Ultrasound Measurements During the Valsalva Maneuver. IEEE J. Biomed. Health Informatics 25(1): 163-174 (2021) - 2020
- [c37]Taehoon Jeong, Anantha P. Chandrakasan, Hae-Seung Lee:
S2ADC: A 12-bit, 1.25MS/s Secure SAR ADC with Power Side-Channel Attack Resistance. CICC 2020: 1-4 - [c36]Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han:
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. DAC 2020: 1-6 - [i2]Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han:
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. CoRR abs/2005.00406 (2020)
2010 – 2019
- 2019
- [c35]Xi Yang, Seung-Jun Bae, Hae-Seung Lee:
An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS. ESSCIRC 2019: 305-308 - 2018
- [c34]Sirma Orguc, Harneet Singh Khurana, Konstantina M. Stankovic, Hae-Seung Lee, Anantha P. Chandrakasan:
EMG-based Real Time Facial Gesture Recognition for Stress Monitoring. EMBC 2018: 2651-2654 - [c33]Joohyun Seo, Charles G. Sodini, Hae-Seung Lee:
Monitoring of Pulse Pressure and Arterial Pressure Waveform Changes during the Valsalva Maneuver by a Portable Ultrasound System. EMBC 2018: 3817-3820 - [c32]Harneet Singh Khurana, Anantha P. Chandrakasan, Hae-Seung Lee:
Recode then LSB-first SAR ADC for Reducing Energy and Bit-cycles. ISCAS 2018: 1-5 - [c31]Xi Yang, Hae-Seung Lee:
Design of a 6th-order Continuous-time Bandpass Delta-Sigma Modulator with 250 MHz IF, 25 MHz Bandwidth, and over 75 dB SNDR. ISCAS 2018: 1-5 - [i1]Hanrui Wang, Jiacheng Yang, Hae-Seung Lee, Song Han:
Learning to Design Circuits. CoRR abs/1812.02734 (2018) - 2017
- [c30]Sirma Orguc, Harneet Singh Khurana, Hae-Seung Lee, Anantha P. Chandrakasan:
0.3 V ultra-low power sensor interface for EMG. ESSCIRC 2017: 219-222 - 2016
- [j38]Kailiang Chen, Hae-Seung Lee, Charles G. Sodini:
A Column-Row-Parallel ASIC Architecture for 3-D Portable Medical Ultrasonic Imaging. IEEE J. Solid State Circuits 51(3): 738-751 (2016) - [c29]David Robertson, Aaron Buchwald, Michael Flynn, Hae-Seung Lee, Un-Ku Moon, Boris Murmann:
Data converter reflections: 19 papers from the last ten years that deserve a second look. ESSCIRC 2016: 161-164 - [c28]Daniel Prashanth, Hae-Seung Lee:
A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs. ACM Great Lakes Symposium on VLSI 2016: 129-132 - [c27]Xi Yang, Hae-Seung Lee:
Design of a 4th-order multi-stage feedforward operational amplifier for continuous-time bandpass delta sigma modulators. ISCAS 2016: 1058-1061 - 2015
- [j37]Do-Yeon Yoon, Stacy Ho, Hae-Seung Lee:
A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS. IEEE J. Solid State Circuits 50(12): 2880-2890 (2015) - [j36]Hyun Ho Boo, Duane S. Boning, Hae-Seung Lee:
A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers. IEEE J. Solid State Circuits 50(12): 2912-2921 (2015) - [c26]SungWon Chung, Hae-Seung Lee:
A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMT. CICC 2015: 1-4 - [c25]Joohyun Seo, Sabino J. Pietrangelo, Hae-Seung Lee, Charles G. Sodini:
Carotid arterial blood pressure waveform monitoring using a portable ultrasound system. EMBC 2015: 5692-5695 - [c24]Hyun Ho Boo, Duane S. Boning, Hae-Seung Lee:
15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers. ISSCC 2015: 1-3 - [c23]Do-Yeon Yoon, Stacy Ho, Hae-Seung Lee:
15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW CT MASH ΔΣ modulator in 28nm CMOS. ISSCC 2015: 1-3 - [c22]Hae-Seung Lee, Seng-Pan Li:
Session 26 overview: Nyquist-rate converters: Data converters subcommittee. ISSCC 2015: 456-457 - 2014
- [j35]Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer:
A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. IEEE J. Solid State Circuits 49(6): 1366-1382 (2014) - [j34]Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee:
A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration. IEEE J. Solid State Circuits 49(12): 2846-2856 (2014) - [c21]Dong-Young Chang, Carlos E. Muñoz, Denis C. Daly, Soon-Kyun Shin, Kevin Guay, Thomas Thurston, Hae-Seung Lee, Kush Gulati, Matthew Z. Straayer:
11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. ISSCC 2014: 204-205 - [c20]Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee:
22.4 A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration. ISSCC 2014: 384-385 - [c19]Kailiang Chen, Hae-Seung Lee, Charles G. Sodini:
A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging. VLSIC 2014: 1-2 - 2013
- [j33]Kailiang Chen, Hae-Seung Lee, Anantha P. Chandrakasan, Charles G. Sodini:
Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver. IEEE J. Solid State Circuits 48(11): 2734-2745 (2013) - [c18]Albert H. Chang, Hae-Seung Lee, Duane S. Boning:
A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration. ESSCIRC 2013: 109-112 - [c17]Do-Yeon Yoon, Hae-Seung Lee, Jeffrey Gealow:
Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators. MWSCAS 2013: 562-565 - 2012
- [j32]Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee:
A 12 b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC. IEEE J. Solid State Circuits 47(7): 1603-1614 (2012) - [c16]Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer:
A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS. CICC 2012: 1-4 - [c15]Nan Sun, Hae-Seung Lee, Donhee Ham:
A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration. ESSCIRC 2012: 269-272 - 2011
- [j31]Payam Lajevardi, Anantha P. Chandrakasan, Hae-Seung Lee:
Zero-Crossing Detector Based Reconfigurable Analog System. IEEE J. Solid State Circuits 46(11): 2478-2487 (2011) - [c14]Jack Chu, Hae-Seung Lee:
A 450 MS/s 10-bit time-interleaved zero-crossing based ADC. CICC 2011: 1-4 - [c13]Sunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee:
A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC. ESSCIRC 2011: 355-358 - [c12]Albert H. Chang, Hae-Seung Lee, Duane S. Boning:
Redundancy in SAR ADCs. ACM Great Lakes Symposium on VLSI 2011: 283-288 - 2010
- [j30]Hae-Seung Lee, Lane Brooks, Charles G. Sodini:
Zero-Crossing-Based Ultra-Low-Power A/D Converters. Proc. IEEE 98(2): 315-332 (2010) - [c11]Albert Chow, Hae-Seung Lee:
Offset cancellation for zero crossing based circuits. ISCAS 2010: 1719-1722
2000 – 2009
- 2009
- [j29]Lane Brooks, Hae-Seung Lee:
A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC. IEEE J. Solid State Circuits 44(12): 3329-3343 (2009) - [j28]Todd Sepke, Peter Holloway, Charles G. Sodini, Hae-Seung Lee:
Noise Analysis for Comparator-Based Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(3): 541-553 (2009) - [c10]Lane Brooks, Hae-Seung Lee:
A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB. ISSCC 2009: 166-167 - 2008
- [j27]Hae-Seung Lee, Charles G. Sodini:
Analog-to-Digital Converters: Digitizing the Analog World. Proc. IEEE 96(2): 323-334 (2008) - [j26]Nan Sun, Hae-Seung Lee, Donhee Ham:
Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching. IEEE Trans. Circuits Syst. II Express Briefs 55-II(9): 877-881 (2008) - [j25]Lane Brooks, Hae-Seung Lee:
Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(10): 2969-2979 (2008) - [c9]Moo-Yeol Choi, Sung-No Lee, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim, Hae-Seung Lee:
A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control. CICC 2008: 89-92 - [c8]Tae-Hwan Oh, Ho-Young Lee, Ju-Hwa Kim, Ho-Jin Park, Kyoung-Ho Moon, Jae-Whui Kim, Hae-Seung Lee:
A 16b 10MS/s digitally self-calibrated ADC with time constant control. CICC 2008: 113-116 - 2007
- [j24]Lane Brooks, Hae-Seung Lee:
A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC. IEEE J. Solid State Circuits 42(12): 2677-2687 (2007) - [c7]Ho-Young Lee, Tae-Hwan Oh, Ho-Jin Park, Hae-Seung Lee, Mark Spaeth, Jae-Whui Kim:
A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration. CICC 2007: 313-316 - [c6]Albert Chow, Hae-Seung Lee:
Transient Noise Analysis for Comparator-Based Switched-Capacitor Circuits. ISCAS 2007: 953-956 - [c5]Lane Brooks, Hae-Seung Lee:
A Zero-Crossing-Based 8b 200MS/s Pipelined ADC. ISSCC 2007: 460-615 - 2006
- [j23]John Kenneth Fiorenza, Todd Sepke, Peter Holloway, Charles G. Sodini, Hae-Seung Lee:
Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies. IEEE J. Solid State Circuits 41(12): 2658-2668 (2006) - [c4]Todd Sepke, John Kenneth Fiorenza, Charles G. Sodini, Peter Holloway, Hae-Seung Lee:
Comparator-based switched-capacitor circuits for scaled CMOS technologies. ISSCC 2006: 812-821 - [c3]Jungwook Yang, Keith Fife, Lane Brooks, Charles G. Sodini, Andrew Betts, Pavan Mudunuru, Hae-Seung Lee:
A 3MPixel Low-Noise Flexible Architecture CMOS Image Sensor. ISSCC 2006: 2004-2013 - 2005
- [j22]Andrew R. Chen, Akintunde Ibitayo (Tayo) Akinwande, Hae-Seung Lee:
CMOS-based microdisplay with calibrated backplane. IEEE J. Solid State Circuits 40(12): 2746-2755 (2005) - 2004
- [j21]Susan Luschas, Richard Schreier, Hae-Seung Lee:
Radio frequency digital-to-analog converter. IEEE J. Solid State Circuits 39(9): 1462-1467 (2004) - [j20]Mark Shane Peng, Hae-Seung Lee:
Study of substrate noise and techniques for minimization. IEEE J. Solid State Circuits 39(11): 2080-2086 (2004) - 2003
- [c2]Susan Luschas, Richard Schreier, Hae-Seung Lee:
A 942 MHz output, 17.5 MHz bandwidth, -70dBc IMD3 ΣΔ DAC. CICC 2003: 131-134 - [c1]Susan Luschas, Hae-Seung Lee:
Output impedance requirements for DACs. ISCAS (1) 2003: 861-864 - 2002
- [j19]Ayman Shabra, Hae-Seung Lee:
Oversampled pipeline A/D converters with mismatch shaping. IEEE J. Solid State Circuits 37(5): 566-578 (2002) - [j18]John F. Bulzacchelli, Hae-Seung Lee, James A. Misewich, Mark B. Ketchen:
Superconducting bandpass ΔΣ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate. IEEE J. Solid State Circuits 37(12): 1695-1702 (2002) - 2001
- [j17]Kush Gulati, Hae-Seung Lee:
A low-power reconfigurable analog-to-digital converter. IEEE J. Solid State Circuits 36(12): 1900-1911 (2001) - 2000
- [j16]Kush Gulati, Hae-Seung Lee:
Corrections to "a high-swing CMOS telescopic operational amplifier". IEEE J. Solid State Circuits 35(1): 129 (2000)
1990 – 1999
- 1999
- [j15]Susanne A. Paul, Hae-Seung Lee, John Goodrich, Titiimaea F. Alailima, Daniel D. Santiago:
A Nyquist-rate pipelined oversampling A/D converter. IEEE J. Solid State Circuits 34(12): 1777-1787 (1999) - 1998
- [j14]Ignacio S. McQuirk, Berthold K. P. Horn, Hae-Seung Lee, John L. Wyatt Jr.:
Estimating the Focus of Expansion in Analog VLSI. Int. J. Comput. Vis. 28(3): 261-277 (1998) - [j13]David A. Martin, Hae-Seung Lee, Ichiro Masaki:
A mixed-signal array processor with early vision applications. IEEE J. Solid State Circuits 33(3): 497-502 (1998) - [j12]Kush Gulati, Hae-Seung Lee:
A high-swing CMOS telescopic operational amplifier. IEEE J. Solid State Circuits 33(12): 2010-2019 (1998) - 1996
- [j11]Paul C. Yu, Hae-Seung Lee:
A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC. IEEE J. Solid State Circuits 31(12): 1854-1861 (1996) - [j10]Susanne A. Paul, Hae-Seung Lee:
A 9-b charge-to-digital converter for integrated image sensors. IEEE J. Solid State Circuits 31(12): 1931-1938 (1996) - 1994
- [j9]Barry Thompson, Hae-Seung Lee, Lawrence M. DeVito:
A 300-MHz BiCMOS serial data transceiver. IEEE J. Solid State Circuits 29(3): 185-192 (1994) - [j8]Theodore L. Tewksbury, Hae-Seung Lee:
Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs. IEEE J. Solid State Circuits 29(3): 239-252 (1994) - [j7]Hae-Seung Lee:
A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC. IEEE J. Solid State Circuits 29(4): 509-515 (1994) - [j6]S. Nadeem, Charles G. Sodini, Hae-Seung Lee:
16-channel oversampled analog-to-digital converter. IEEE J. Solid State Circuits 29(9): 1077-1085 (1994) - 1992
- [j5]John L. Wyatt Jr., Craig Keast, Mark Seidel, David L. Standley, Berthold K. P. Horn, Tom Knight, Charles G. Sodini, Hae-Seung Lee, Tomaso A. Poggio:
Analog VLSI systems for image acquisition and fast early vision processing. Int. J. Comput. Vis. 8(3): 217-230 (1992)
1980 – 1989
- 1989
- [j4]Theodore L. Tewksbury, Hae-Seung Lee, Gerald A. Miller:
The effects of oxide traps on the large-signal transient response of analog MOS circuits. IEEE J. Solid State Circuits 24(2): 542-544 (1989) - [j3]Kurt M. Ware, Hae-Seung Lee, Charles G. Sodini:
A 200-MHz CMOS phase-locked loop with dual phase detectors. IEEE J. Solid State Circuits 24(6): 1560-1568 (1989) - 1988
- [j2]Benjamin J. McCarroll, Charles G. Sodini, Hae-Seung Lee:
A high-speed CMOS comparator for use in an ADC. IEEE J. Solid State Circuits 23(1): 159-165 (1988) - [j1]Joseph T. Kung, Hae-Seung Lee, Roger T. Howe:
A digital readout technique for capacitive sensor applications. IEEE J. Solid State Circuits 23(4): 972-977 (1988)
Coauthor Index
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