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ORCIDJavier D. Bruguera
Javier Diaz Bruguera
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2020 – today
- 2023
[j51]Javier D. Bruguera
:
Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units. IEEE Trans. Computers 72(10): 2990-3001 (2023)- 2022
- [c58]Javier D. Bruguera:
Low-Latency and High-Bandwidth Pipelined Radix-64 Division and Square Root Unit. ARITH 2022: 10-17 - [c57]David M. Russinoff, Javier D. Bruguera, Cuong Chau, Mayank Manjrekar, Nicholas Pfister, Harsha Valsaraju:
Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking. ARITH 2022: 120-126 - 2020
- [j50]Javier D. Bruguera:
Low Latency Floating-Point Division and Square Root Unit. IEEE Trans. Computers 69(2): 274-287 (2020)
2010 – 2019
- 2019
- [j49]Javier D. Bruguera, Florent de Dinechin:
Guest Editors Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 68(7): 951-952 (2019) - 2018
- [c56]Javier D. Bruguera:
Radix-64 Floating-Point Divider. ARITH 2018: 84-91 - 2017
- [e2]Neil Burgess, Javier D. Bruguera, Florent de Dinechin:
24th IEEE Symposium on Computer Arithmetic, ARITH 2017, London, United Kingdom, July 24-26, 2017. IEEE Computer Society 2017, ISBN 978-1-5386-1965-0 [contents] - 2016
- [j48]Lois Orosa, Javier D. Bruguera, Elisardo Antelo:
Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors. Comput. J. 59(10): 1453-1469 (2016) - [j47]E. G. Paredes, Margarita Amor, Montserrat Bóo, Javier D. Bruguera, Jürgen Döllner:
Hybrid terrain rendering based on the external edge primitive. Int. J. Geogr. Inf. Sci. 30(6): 1095-1116 (2016) - 2014
- [j46]Daniel Piso Fernandez, Javier D. Bruguera:
Obtaining Accurate Error Expressions and Bounds for Floating-Point Multiplicative Algorithms. Comput. J. 57(2): 319-331 (2014) - [j45]Javier D. Bruguera:
Optimizing the representation of intervals. Sci. Comput. Program. 90: 21-33 (2014) - [j44]Álvaro Vázquez, Elisardo Antelo, Javier D. Bruguera:
Fast Radix-10 Multiplication Using Redundant BCD Codes. IEEE Trans. Computers 63(8): 1902-1914 (2014) - [c55]Daniel Piso Fernandez, Javier Diaz Bruguera:
A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms. DSD 2014: 639-642 - 2013
- [j43]Álvaro Vázquez, Javier D. Bruguera:
Iterative Algorithm and Architecture for Exponential, Logarithm, Powering, and Root Extraction. IEEE Trans. Computers 62(9): 1721-1731 (2013) - [j42]Roberto R. Osorio, Javier D. Bruguera:
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. J. Signal Process. Syst. 72(2): 119-132 (2013) - 2012
- [j41]E. G. Paredes, Montserrat Bóo, Margarita Amor, Javier D. Bruguera, Jürgen Döllner:
Extended hybrid meshing algorithm for multiresolution terrain models. Int. J. Geogr. Inf. Sci. 26(5): 771-793 (2012) - [j40]Marc Daumas, Javier D. Bruguera:
8th Conference on Real Numbers and Computers. Inf. Comput. 216: 1-2 (2012) - [j39]Lois Orosa, Elisardo Antelo, Javier D. Bruguera:
FlexSig: Implementing flexible hardware signatures. ACM Trans. Archit. Code Optim. 8(4): 30:1-30:20 (2012) - [c54]E. G. Paredes, Montserrat Bóo, Margarita Amor, Jürgen Döllner, Javier D. Bruguera:
GPU-based Visualization of Hybrid Terrain Models. GRAPP/IVAPP 2012: 254-259 - 2011
- [j38]Javier D. Bruguera, Marius Cornea, Debjit Das Sarma:
Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 60(2): 145-147 (2011) - [j37]Daniel Piso Fernandez, Javier D. Bruguera:
Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate. IEEE Trans. Computers 60(11): 1535-1546 (2011) - [c53]Álvaro Vázquez, Javier D. Bruguera:
Composite Iterative Algorithm and Architecture for q-th Root Calculation. IEEE Symposium on Computer Arithmetic 2011: 52-61
2000 – 2009
- 2009
- [c52]Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera:
High Performance Image Processing on a Massively Parallel Processor Array. DSD 2009: 233-236 - [c51]Daniel Piso Fernandez, Javier D. Bruguera:
Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation. DSD 2009: 293-300 - [e1]Javier D. Bruguera, Marius Cornea, Debjit Das Sarma, John Harrison:
19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009. IEEE Computer Society 2009, ISBN 978-0-7695-3670-5 [contents] - 2008
- [j36]Alex Piñeiro, Javier D. Bruguera, Fabrizio Lamberti, Paolo Montuschi:
A Radix-2 Digit-by-Digit Architecture for Cube Root. IEEE Trans. Computers 57(4): 562-566 (2008) - [c50]Daniel Piso Fernandez, Javier D. Bruguera:
Forcing one-sided results in Goldschmidt algorithm. ACSCC 2008: 1830-1833 - [c49]Roberto R. Osorio, Javier D. Bruguera:
An FPGA architecture for CABAC decoding in manycore systems. ASAP 2008: 293-298 - [c48]Daniel Piso Fernandez, Javier D. Bruguera:
A New Rounding Algorithm for Variable Latency Division and Square Root Implementations. DSD 2008: 760-767 - [c47]Hans-Joachim Bungartz, Javier D. Bruguera, Peter Arbenz, Bruce Hendrickson:
Topic 10: Parallel Numerical Algorithms. Euro-Par 2008: 778-779 - 2007
- [j35]F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera:
Hardware support for adaptive tessellation of Bézier surfaces based on local tests. J. Syst. Archit. 53(4): 233-250 (2007) - [j34]Paolo Montuschi, Javier D. Bruguera, Luigi Ciminiera, José-Alejandro Piñeiro:
A Digit-by-Digit Algorithm for mth Root Extraction. IEEE Trans. Computers 56(12): 1696-1706 (2007) - [c46]Roberto R. Osorio, Javier D. Bruguera:
Entropy Coding on a Programmable Processor Array for Multimedia SoC. ASAP 2007: 222-227 - 2006
- [j33]Roberto R. Osorio, Javier D. Bruguera:
High-Throughput Architecture for H.264/AVC CABAC Compression System. IEEE Trans. Circuits Syst. Video Technol. 16(11): 1376-1384 (2006) - [c45]Viay Holimath, Javier D. Bruguera:
A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. DSD 2006: 236-239 - [c44]Roberto R. Osorio, Javier D. Bruguera:
A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. DSD 2006: 269-274 - [c43]Javier D. Bruguera, Roberto R. Osorio:
A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. DSD 2006: 407-414 - 2005
- [j32]José-Alejandro Piñeiro, Stuart F. Oberman, Jean-Michel Muller, Javier D. Bruguera:
High-Speed Function Approximation Using a Minimax Quadratic Interpolator. IEEE Trans. Computers 54(3): 304-318 (2005) - [j31]José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera:
High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. J. VLSI Signal Process. 40(1): 109-123 (2005) - [c42]Javier D. Bruguera, Tomás Lang:
Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. IEEE Symposium on Computer Arithmetic 2005: 42-51 - [c41]Roberto R. Osorio, Javier D. Bruguera:
A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. DSD 2005: 298-305 - [c40]F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera:
Adaptive Tessellation of Bezier Surfaces Based on Displacement Maps. WSCG (Short Papers) 2005: 29-32 - 2004
- [j30]Tomás Lang, Javier D. Bruguera:
Floating-Point Multiply-Add-Fused with Reduced Latency. IEEE Trans. Computers 53(8): 988-1003 (2004) - [j29]José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera:
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. IEEE Trans. Computers 53(9): 1085-1096 (2004) - [c39]Roberto R. Osorio, Javier D. Bruguera:
Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. DSD 2004: 62-69 - [c38]Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera:
Algorithms and Hardware for Data Compression in Point Rendering Applications. WSCG (Short Papers) 2004: 173-180 - 2003
- [j28]Juan Touriño, Jorge Parapar, Ramon Doallo, Marcos Boullón, Francisco F. Rivera, Javier D. Bruguera, Xesús P. González, Rafael Crecente, Carlos Álvarez:
Research Article: A GIS-embedded system to support land consolidation plans in Galicia. Int. J. Geogr. Inf. Sci. 17(4): 377-396 (2003) - [j27]Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera:
Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. J. Syst. Archit. 49(12-15): 543-555 (2003) - [j26]María J. Martín, David E. Singh, José Carlos Mouriño, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera:
High performance air pollution modeling for a power plant environment. Parallel Comput. 29(11-12): 1763-1790 (2003) - [j25]Javier D. Bruguera, Tomás Lang:
Multilevel Reverse-Carry Addition: Single and Dual Adders. J. VLSI Signal Process. 33(1-2): 55-74 (2003) - [c37]José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera:
High-Radix Iterative Algorithm for Powering Computation. IEEE Symposium on Computer Arithmetic 2003: 204-211 - [c36]José-Alejandro Piñeiro, Javier D. Bruguera, Milos D. Ercegovac:
On-line high-radix exponential with selection by rounding. ISCAS (4) 2003: 121-124 - [c35]F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera:
Adaptive Tessellation of NURBS Surfaces. WSCG 2003 - 2002
- [j24]José-Alejandro Piñeiro, Javier D. Bruguera:
High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root. IEEE Trans. Computers 51(12): 1377-1388 (2002) - [c34]Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera:
Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes. 3DPVT 2002: 380-383 - [c33]José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera:
High-Radix Logarithm with Selection by Rounding. ASAP 2002: 101-110 - [c32]Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera:
Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. DSD 2002: 218-225 - [c31]Ángel del Río, Montserrat Bóo, Margarita Amor, Javier D. Bruguera:
Hardware Implementation of the Subdivision Loop Algorithm. EUROMICRO 2002: 189-199 - [c30]José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera:
Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. ICCD 2002: 132-137 - [c29]Tomás Lang, Javier D. Bruguera:
Floating-Point Fused Multiply-Add with Reduced Latency. ICCD 2002: 145- - 2001
- [j23]Javier D. Bruguera, Tomás Lang:
Multilevel reverse most-significant carry computation. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 959-962 (2001) - [c28]José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller:
Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. IEEE Symposium on Computer Arithmetic 2001: 40- - [c27]Javier D. Bruguera, Tomás Lang:
Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. IEEE Symposium on Computer Arithmetic 2001: 203-210 - [c26]José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller:
FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. DSD 2001: 262-269 - [c25]Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera:
Implementation of a NURBS to Bézier Conversor with Constant Latency. FPL 2001: 213-222 - [c24]Juan Touriño, Francisco F. Rivera, Carlos Álvarez, Cesar M. Dans, Jorge Parapar, Ramon Doallo, Marcos Boullón, Javier D. Bruguera, Rafael Crecente, Xesús P. González:
COPA: a GIS-based Tool for Land Consolidation Projects. ACM-GIS 2001: 53-58 - [c23]José Carlos Mouriño, David E. Singh, María J. Martín, J. M. Eiroa, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera:
Parallelization of the STEM-II Air Quality Model. HPCN Europe 2001: 543-546 - [c22]José Carlos Mouriño, María J. Martín, Ramon Doallo, David E. Singh, Francisco F. Rivera, Javier D. Bruguera:
The STEM-II Air Quality Model on a Distributed Memory System. ICPP Workshops 2001: 85-92 - 2000
- [j22]Elisardo Antelo, Tomás Lang, Javier D. Bruguera:
Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. IEEE Trans. Computers 49(7): 727-739 (2000) - [j21]Elisardo Antelo, Tomás Lang, Javier D. Bruguera:
Very-High Radix CORDIC Rotation Based on Selection by Rounding. J. VLSI Signal Process. 25(2): 141-153 (2000) - [c21]Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera:
Parallel Architecture for Conversion of NURBS Curves to Bézier Curves. EUROMICRO 2000: 1324-1331 - [c20]Roberto R. Osorio, Javier D. Bruguera:
Architectures for arithmetic coding in image compression. EUSIPCO 2000: 1-4 - [c19]Javier D. Bruguera, Tomás Lang:
Multilevel Reverse-Carry Adder. ICCD 2000: 155-162 - [c18]Carlos E. Cabrera Reyes, Javier D. Bruguera:
VLSI systolic array architecture for the lattice structure of the discrete wavelet transform. ISCAS 2000: 605-608
1990 – 1999
- 1999
- [j20]Javier D. Bruguera, Tomás Lang:
Leading-One Prediction with Concurrent Position Correction. IEEE Trans. Computers 48(10): 1083-1097 (1999) - [c17]Elisardo Antelo, Tomás Lang, Javier D. Bruguera:
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. IEEE Symposium on Computer Arithmetic 1999: 204- - [c16]Tomás Lang, Javier D. Bruguera:
Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. ICCD 1999: 73-79 - [c15]Roberto R. Osorio, Javier D. Bruguera:
New model for arithmetic coding/decoding of multilevel images based on a cache memory. ICECS 1999: 697-700 - 1998
- [j19]Elisardo Antelo, Tomás Lang, Javier D. Bruguera:
Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. IEEE Trans. Computers 47(2): 152-161 (1998) - [j18]Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata:
A novel design of a two operand normalization circuit. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 173-176 (1998) - [j17]Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
Radix-4 Vectoring CORDIC Algorithm and Architectures. J. VLSI Signal Process. 19(2): 127-147 (1998) - [c14]Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera:
Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. EUROMICRO 1998: 10139- - [c13]Javier D. Bruguera, Tomás Lang:
Leading-one prediction scheme for latency improvement in single datapath floating-point adders. ICCD 1998: 298-305 - 1997
- [j16]Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata:
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers 46(8): 855-870 (1997) - [j15]Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Emilio L. Zapata:
Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. IEEE Trans. Computers 46(11): 1264-1271 (1997) - [j14]Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata:
High-performance VLSI architecture for the Viterbi algorithm. IEEE Trans. Commun. 45(2): 168-176 (1997) - [j13]Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata:
Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures. J. VLSI Signal Process. 17(1): 57-73 (1997) - [c12]Roberto R. Osorio, Javier D. Bruguera:
New arithmetic coder/decoder architectures based on pipelining. ASAP 1997: 106-115 - [c11]Mercedes Peón, Roberto R. Osorio, Javier D. Bruguera:
A VLSI implementation of an arithmetic coder for image compression. EUROMICRO 1997: 591- - [c10]Carlos Cabrera, Montserrat Bóo, Javier D. Bruguera:
VLSI implementation of an area-efficient architecture for the Viterbi algorithm. ICASSP 1997: 623-626 - 1996
- [j12]Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata:
Unified Mixed Radix 2-4 Redundant CORDIC Processor. IEEE Trans. Computers 45(9): 1068-1073 (1996) - [j11]Javier D. Bruguera, Nicolás Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata:
Cordic based parallel/pipelined architecture for the Hough transform. J. VLSI Signal Process. 12(3): 207-221 (1996) - [c9]Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP 1996: 55-64 - [c8]Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata:
High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. ASAP 1996: 165- - [c7]Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata:
High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II 1996: 155-164 - [c6]Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata:
High performance VLSI architecture for the trellis coded quantization. ICIP (2) 1996: 995-998 - 1995
- [j10]Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata:
A Parallel Architecture for the Self-Sorting FFT Algorithm. J. Parallel Distributed Comput. 31(1): 88-97 (1995) - [c5]Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata:
Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic 1995: 172-179 - [c4]Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata:
Digit On-line Large Radix CORDIC Rotator. ASAP 1995: 246-257 - [c3]Julio Villalba, José Antonio Hidalgo López, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP 1995: 258-269 - [c2]Javier D. Bruguera, Tomás Lang:
2-D DCT using on-line arithmetic. ICASSP 1995: 3275-3278 - 1994
- [j9]Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata:
Parallel Architecture for Fast Transforms with Trigonometric Kernel. IEEE Trans. Parallel Distributed Syst. 5(10): 1091-1099 (1994) - 1993
- [j8]Javier D. Bruguera, Elisardo Antelo, Emilio L. Zapata:
Design of a Pipelined Radix 4 CORDIC Processor. Parallel Comput. 19(7): 729-744 (1993) - 1992
- [j7]Emilio L. Zapata, Ignacio Benavides, Francisco F. Rivera, Javier D. Bruguera, Tomás F. Pena, José María Carazo:
Image reconstruction on hypercube computers: Application to electron microscopy. Signal Process. 27(1): 51-64 (1992) - 1991
- [c1]Francisco Argüello, Ramon Doallo, Javier D. Bruguera, Emilio L. Zapata:
Design of a constant geometry fast Hartley transformer. ICASSP 1991: 1137-1140 - 1990
- [j6]Oscar G. Plata, Javier D. Bruguera, Francisco F. Rivera, Ramon Doallo, Emilio L. Zapata:
ACLE: A Software Package for SIMD Computer Simulation. Comput. J. 33(3): 194-203 (1990) - [j5]Javier D. Bruguera, Emilio L. Zapata, Oscar G. Plata:
A reliability model for multiprocessor networks with degradable nodes. Microprocessing and Microprogramming 29(1): 15-25 (1990) - [j4]Emilio L. Zapata, Francisco Argüello, Francisco Fernandez Rivera, Javier D. Bruguera:
Multidimensional fast Hartley transform onto SIMD hypercubes. Microprocessing and Microprogramming 29(2): 121-134 (1990) - [j3]Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera, Emilio L. Zapata, Richard L. Peskin:
Gaussian elimination with pivoting on hypercubes. Parallel Comput. 14(1): 51-60 (1990) - [j2]Inmaculada García, Juan Julián Merelo Guervós, Javier D. Bruguera, Emilio L. Zapata:
Parallel quadrant interlocking factorization on hypercube computers. Parallel Comput. 15(1-3): 87-100 (1990)
1980 – 1989
- 1989
- [j1]Emilio L. Zapata, Javier D. Bruguera, Oscar G. Plata, Francisco F. Rivera:
A parallel markovian model reliability algorithm for hypercube networks. Microprocessing and Microprogramming 27(1-5): 501-508 (1989)
Coauthor Index
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