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2020 – today

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2024
[j26]
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Kevin Kai-Chun Chang, Guan-Ting Liu, Chun-Yao Chiang, Pei-Yu Lee, Iris Hui-Ru Jiang:
Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 2840-2853 (2024)
[j25]
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Kai-En Lin, Kuan-Chun Wang, Yu-Heng Chen, Li-Heng Lin, Ying-Hua Lee, Chung-Wei Lin, Iris Hui-Ru Jiang:
Graph-Based Deadlock Analysis and Prevention for Robust Intelligent Intersection Management. ACM Trans. Cyber Phys. Syst. 8(3): 33:1-33:22 (2024)
[c85]
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Yen-Yu Chen, Hao-Yu Wu, Iris Hui-Ru Jiang, Cheng-Hong Tsai, Chien-Cheng Wu:
Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops. ISPD 2024: 21-29
[c84]
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Wei-Chen Tai, Min-Hsien Chung, Iris Hui-Ru Jiang:
Novel Airgap Insertion and Layer Reassignment for Timing Optimization Guided by Slack Dependency. ISPD 2024: 41-49
[c83]
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Chien-Pang Lu, Iris Hui-Ru Jiang, Chung-Ching Peng, Mohd Mawardi Mohd Razha, Alessandro Uber:
Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization. ISPD 2024: 205-212
[e2]
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Iris Hui-Ru Jiang, Gracieli Posser:
Proceedings of the 2024 International Symposium on Physical Design, ISPD 2024, Taipei, Taiwan, March 12-15, 2024. ACM 2024 [contents]
2023
[j24]
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Iris Hui-Ru Jiang, David G. Chinnery, Gracieli Posser, Jens Lienig:
Introduction to the Special Section on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. 28(5): 68:1-68:3 (2023)
[c82]
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Iris Hui-Ru Jiang:
Lightning Talk: All Routes to Timing Closure. DAC 2023: 1-2
[c81]
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Iris Hui-Ru Jiang, David G. Chinnery:
EDA for Domain Specific Computing: An Introduction for the Panel. ISPD 2023: 205
[e1]
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David G. Chinnery, Iris Hui-Ru Jiang:
Proceedings of the 2023 International Symposium on Physical Design, ISPD 2023, Virtual Event, USA, March 26-29, 2023. ACM 2023, ISBN 978-1-4503-9978-4 [contents]
2022
[c80]
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Kevin Kai-Chun Chang, Chun-Yao Chiang, Pei-Yu Lee, Iris Hui-Ru Jiang:
Timing macro modeling with graph neural networks. DAC 2022: 1219-1224
[c79]
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Tsung-Lin Tsou, Chung-Wei Lin, Iris Hui-Ru Jiang:
Deadlock Analysis and Prevention for Intersection Management Based on Colored Timed Petri Nets. DATE 2022: 124-127
[c78]
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Yen-Shuo Chen, Iris Hui-Ru Jiang:
Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering. DATE 2022: 604-607
[c77]
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Guan-Ting Liu, Wei-Chen Tai, Yi-Ting Lin, Iris Hui-Ru Jiang, James P. Shiely, Pu-Jen Cheng:
Sub-Resolution Assist Feature Generation with Reinforcement Learning and Transfer Learning. ICCAD 2022: 29:1-29:9
[c76]
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Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang:
Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines. ISPD 2022: 13-20
[c75]
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Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen:
Intelligent Design Automation for Heterogeneous Integration. ISPD 2022: 105-106
[c74]
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Li-Heng Lin, Kuan-Chun Wang, Ying-Hua Lee, Kai-En Lin, Chung-Wei Lin, Iris Hui-Ru Jiang:
Deadlock Resolution for Intelligent Intersection Management with Changeable Trajectories. IV 2022: 573-579
2021
[j23]
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Yi-Ting Lin, Iris Hui-Ru Jiang:
Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1909-1919 (2021)
[j22]
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Wei Li, Yuzhe Ma, Qi Sun, Lu Zhang, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open-Source Layout Decomposer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2331-2344 (2021)
[c73]
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Sean Shang-En Tseng, Iris Hui-Ru Jiang, James P. Shiely:
Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval. DAC 2021: 181-186
[c72]
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Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo:
DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. ICCAD 2021: 1-6
[c71]
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Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Opportunities for 2.5/3D Heterogeneous SoC Integration. VLSI-DAT 2021: 1
[c70]
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Shang-Chien Lin, Chia-Chu Kung, Lee Lin, Chung-Wei Lin, Iris Hui-Ru Jiang:
Efficient Mandatory Lane Changing of Connected and Autonomous Vehicles. VTC Fall 2021: 1-7
2020
[j21]
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Wei-Chun Chang, Iris Hui-Ru Jiang:
iClaire: A Fast and General Layout Pattern Classification Algorithm With Clip Shifting and Centroid Recreation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1662-1673 (2020)
[c69]
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Sheng-Jung Yu, Chen-Chien Kao, Chia-Han Huang, Iris Hui-Ru Jiang:
Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability. ASP-DAC 2020: 133-138
[c68]
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Hsien-Han Cheng, Iris Hui-Ru Jiang, Oscar Ou:
Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures. DAC 2020: 1-6
[c67]
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Tung-Wei Lin, Wei-Chen Tai, Yu-Cheng Lin, Iris Hui-Ru Jiang:
Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA Systems. DAC 2020: 1-6
[c66]
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Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang:
Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization. DAC 2020: 1-2
[c65]
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Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo:
DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. ICCAD 2020: 71:1-71:6
[c64]
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Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. ICCAD 2020: 125:1-125:7
[c63]
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Xuan-Xue Huang, Hsien-Chia Chen, Sheng-Wei Wang, Iris Hui-Ru Jiang, Yih-Chih Chou, Cheng-Hong Tsai:
Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance. ICCAD 2020: 156:1-156:9
[c62]
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  - conf/ivs/LinHLLJL20
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Shang-Chien Lin, Hsiang Hsu, Yi-Ting Lin, Chung-Wei Lin, Iris Hui-Ru Jiang, Changliu Liu:
A Dynamic Programming Approach to Optimal Lane Merging of Connected and Autonomous Vehicles. IV 2020: 349-356

2010 – 2019

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2019
[j20]
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  - journals/tecs/LinHLLJL19
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Yi-Ting Lin, Hsiang Hsu, Shang-Chien Lin, Chung-Wei Lin, Iris Hui-Ru Jiang, Changliu Liu:
Graph-Based Modeling, Scheduling, and Verification for Intersection Management of Intelligent Vehicles. ACM Trans. Embed. Comput. Syst. 18(5s): 95:1-95:21 (2019)
[c61]
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Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer: Invited Paper. ASICON 2019: 1-4
[c60]
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Yi-Ting Lin, Iris Hui-Ru Jiang:
Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials. DAC 2019: 151
[c59]
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Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo:
DATC RDF-2019: Towards a Complete Academic Reference Design Flow. ICCAD 2019: 1-6
[c58]
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Ya-Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang, Gi-Joon Nam:
Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing. ISPD 2019: 11-18
[c57]
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Hua-Yu Chang, Iris Hui-Ru Jiang:
Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement. ISPD 2019: 93-100
2018
[j19]
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Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin:
OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1825-1838 (2018)
[j18]
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Pei-Yu Lee, Iris Hui-Ru Jiang:
iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis. ACM Trans. Design Autom. Electr. Syst. 23(4): 48:1-48:21 (2018)
[c56]
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Pei-Yu Lee, Iris Hui-Ru Jiang, Tung-Chieh Chen:
FastPass: Fast timing path search for generalized timing exception handling. ASP-DAC 2018: 172-177
[c55]
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Chien-Pang Lu, Iris Hui-Ru Jiang:
COSAT: congestion, obstacle, and slew aware tree construction for multiple power domain design. DAC 2018: 47:1-47:6
[c54]
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Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam:
DATC RDF: an academic flow from logic synthesis to detailed routing. ICCAD 2018: 37
[c53]
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Iris Hui-Ru Jiang, Hua-Yu Chang:
Recent Research and Challenges in Multiple Patterning Layout Decomposition. ISVLSI 2018: 498-499
[c52]
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Iris Hui-Ru Jiang, Pei-Yu Lee:
Timing Macro Modeling for Efficient Hierarchical Timing Analysis. ISVLSI 2018: 714
[i2]
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Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer. CoRR abs/1809.07554 (2018)
[i1]
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Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam:
DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing. CoRR abs/1810.01078 (2018)
2017
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Iris Hui-Ru Jiang, Hua-Yu Chang:
Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 2080-2092 (2017)
[c51]
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Wei-Chun Chang, Iris Hui-Ru Jiang, Yen-Ting Yu, Wei-Fang Liu:
iClaire: A Fast and General Layout Pattern Classification Algorithm. DAC 2017: 64:1-64:6
[c50]
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Wei-Lun Chiu, Iris Hui-Ru Jiang, Chien-Pang Lu, Yu-Tung Chang:
Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation. DAC 2017: 64:1-64:6
[c49]
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Chien-Pang Lu, Iris Hui-Ru Jiang:
Fast low power rule checking for multiple power domain design. DATE 2017: 1745-1750
[c48]
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Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, Gi-Joon Nam:
DATC RDF: Robust design flow database: Invited paper. ICCAD 2017: 872-873
[c47]
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Pei-Yu Lee, Iris Hui-Ru Jiang, Ting-You Yang:
iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis. ISPD 2017: 83-89
2016
[j16]
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Chang Xu, Guojie Luo, Peixin Li, Yiyu Shi, Iris Hui-Ru Jiang:
Analytical Clustering Score with Application to Postplacement Register Clustering. ACM Trans. Design Autom. Electr. Syst. 21(3): 41:1-41:18 (2016)
[c46]
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Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li:
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. ASP-DAC 2016: 705-711
[c45]
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Hua-Yu Chang, Iris Hui-Ru Jiang:
Multiple patterning layout decomposition considering complex coloring rules. DAC 2016: 40:1-40:6
[c44]
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An-Che Cheng, Iris Hui-Ru Jiang, Jing-Yang Jou:
Resource-aware functional ECO patch generation. DATE 2016: 1036-1041
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Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin:
OWARU: free space-aware timing-driven incremental placement. ICCAD 2016: 8
[c42]
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Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, Yih-Lang Li:
OpenDesign flow database: the infrastructure for VLSI design and design automation research. ICCAD 2016: 42
2015
[j15]
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Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir A. Jamsek, Gi-Joon Nam:
Feature detection for image analytics via FPGA acceleration. IBM J. Res. Dev. 59(2/3) (2015)
[j14]
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Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles C. Chiang:
Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 460-470 (2015)
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Yu-Ming Yang, King Ho Tam, Iris Hui-Ru Jiang:
Criticality-dependency-aware timing characterization and analysis. DAC 2015: 167:1-167:6
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Chien-Pang Lu, Iris Hui-Ru Jiang, Chin-Hsiung Hsu:
GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design. ICCAD 2015: 861-866
[c39]
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Pei-Yu Lee, Iris Hui-Ru Jiang, Cheng-Ruei Li, Wei-Lun Chiu, Yu-Ming Yang:
iTimerC 2.0: Fast Incremental Timing and CPPR Analysis. ICCAD 2015: 890-894
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Chang Xu, Peixin Li, Guojie Luo, Yiyu Shi, Iris Hui-Ru Jiang:
Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging. ISPD 2015: 93-100
2014
[j13]
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Yu-Ming Yang, Iris Hui-Ru Jiang, Sung-Ting Ho:
PushPull: Short-Path Padding for Timing Error Resilient Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 558-570 (2014)
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An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou:
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. ACM Trans. Design Autom. Electr. Syst. 20(1): 7:1-7:23 (2014)
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Functional ECO Using Metal-Configurable Gate-Array Spare Cells. DAC 2014: 191:1-191:6
[c36]
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Yen-Ting Yu, Iris Hui-Ru Jiang, Yumin Zhang, Charles C. Chiang:
DRC-based hotspot detection considering edge tolerance and incomplete specification. ICCAD 2014: 101-107
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Iris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, Jin-Fu Li:
The overview of 2014 CAD contest at ICCAD. ICCAD 2014: 356
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Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes:
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations. ICCAD 2014: 382-388
[c33]
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Yu-Ming Yang, Yu-Wei Chang, Iris Hui-Ru Jiang:
iTimerC: common path pessimism removal using effective reduction methods. ICCAD 2014: 600-605
2013
[j11]
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Chih-Long Chang, Iris Hui-Ru Jiang:
Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 242-246 (2013)
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
ECO Optimization Using Metal-Configurable Gate-Array Spare Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1722-1733 (2013)
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Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles C. Chiang:
Machine-learning-based hotspot detection using topological classification and critical feature extraction. DAC 2013: 67:1-67:6
[c31]
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Iris Hui-Ru Jiang, Zhuo Li, Hwei-Tseng Wang, Natarajan Viswanathan:
The overview of 2013 CAD contest at ICCAD. ICCAD 2013: 264
[c30]
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Yu-Ming Yang, Iris Hui-Ru Jiang, Sung-Ting Ho:
PushPull: short path padding for timing error resilient circuits. ISPD 2013: 50-57
[c29]
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Chang-Cheng Tsai, Yiyu Shi, Guojie Luo, Iris Hui-Ru Jiang:
FF-bond: multi-bit flip-flop bonding at placement. ISPD 2013: 147-153
2012
[j9]
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Wan-Yu Lee, Iris Hui-Ru Jiang, Tsung-Wan Mei:
Generic Integer Linear Programming Formulation for 3D IC Partitioning. J. Inf. Sci. Eng. 28(6): 1129-1144 (2012)
[j8]
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Iris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang:
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 192-204 (2012)
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1857-1866 (2012)
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Jing-Wei Lin, Tsung-Yi Ho, Iris Hui-Ru Jiang:
Reliability-Driven Power/Ground Routing for Analog ICs. ACM Trans. Design Autom. Electr. Syst. 17(1): 6:1-6:26 (2012)
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Iris Hui-Ru Jiang, Hua-Yu Chang:
ECOS: Stable Matching Based Metal-Only ECO Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 485-497 (2012)
[j4]
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Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang:
WiT: Optimal Wiring Topology for Electromigration Avoidance. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 581-592 (2012)
[c28]
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Timing ECO optimization using metal-configurable gate-array spare cells. DAC 2012: 802-807
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Yen-Ting Yu, Ya-Chung Chan, Subarna Sinha, Iris Hui-Ru Jiang, Charles C. Chiang:
Accurate process-hotspot detection using critical design rule extraction. DAC 2012: 1167-1172
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Iris Hui-Ru Jiang, Zhuo Li, Yih-Lang Li:
Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. ICCAD 2012: 341
[c25]
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Chih-Long Chang, Iris Hui-Ru Jiang, Yu-Ming Yang, Evan Y.-W. Tsai, Aki S.-H. Chen:
Novel pulsed-latch replacement based on time borrowing and spiral clustering. ISPD 2012: 121-128
2011
[c24]
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Simultaneous functional and timing ECO. DAC 2011: 140-145
[c23]
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Timing ECO optimization via Bézier curve smoothing and fixability identification. ICCAD 2011: 742-746
[c22]
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Iris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang, Evan Y.-W. Tsai, Lancer S.-F. Chen:
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs. ISPD 2011: 115-122
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Cheng-Chi Chan, Yen-Ting Yu, Iris Hui-Ru Jiang:
3DICE: 3D IC cost evaluation based on fast tier number estimation. ISQED 2011: 50-55
2010
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Iris Hui-Ru Jiang, Hua-Yu Chang:
Live Demo: ECOS 1.0: A metal-only ECO synthesizer. ISCAS 2010: 2774
[c19]
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Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang:
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. ISPD 2010: 177-184
[c18]
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Yu-Ming Yang, Iris Hui-Ru Jiang:
Analog placement and global routing considering wiring symmetry. ISQED 2010: 618-623
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Houng-Yi Li, Iris Hui-Ru Jiang, Hung-Ming Chen:
Simultaneous voltage island generation and floorplanning. SoCC 2010: 219-223

2000 – 2009

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2009
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Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung:
Matching-based minimum-cost spare cell selection for design changes. DAC 2009: 408-411
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Wan-Yu Lee, Iris Hui-Ru Jiang:
VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power. ACM Great Lakes Symposium on VLSI 2009: 39-44
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Iris Hui-Ru Jiang, Ming-Hua Wu:
POSA: Power-state-aware Buffered Tree Construction. ISCAS 2009: 787
[c13]
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Iris Hui-Ru Jiang:
Generic integer linear programming formulation for 3D IC partitioning. SoCC 2009: 321-324
2008
[c12]
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Iris Hui-Ru Jiang, Ming-Hua Wu:
Power-state-aware buffered tree construction. ICCD 2008: 21-26
[c11]
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Iris Hui-Ru Jiang, Yen-Ting Yu:
Configurable rectilinear Steiner tree construction for SoC and nano technologies. ICCD 2008: 34-39
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Iris Hui-Ru Jiang, Shung-Wei Lin, Yen-Ting Yu:
Unification of obstacle-avoiding rectilinear Steiner tree construction. SoCC 2008: 127-130
2006
[j3]
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Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou:
Reliable crosstalk-driven interconnect optimization. ACM Trans. Design Autom. Electr. Syst. 11(1): 88-103 (2006)
[c9]
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Ming-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, Iris Hui-Ru Jiang:
Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design. SoCC 2006: 211-214
2004
[j2]
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Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floor plan and buffer-block optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 694-703 (2004)
2003
[c8]
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Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floorplanning and buffer block planning. ASP-DAC 2003: 431-434
2002
[c7]
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Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang:
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. ISQED 2002: 523-528
2001
[c6]
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Li-An Sung, Iris Hui-Ru Jiang, Yoh-Wen Chang, Jing-Yang Jou, Jiin-Chuan Wu, Tai-Sheng Feng:
On placement and routing of wafer scale memory. ICECS 2001: 883-887
2000
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Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou:
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 999-1010 (2000)
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Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou:
Optimal reliable crosstalk-driven interconnect optimization. ISPD 2000: 128-133

1990 – 1999

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1999
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Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang:
Hierarchical Floorplan Design on the Internet. ASP-DAC 1999: 189-192
[c3]
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Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang:
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. DAC 1999: 90-95
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Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang:
A clustering- and probability-based approach for time-multiplexed FPGA partitioning. ICCAD 1999: 364-369
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Jie-Hong Roland Jiang, Iris Hui-Ru Jiang:
Optimum loading dispersion for high-speed tree-type decision circuitry. ICCAD 1999: 520-525

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