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ORCIDESSDERC 2012: Bordeaux, France
- Proceedings of the 2012 European Solid-State Device Research Conference, ESSDERC 2012, Bordeaux, France, September 17-21, 2012. IEEE 2012, ISBN 978-1-4673-1707-8
Joint ESSDERC/ESSCIRC Plenaries
- Kinam Kim:
Future silicon technology. 1-6 - Maurizio Zuffada:
The industrialization of the Silicon Photonics: Technology road map and applications. 7-13 - Nan Sun, Yong Liu, Ling Qin, Guangyu Xu
, Donhee Ham:
Solid-state and biological systems interface. 14-17 - Liam Madden, Ephrem Wu, Namhoon Kim, Bahareh Banijamali, Khaldoon Abugharbieh, Suresh Ramalingam, Xin Wu:
Advancing high performance heterogeneous integration through die stacking. 18-24 - Max Christian Lemme:
Graphene for microelectronics: Can it make a difference? 25-27
ESSDERC Plenaries
- Sandip Tiwari:
Nanostructure devices for logic and memory and beyond. 28-35 - Behtash Behin-Aein, Angik Sarkar, Supriyo Datta:
Modeling circuits with spins and magnets for all-spin logic. 36-40 - Hagen Klauk:
Organic complementary circuits - Scaling towards low voltage and submicron channel length. 41-45
Joint ESSDERC/ESSCIRC Session on Compact Modeling
- Yogesh Singh Chauhan, Sriramkumar Venugopalan, Mohammed A. Karim, Sourabh Khandelwal, Navid Paydavosi, Pankaj Thakur, Ali M. Niknejad, Chenming Hu:
BSIM - Industry standard compact MOSFET models. 30-33 - Maria-Anna Chalkiadaki, Anurag Mangla, Christian C. Enz, Yogesh Singh Chauhan, Mohammed Ahosan Ul Karim, Sriramkumar Venugopalan, Ali M. Niknejad, Chenming Hu:
Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology. 34-37 - Benjamin Dormieu, Patrick Scheer, Clement Charbuillet, Sebastien Jan, François Danneville:
4-Port isolated MOS modeling and extraction for mmW applications. 38-41
Joint ESSDERC/ESSCIRC Session on Variablity / Reliability
- Tobias Gemmeke, Maryam Ashouei:
Variability aware cell library optimization for reliable sub-threshold operation. 42-45 - Bertrand Ardouin, Jean-Yves Dupuy, Jean Godin, Virginie Nodjiadjim, Muriel Riet, François Marc, Gilles Amadou Koné, Sudip Ghosh, Brice Grandchamp, Cristell Maneux:
Advancements on reliability-aware analog circuit design. 46-52
High Mobility Devices
- Marc Belleville, Olivier Thomas, Alexandre Valentian, Fabien Clermidy:
Design challenges for nano-scale devices. 69-72 - Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Hiroshi Iwai, Gérard Ghibaudo, Gilles Reimbold:
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs. 73-76 - Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells. 77-80
High-k Dielectrics and Applications
- Yukinori Morita, Shinji Migita, Wataru Mizubayashi, Meishoku Masahara, Hiroyuki Ota:
Two-step annealing effects on ultrathin EOT higher-k (k = 40) ALD-HfO2 gate stacks. 81-84 - Akira Wada, Seiji Samukawa, Rui Zhang, Shinichi Takagi:
Thin germanium dioxide film with a high quality interface formed in a direct neutral beam oxidation process. 85-88 - Takamasa Kawanago, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo Hattori, Hiroshi Iwai:
(100)- and (110)-oriented nMOSFETs with highly scaled EOT in La-silicate/Si interface for multi-gate architecture. 89-92 - Maziar M. Naiini, Christoph Henkel, B. Gunnar Malm, Mikael Östling:
CMOS compatible ALD high-k double slot grating couplers for on-chip optical interconnects. 93-96
Emerging Device Modeling
- Carlo Jacoboni, Enrico Piccinini, Fabrizio Buscemi:
Transport in amorphous materials with applications to phase-change memories. 97-100 - K. C. Kwong, Philip K. T. Mok, Mansun Chan:
Geometry based resistance model for phase change memory. 101-104 - Elena Gnani, Susanna Reggiani, Antonio Gnudi, Giorgio Baccarani:
Drain-conductance optimization in nanowire TFETs. 105-108
Variability
- Salvatore M. Amoroso, Louis Gerrer, Stanislav Markov, Fikru Adamu-Lema, Asen Asenov:
Comprehensive statistical comparison of RTN and BTI in deeply scaled MOSFETs by means of 3D 'atomistic' simulation. 109-112 - Xingsheng Wang, Binjie Cheng, Andrew R. Brown, Campbell Millar, Asen Asenov:
Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design. 113-116 - Valentina Bonfiglio, Giuseppe Iannaccone:
Sensitivity-based investigation of threshold voltage variability in 32-nm flash memory cells. 117-120
Advanced FETs
- Veeresh Deshpande, Sylvain Barraud, Xavier Jehl, Romain Wacquez, Maud Vinet, Remi Coquand, B. Roche, B. Voisin, François Triozon, C. Vizioz, L. Tosti, Bernard Previtali, P. Perreau, T. Poiroux, Marc Sanquer, Olivier Faynot:
Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities. 121-124 - Tom van Hemert, Raymond J. E. Hueting:
Active strain modulation in field effect devices. 125-128
Thin-Film Transistors
- Min-Kyu Joo, Un Jeong Kim, Dae-Young Jeon, So Jeong Park, Mireille Mouis, Gyu-Tae Kim, Gérard Ghibaudo:
Static and low frequency noise characterization of densely packed CNT-TFTs. 129-132 - Niko Münzenrieder, Christoph Zysset, Thomas Kinkeldei, Luisa Petti, Giovanni A. Salvatore, Gerhard Tröster:
Mechanically flexible double gate a-IGZO TFTs. 133-136 - Suhana M. Sultan, Kai Sun, Maurits R. R. de Planque, Peter Ashburn, Harold M. H. Chong:
Top-down fabricated ZnO nanowire transistors for application in biosensors. 137-140
Novel Thin Film Integration
- Evangelos A. Angelopoulos, Muhammad S. Al-Shahed, Wolfgang Appel, Stefan Endler, Saleh Ferwana, Christine Harendt, Mahadi-Ul Hassan, Horst Rempp, Martin Zimmermann, Joachim N. Burghartz:
Manufacturing aspects of an ultra-thin chip technology. 141-144 - Agata Sakic, Lin Qi, Tom L. M. Scholtes, Johan van der Cingel, Lis K. Nanver:
Epitaxial growth of large-area p+n diodes at 400 ºC by Aluminum-Induced Crystallization. 145-148 - Hokyun An, Kong-Soo Lee, Yoongoo Kang, Seonghoon Jeong, Wonseok Yoo, Jae-Jong Han, Bonghyun Kim, Hanjin Lim, Seokwoo Nam, Gi-Tae Jeong, Ho-Kyu Kang, Chilhee Chung, Byoungdeog Choi:
Current-voltage characteristics of vertical diodes for next generation memories. 149-152
Tunneling Devices
- Lars Knoll, Qing-Tai Zhao, Stefan Trellenkamp, Anna Schäfer, K. K. Bourdelle, Siegfried Mantl:
Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped Nisi2 tunnel junctions. 183-156 - Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Ming-Fu Tsai, Chia-Hao Pao, Pin Su, Ching-Te Chuang:
A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance. 157-160 - Cem Alper, Luca De Michielis, Nilay Dagtekin, Livio Lattanzio, Adrian M. Ionescu:
Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance. 161-164
MEMS / OTFT
- Michal Zaborowski, Daniel Tomaszewski, Piotr Dumania, Piotr Grabiec:
From FinFET to nanowire ISFET. 165-168 - Alfons W. Groenland, Elizaveta Vereshchagina, Alexey Y. Kovalgin, Rob A. M. Wolters, J. G. E. Gardeniers, Jurriaan Schmitz:
Micro- and nano-link ultra-low power heaters for sensors. 169-172 - Stéphanie Jacob, Mohamed Benwadih, Jacqueline Bablet, Isabelle Chartier, Romain Gwoziecki, Sahel Abdinia, Eugenio Cantatore, Lidia Maddiona, Francesca Tramontana, Giorgio Maiellaro, Luigi Mariucci, Giuseppe Palmisano, Romain Coppard:
High performance printed N and P-type OTFTs for complementary circuits on plastic substrate. 173-176
High-frequency Transistors
- Xingui Zhang, Hua Xin Guo, Xiao Gong, Yee-Chia Yeo:
A gate-last In0.53Ga0.47As channel FinFET with Molybdenum source/drain contacts. 177-180 - Andreas Mai, Holger Rücker:
Complementary RF-LDMOS transistors realized with standard CMOS implantations. 181-184 - Susanna Reggiani, Gaetano Barone, Elena Gnani, Antonio Gnudi, Stefano Poli, Ming-Yeh Chuang, Weidong Tian, Rick Wise:
TCAD degradation modeling for LDMOS transistors. 185-188 - Mario Weis, Sébastien Fregonese, Marco Santorelli, Amit Kumar Sahoo, Cristell Maneux, Thomas Zimmer:
Pulsed I(V) - pulsed RF measurement system for microwave device characterization with 80ns/45GHz. 189-192
DRAMs and SRAMs
- Youngseung Cho, Yoosang Hwang, Huijung Kim, Eunok Lee, Soojin Hong, Hyun-Woo Chung, Daeik Kim, Jinyoung Kim, Yong Chul Oh, Hyeongsun Hong, Gyo-Young Jin, Chilhee Chung:
Novel Deep Trench Buried-Body-Contact (DBBC) of 4F2 cell for sub 30nm DRAM technology. 193-196 - Jing Wan, Cyrille Le Royer, Alexander Zaslavsky, Sorin Cristoloveanu:
Z2-FET used as 1-transistor high-speed DRAM. 197-200 - Qi Li, Bo Wang, Tony T. Kim:
A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement. 201-204 - Plamen Asenov, Dave Reid, Scott Roy, Campbell Millar, Asen Asenov:
An advanced statistical compact model strategy for SRAM simulation at reduced VDD. 205-208
Mobility Characterization and Parameter Extraction in Advanced MOSFETs
- Carlos Navarro, Noel Rodriguez, Luca Donetti, Akiko Oliata, Francisco Gámiz, François Andrieu, Olivier Faynot, Claire Fenouillet-Béranger, Sorin Cristoloveanu:
Multibranch mobility characterization: Evidence of carrier mobility enhancement by back-gate biasing in FD-SOI MOSFET. 209-212 - Philippe Gaubert, Akinobu Teramoto, Shigetoshi Sugawa, Tadahiro Ohmi:
The role of the temperature on the scattering mechanisms limiting the electron mobility in metal-oxide-semiconductor field-effect-transistors fabricated on (110) silicon-oriented wafers. 213-216 - Imed Ben Akkez, Antoine Cros, Claire Fenouillet-Béranger, Frédéric Boeuf, Quentin Rafhay, Francis Balestra, Gérard Ghibaudo:
New parameter extraction method based on split C-V for FDSOI MOSFETs. 217-220 - Christoph Kerner, Ivan Ciofi, Thomas Chiarella, Stefaan Van Huylenbroeck:
Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques. 221-225
Advanced Photodetectors
- Robert K. Henderson, Eric A. G. Webster, Richard Walker:
A gate Modulated avalanche bipolar transistor in 130nm CMOS technology. 226-229 - Danilo Bronzi, Federica A. Villa, Simone Bellisai, Bojan Markovic, Simone Tisa, Alberto Tosi, Franco Zappa, Sascha Weyers, Daniel Durini, Werner Brockherde, Uwe Paschen:
Low-noise and large-area CMOS SPADs with timing response free from slow tails. 230-233 - Wei-Cheng Lien, Albert P. Pisano, Dung-Sheng Tsai, Jr-Hau He, Debbie G. Senesky:
Extreme temperature 4H-SiC metal-semiconductor-metal ultraviolet photodetectors. 234-237 - Eric A. G. Webster, Richard J. Walker, Robert K. Henderson, Lindsay Grant:
A silicon photomultiplier with >30% detection efficiency from 450-750nm and 11.6μm pitch NMOS-only pixel with 21.6% fill factor in 130nm CMOS. 238-241
Analog/Low Power Devices
- Romain Ritzenthaler, Tom Schram, Erik Bury, Jérôme Mitard, L.-Å. Ragnarsson, Guido Groeseneken, N. Horiguchi, Aaron Thean, Alessio Spessot, Christian Caillat, V. Srividya, Pierre Fazan:
Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. 242-245 - Valeria Kilchytska, Denis Flandre, François Andrieu:
On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime. 246-249
Emerging Devices
- Sam Vaziri, Anderson D. Smith, Christoph Henkel, Mikael Östling, Max Christian Lemme, Grzegorz Lupina, Gunther Lippert, Jarek Dabrowski, Wolfgang Mehr:
An integration approach for graphene double-gate transistors. 250-253 - Hiwa Mahmoudi, Viktor Sverdlov, Siegfried Selberherr:
MTJ-based implication logic gates and circuit architecture for large-scale spintronic stateful logic systems. 254-257 - Emanuele Verrelli, Dimitris Tsoukalas, Pascal Normand, Nikos Boukos, A. H. Kean:
Resistive switching memory using titanium-oxide nanoparticle films. 258-261
Characterization of Aging and Failure Mechanisms
- Pulkit Jain, John Keane, Chris H. Kim:
An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs. 262-265 - Nuria Ayala, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Xavier Aymerich:
Unified characterization of RTN and BTI for circuit performance and variability simulation. 266-269 - Laurent Brunel, Nathalie Malbert, Arnaud Curutchet, Nathalie Labat, Benoit Lambert:
Kink effect characterization in AlGaN/GaN HEMTs by DC and drain current transient measurements. 270-273
Resistive Memories
- Francesco Maria Puglisi, Paolo Pavan, Andrea Padovani, Luca Larcher, Gennadi Bersuker:
Random Telegraph Signal noise properties of HfOx RRAM in high resistive state. 274-277 - Elisa Vianello, Carlo Cagli, Gabriel Molas, Emeline Souchier, Philippe Blaise, Catherine Carabasse, G. Rodriguez, V. Jousseaume, Barbara De Salvo, Florian Longnos, Faiz Dahmani, P. Verrier, D. Bretegnier, J. Liebault:
On the impact of Ag doping on performance and reliability of GeS2-based Conductive Bridge Memories. 278-281 - Leqi Zhang, Stefan Cosemans, Dirk J. Wouters, Guido Groeseneken, Malgorzata Jurczak:
Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write. 282-285 - Quentin Hubert, Carine Jahan, Alain Toffoli, Gabriele Navarro, S. Chandrashekar, Pierre Noe, Veronique Sousa, Luca Perniola, J.-F. Nodin, A. Persico, S. Maitrejean, A. Roule, E. Henaff, M. Tessaire, P. Zuliani, Roberto Annunziata, Gilles Reimbold, G. Pananakakis, Barbara De Salvo:
Carbon-doped Ge2Sb2Te5 phase-change memory devices featuring reduced RESET current and power consumption. 286-289
Quantum Transport
- Yann-Michel Niquet, Christophe Delerue, Viet Hung Nguyen, Christophe Krzeminski, François Triozon:
Transport properties of strained silicon nanowires. 290-293 - Lida Ansari, Giorgos Fagas, James C. Greer:
Tin nanowire field effect transistor. 294-297 - Mirko Poljak, Emil B. Song, Minsheng Wang, Tomislav Suligoj, Kang L. Wang:
Effects of disorder on transport properties of extremely scaled graphene nanoribbons. 298-301
GaN-based Power Switches
- Dirk Wellekens, Rafael Venegas, Xuanwu Kang, Mohammed Zahid, Tian-Li Wu, Denis Marcon, Puneet Srivastava, Marleen Van Hove, Stefaan Decoutere:
High temperature behaviour of GaN-on-Si high power MISHEMT devices. 302-305 - Abel Fontserè, Amador Pérez-Tomás, Philippe Godignon, José Millán, J. M. Parsey, Peter Moens:
High voltage low Ron in-situ SiN/Al0.35GaN0.65/GaN-on-Si power HEMTs operation up to 300°C. 306-309 - Sameh G. Khalil, Rongming Chu, Ray Li, Danny Wong, Scott Newell, Xu Chen, M. Chen, D. Zehnder, S. Kim, A. Corrion, Brian Hughes, Karim Boutros, C. Namuduri:
Critical gate module process enabling the implementation of a 50A/600V AlGaN/GaN MOS-HEMT. 310-313 - Daniel Piedra, Hyung-Seok Lee, Tomás Palacios, Xiang Gao, Shiping Guo:
Scaling of InAlN/GaN power transistors. 314-317
Semi-classical Transport
- Christoph Jungemann, Sung-Min Hong, Bernd Meinerzhagen, Anh-Tuan Pham:
Deterministic simulation of 3D and quasi-2D electron and hole systems in SiGe devices. 318-321 - Daniel Lizzit, Pierpaolo Palestri, David Esseni, Francesco Conzatti, Luca Selmi:
A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs. 322-325 - Pedram Razavi, Giorgos Fagas, Isabelle Ferain, Ran Yu, Samaresh Das:
Electron transport in germanium junctionless nanowire transistors. 326-329
Low Frequency Noise in Next Generation FET Devices
- Tommaso Romeo, Luigi Pantisano, Eddy Simoen, Raymond Krom, Mitsuhiro Togo, N. Horiguchi, Jérôme Mitard, Aaron Thean, Guido Groeseneken, Cor Claeys, Felice Crupi:
Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs. 330-333 - Christoforos G. Theodorou, Eleftherios G. Ioannidis, Sébastien Haendler, Nicolas Planes, Franck Arnaud, Jalal Jomaah, Charalambos A. Dimitriadis, Gérard Ghibaudo:
Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs. 334-337 - Eddy Simoen, Marc Aoulaiche, Anabela Veloso, M. Jurczak, Cor Claeys, L. Mendes Almeida, Maria Glória Caño de Andrade, A. Luque Rodriguez, J. A. Jimenez Tejada, Christian Caillat, Pierre Fazan:
On the correlation between the retention time of FBRAM and the low-frequency noise of UTBOX SOI nMOSFETs. 338-341 - Kenji Ohmori, Ranga Hettiarachchi, Keisaku Yamada:
Effect of substrate bias on frequency dependence of MOSFET noise intensity. 342-345
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