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ORCIDiNIS 2017: Bhopal, India
- IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017. IEEE 2017, ISBN 978-1-5386-1356-6
- Mannem Naga Sasikanth, Sashank Gambhira, Mrigank Sharad:
Design Optimization of DSP for Wearable Biomedical Device. 1-5 - Rahul Kurzekar, Hardik Arora, Rahul Shrestha:
Embedded Hardware Prototype for Gas Detection and Monitoring System in Android Mobile Platform. 6-10 - Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha:
Reliability and Threat Analysis of NBTI Stress on DSP Cores. 11-14 - Pallabi Sarkar
, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar:
A Firefly Algorithm Driven Approach for High Level Synthesis. 15-19 - Anirban Sengupta, Dipanjan Roy:
Mathematical Validation of HWT Based Lossless Image Compression. 20-22 - Subhendu Kumar Sahoo, Pramod Kumar Meher:
Lookup Table-Based Low-Power Implementation of Multi-channel Filters for Software Defined Radio. 23-27 - Dharmendra Kumar, Chintoo Kumar, Shipra Gautam, Debasis Mitra:
Design of Practical Parity Generator and Parity Checker Circuits in QCA. 28-33 - Rathin K. Joshi, Rutu Parekh, Yash Agrawal:
Design and Optimization of Single Electron Transistor Based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation. 34-39 - Pratima Chatterjee, Prasun Ghosal:
Realizing All Logic Operations Using mRNA-Ribosome System as a Post Si Alternative. 40-45 - Subhendu Kumar Sahoo, Gangishetty Akhilesh, Rasmita Sahoo:
Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET. 46-49 - Shrestha Bansal, Hemanta Kumar Mondal, Sri Harsha Gade, Sujay Deb:
Energy Efficient NoC Router for High Throughput Applications in Many-Core GPUs. 50-55 - Grandhi Sai Anirudh, Soumya J.:
Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes. 56-60 - Saranyu Chattopadhyay, Kaustav Brahma, Arkaprova Ray, Mrigank Sharad:
STT-MRAM for Low Power Access for Read-Intensive Parallel Deep-Learning Architectures. 61-65 - Vipul Kumar Mishra, Anirban Sengupta:
Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis. 66-68 - Vipul Kumar Mishra:
Cost Aware Majority Logic Synthesis for Emerging Technologies. 69-73 - Saurabh Chaturvedi, Mladen Bozanic, Saurabh Sinha:
Implementation of a 6 GHz MEMS Switch. 74-77 - Soudip Sinha Roy:
Towards the Approximation of Cell Wise Switching Time in Quantum-Dot Cellular Automata. 78-83 - Soudip Sinha Roy:
Fault Tolerance and Temperature Stability: The Dynamic Error Estimation in Quantum-Dot Cellular Automata. 84-89 - Aditya Japa, T. Nagateja, Ramesh Vaddi:
Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms. 90-92 - Nawaz Shafi, Chitrakant Sahu, C. Periasamy, Jawar Singh:
SiGe Source Charge Plasma TFET for Biosensing Applications. 93-98 - Nagendra Babu Gunti, Karthikeyan Lingasubramanian:
Neutralization of the Effect of Hardware Trojan in SCADA System Using Selectively Placed TMR. 99-104 - Nagendra Babu Gunti, Karthikeyan Lingasubramanian:
Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy Scheme. 105-110 - Gurveen Vaseer, Garima Ghai, Pushpinder Singh Patheja:
A Novel Intrusion Detection Algorithm: An AODV Routing Protocol Case Study. 111-116 - S. Dinesh Kumar, Himanshu Thapliyal:
Security Evaluation of MTJ/CMOS Circuits Against Power Analysis Attacks. 117-122 - Himanshu Thapliyal, T. S. S. Varun, Edgard Muñoz-Coreas, Keith A. Britt, Travis S. Humble:
Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth. 123-128 - Anoop D, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
High Performance Sense Amplifier Based Flip Flop for Driver Applications. 129-132 - Sarfraz Hussain, Rajesh Kumar, Gaurav Trivedi:
A Novel Low Power High Speed BEC for 2GHz Sampling Rate Flash ADC in 45nm Technology. 133-138 - Sarfraz Hussain, Rajesh Kumar, Gaurav Trivedi:
Comparison and Design of Dynamic Comparator in 180nm SCL Technology for Low Power and High Speed Flash ADC. 139-144 - Samya Muhuri, Debasree Das, Susanta Chakraborty:
An Automated Game Theoretic Approach for Cooperative Road Traffic Management in Disaster. 145-150 - Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra:
Security Enhancements to System on Chip Devices for IoT Perception Layer. 151-156 - Tapan Chowdhury, Arijit Mukherjee, Susanta Chakraborty:
An Efficient MapReduce-Based Adaptive K-Means Clustering for Large Dataset. 157-162 - Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengrajan, Maryam Shojaei Baghini:
Enhanced Look-Up Table Approach for Modeling of Floating Body SOI MOSFET. 163-168 - Pankaj Kumar, Syed Samsuz Zaman, Manash Pratim Sarma, Ashok Ray, Gaurav Trivedi:
Basic CMOS Gate Design by Mixed-Mode Analysis of Step-Channel TMDG-MOSFET. 173-178 - Rekib Uddin Ahmed, Prabir Saha:
Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime. 179-183 - Mohammed Ahmed:
Digital Video Stabilization- Review with a Perspective of Real Time Implementation. 184-189 - Deepak Soni, Dheeraj Sharma, Shivendra Yadav, Mohd. Aslam, Dharmendra Singh Yadav, Neeraj Sharma:
Gate Metal Work Function Engineering for the Improvement of Electrostatic Behaviour of Doped Tunnel Field Effect Transistor. 190-194 - Dharmendra Singh Yadav, Dheeraj Sharma, Sukeshni Tirkey, Deepak Soni, Deepak G. Sharma, Shriya Bajpai, Neeraj Sharma:
A Comparative Study of GaP/SiGe Hetero Junction Double Gate Tunnel Field Effect Transistor. 195-199 - Syed Samsuz Zaman, Pankaj Kumar, Manash Pratim Sarma, Ashok Ray, Gaurav Trivedi:
Design and Simulation of SF-FinFET and SD-FinFET and Their Performance in Analog, RF and Digital Applications. 200-205 - Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya:
A Design Methodology for MOS Current Mode Logic VCO. 206-209 - Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya:
A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. 210-214 - Rajani Suthar, Kirti S. Pande, N. S. Murty:
Leakage Reduction in DT8T SRAM Cell Using Body Biasing Technique. 215-219 - Shivram Mansore, Radheshyam Gamad, D. K. Mishra:
A Single-Ended Read Decoupled 9T SRAM Cell for Low Power Applications. 220-223 - Alak Majumder, Pritam Bhattacharjee:
Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip. 224-228 - Bipasha Nath, Alak Majumder:
Binary Counter Based Gated Clock Tree for Integrated CPU Chip. 229-233 - Amit Singh Rajput, Manisha Pattanaik, Ritesh Kumar Tiwari:
Design and Analysis of Schmitt Trigger Based 10T SRAM in 32 nm Technology. 234-237 - Ashish Sharma, Yogendra Gupta, Sonal Yadav, Lava Bhargava, Manoj Singh Gaur, Vijay Laxmi:
A Power, Thermal and Reliability-Aware Network-on-Chip. 243-245 - Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra:
Microprocessor Based Physical Unclonable Function. 246-251 - Sauvagya Ranjan Sahoo, Sudeendra Kumar K, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra:
On-chip RO-Sensor for Recycled IC Detection. 252-256 - Tuhin Subhra Das, Prasun Ghosal:
MSM: Performance Enhancing Area and Congestion Aware Network-on-Chip Architecture. 257-262 - Manoj R, Adrian Fernandez:
Rapid Prototyping IoT End Applications Using Software Development Kits and Add on Plugins. 263-267
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last updated on 2025-01-03 23:16 CET by the dblp team
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