default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIET Computers & Digital Techniques, Volume 8
Volume 8, Number 1, January 2014
- Irith Pomeranz:
Reducing the input test data volume under transparent scan. 1-10 - Ghassem Jaberipur, HamidReza Ahmadifar
:
A ROM-less reverse RNS converter for moduli set {2q±1, 2q±3}. 11-22 - Mandeep Chaudhary, Peter Lee:
Two-stage logarithmic converter with reduced memory requirements. 23-29 - Marzieh Lenjani, Mahmoud Reza Hashemi:
Tree-based scheme for reducing shared cache miss rate leveraging regional, statistical and temporal similarities. 30-48 - Sukanta Bhattacharjee, Ansuman Banerjee, Bhargab B. Bhattacharya:
Sample preparation with multiple dilutions on digital microfluidic biochips. 49-58
Volume 8, Number 2, March 2014
- Chen Xin, Wu Ning, Bai Na, Huang Hui, Hu Wei:
Built-in self test design of power switch with clock-gated charge/discharge transistor. 59-69 - Georgios Athanasiou, Harris E. Michail, George Theodoridis, Costas E. Goutis:
Optimising the SHA-512 cryptographic hash function on FPGAs. 70-82 - L. Valenti, Marcello Dalpasso, Michele Favalli:
Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits. 83-89 - Irith Pomeranz:
Multi-cycle broadside tests with runs of constant primary input vectors. 90-96 - Basel Halak:
Partial coding algorithm for area and energy efficient crosstalk avoidance codes implementation. 97-107
Volume 8, Number 3, May 2014
- Suboh A. Suboh, Vikram K. Narayana, Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazawi:
Methodology for adapting on-chip interconnect architectures. 109-117 - Mostafa Farahani, Amirali Baniasadi:
Column selection solutions for L1 data caches implemented using eight-transistor cells. 118-128 - Hafiz Md. Hasan Babu, Nazir Saleheen, Lafifa Jamal, Sheikh Muhammad Sarwar, Tsutomu Sasao:
Approach to design a compact reversible low power binary comparator. 129-139 - Xiaoxuan She, Ningxi Li:
Single event transient tolerant frequency divider. 140-147 - Arash Beldachi, Simon J. Hollis, José L. Núñez-Yáñez:
eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip. 148-162
Volume 8, Number 4, July 2014
- Sudip Roy, Bhargab B. Bhattacharya, Sarmishtha Ghoshal, Krishnendu Chakrabarty:
High-throughput dilution engine for sample preparation on digital microfluidic biochips. 163-171 - Gerhard W. Dueck:
Challenges and advances in Toffoli network optimisation. 172-177 - Arash Beldachi, José L. Núñez-Yáñez:
Run-time power and performance scaling in 28 nm FPGAs. 178-186 - Alexandru Amaricai, Oana Boncalo, Constantina-Elena Gavriliu:
Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays. 187-197
Volume 8, Number 5, September 2014
- Po-Juei Chen, Chieh-Chih Che, J. C.-M. Li, Shuo-Fen Kuo, Pei-Ying Hsueh, Chun-Yi Kuo, Jih-Nung Lee:
Physical-aware systematic multiple defect diagnosis. 199-209 - Cheoljon Jang, Jaehwan Kim, Jong-Wha Chong:
Power-aware floorplanning-based power throughsilicon- via technology and bump minimisation for three-dimensional power delivery network. 210-218 - Ioan Ungurean, Vasile Gheorghita Gaitan, Nicoleta-Cristina Gaitan:
Intensive computing on a large data volume with a short-vector single instruction multiple data processor. 219-228 - Changhe Song, Yunsong Li, Jie Guo, Jie Lei:
Block-based two-dimensional wavelet transform running on graphics processing unit. 229-236
Volume 8, Number 6, November 2014
- Ilia Polian, Mohammad Tehranipoor:
Guest Editorial. 237-238 - Eberhard Böhl:
Simple true random number generator for any semi-conductor technology. 239-245 - Cédric Marchand, Julien Francq:
Low-level implementation and side-channel detection of stealthy hardware trojans on field programmable gate arrays. 246-255 - Giovanni Agosta, Alessandro Barenghi, Massimo Maggi, Gerardo Pelosi:
Design space extension for secure implementation of block ciphers. 256-263 - Nisha Jacob, Dominik Merli, Johann Heyszl, Georg Sigl:
Hardware Trojans: current challenges and approaches. 264-273 - Brice Colombier, Lilian Bossuet:
Survey of hardware protection of design data for integrated circuits and intellectual properties. 274-287 - Fareena Saqib, Matthew Areno, Jim Aarestad, James F. Plusquellic:
ASIC implementation of a hardware-embedded physical unclonable function. 288-299 - Alessandro Cilardo, Mario Barbareschi, Antonino Mazzeo:
Secure distribution infrastructure for hardware digital contents. 300-310
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-05 20:49 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
