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ORCIDJames F. Plusquellic
Jim Plusquellic
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- affiliation: University of New Mexico, Albuquerque, USA
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2020 – today
- 2025
[j44]Priya A. Bhakta
, Jim Plusquellic, Andrew Suchanek, Tom J. Mannos:
Fail-Safe Logic Design Strategies Within Modern FPGA Architectures. IEEE Access 13: 3434-3452 (2025)- 2024
- [j43]Idris Somoye, Jim Plusquellic, Tom J. Mannos, Brian Dziki:
An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor. Cryptogr. 8(2): 16 (2024) - [j42]Jenilee Jao, Ian Wilcox, Jim Plusquellic, Biliana S. Paskaleva, Pavel B. Bochev:
Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions. Cryptogr. 8(3): 32 (2024) - [j41]Benjamin Bean, Cyrus Minwalla, Eirini-Eleni Tsiropoulou, Jim Plusquellic:
PUF-based Digital Money with Propagation-of-Provenance and Offline Transfers between Two Parties. ACM J. Emerg. Technol. Comput. Syst. 20(3): 9:1-9:26 (2024) - [j40]Idris Somoye, Tom J. Mannos, Brian Dziki, Jim Plusquellic:
Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1677-1690 (2024) - [i3]Jenilee Jao, Kristi Hoffman, Cheryl Reid, Ryan Thomson, Michael Thompson, Jim Plusquellic:
Statistical Quality Comparison of the Bitstrings Generated by a Physical Unclonable Function across Xilinx, Altera and Microsemi Devices. CoRR abs/2408.06463 (2024) - [i2]Jim Plusquellic, Jennifer Howard, Ross MacKinnon, Kristianna Hoffman, Eirini-Eleni Tsiropoulou, Calvin Chan:
A Physical Layer Analysis of Entropy in Delay-Based PUFs Implemented on FPGAs. CoRR abs/2409.00825 (2024) - 2023
- [j39]Jenilee Jao, Ian Wilcox, Sriram Thotakura, Calvin Chan, Jim Plusquellic, Biliana S. Paskaleva, Pavel B. Bochev:
An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions. J. Hardw. Syst. Secur. 7(4): 110-123 (2023) - [j38]Jenilee Jao, Ian Wilcox, Sriram Thotakura, Calvin Chan, Jim Plusquellic, Biliana S. Paskaleva, Pavel B. Bochev:
Correction to: An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions. J. Hardw. Syst. Secur. 7(4): 124 (2023) - [j37]Jim Plusquellic, Eirini-Eleni Tsiropoulou, Cyrus Minwalla:
Privacy-Preserving Authentication Protocols for IoT Devices Using the SiRF PUF. IEEE Trans. Emerg. Top. Comput. 11(4): 918-933 (2023) - [c71]Md. Sadman Siraj, Aisha B. Rahman, Eirini-Eleni Tsiropoulou, Symeon Papavassiliou, Jim Plusquellic:
Symbiotic Positioning, Navigation, and Timing. DCOSS-IoT 2023: 261-268 - [c70]Md. Sadman Siraj, Eirini-Eleni Tsiropoulou, Symeon Papavassiliou, Jim Plusquellic:
SAFE: Secure Symbiotic Positioning, Navigation, and Timing. GLOBECOM 2023: 2832-2837 - 2022
- [j36]Donald E. Owen, Jithin Joseph, Jim Plusquellic, Tom J. Mannos, Brian Dziki:
Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor. Cryptogr. 6(3): 38 (2022) - [j35]Jim Plusquellic:
Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA. Cryptogr. 6(4): 59 (2022) - [j34]Saraju P. Mohanty, Jim Plusquellic, Garrett S. Rose, Wei Zhang, Maria K. Michael:
Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things. ACM J. Emerg. Technol. Comput. Syst. 18(1): 1:1-1:3 (2022) - [j33]Georgios Fragkos, Cyrus Minwalla, Eirini-Eleni Tsiropoulou, Jim Plusquellic:
Enhancing Privacy in PUF-Cash through Multiple Trusted Third Parties and Reinforcement Learning. ACM J. Emerg. Technol. Comput. Syst. 18(1): 7:1-7:26 (2022) - [j32]Georgios Fragkos, Cyrus Minwalla, Jim Plusquellic, Eirini-Eleni Tsiropoulou:
Local Trust in Internet of Things Based on Contract Theory. Sensors 22(6): 2393 (2022) - [j31]Jim Plusquellic, Donald E. Owen, Tom J. Mannos, Brian Dziki:
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 438-451 (2022) - [c69]Fisayo Sangoleye, Md Sahabul Hossain, Eirini-Eleni Tsiropoulou, Jim Plusquellic:
Network Economics-based Crowdsourcing in UAV-assisted Smart Cities Environments. DCOSS 2022: 101-108 - [c68]Nafis Irtija, Eirini-Eleni Tsiropoulou, Cyrus Minwalla, Jim Plusquellic:
True Random Number Generation with the Shift-register Reconvergent-Fanout (SiRF) PUF. HOST 2022: 101-104 - [c67]Md Sahabul Hossain, Nafis Irtija, Eirini-Eleni Tsiropoulou, Jim Plusquellic, Symeon Papavassiliou:
Reconfigurable Intelligent Surfaces enabling Positioning, Navigation, and Timing Services. ICC 2022: 4625-4630 - [c66]Md. Sadman Siraj, Aisha B. Rahman, Maria Diamanti, Eirini-Eleni Tsiropoulou, Symeon Papavassiliou, Jim Plusquellic:
Orchestration of Reconfigurable Intelligent Surfaces for Positioning, Navigation, and Timing. MILCOM 2022: 148-153 - [i1]Nafis Irtija, Jim Plusquellic, Eirini-Eleni Tsiropoulou, Joshua Goldberg, Daniel S. Lobser, Daniel Stick:
Design and analysis of digital communication within an SoC-based control system for trapped-ion quantum computing. CoRR abs/2209.15601 (2022) - 2021
- [j30]Georgios Fragkos, Cyrus Minwalla, Jim Plusquellic, Eirini-Eleni Tsiropoulou:
Artificially Intelligent Electronic Money. IEEE Consumer Electron. Mag. 10(4): 81-89 (2021) - [j29]Derek Heeger, Maeve Garigan, Eirini-Eleni Tsiropoulou, Jim Plusquellic:
Secure LoRa Firmware Update with Adaptive Data Rate Techniques. Sensors 21(7): 2384 (2021) - 2020
- [j28]Mitchell T. Martin, Jim Plusquellic:
NotchPUF: Printed Circuit Board PUF Based on Microstrip Notch Filter. Cryptogr. 4(2): 11 (2020) - [j27]Ivan Bow, Nahome Bete, Fareena Saqib, Wenjie Che, Chintan Patel, Ryan W. Robucci, Calvin Chan, Jim Plusquellic:
Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity. Cryptogr. 4(2): 13 (2020) - [c65]Derek Heeger, Maeve Garigan, Eirini-Eleni Tsiropoulou, Jim Plusquellic:
Secure Energy Constrained LoRa Mesh Network. ADHOC-NOW 2020: 228-240 - [c64]Kelly Rael, Georgios Fragkos, Jim Plusquellic, Eirini-Eleni Tsiropoulou:
UAV-enabled Human Internet of Things. DCOSS 2020: 312-319 - [c63]Derek Heeger, Jim Plusquellic:
Analysis of IoT Authentication Over LoRa. DCOSS 2020: 458-465 - [c62]Derek Heeger, Maeve Garigan, Jim Plusquellic:
Adaptive Data Rate Techniques for Energy Constrained Ad Hoc LoRa Networks. GIoTS 2020: 1-6 - [c61]Georgios Fragkos, Cyrus Minwalla, Jim Plusquellic, Eirini-Eleni Tsiropoulou:
Reinforcement Learning Toward Decision-Making for Multiple Trusted-Third-Parties in PUF-Cash. WF-IoT 2020: 1-6
2010 – 2019
- 2019
- [j26]Jeff Calhoun, Cyrus Minwalla, Charles Helmich, Fareena Saqib, Wenjie Che, Jim Plusquellic:
Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash). Cryptogr. 3(3): 18 (2019) - [c60]Domenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic, Mark M. Tehranipoor:
IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future. ITC 2019: 1-4 - [c59]Ali Shuja Siddiqui, Geraldine Shirley, Shreya Bendre, Girija Bhagwat, Jim Plusquellic, Fareena Saqib:
Secure Design Flow of FPGA Based RISC-V Implementation. IVSW 2019: 37-42 - [c58]Ali Shuja Siddiqui, Geraldine Shirley, Sam Reji Joseph, Yutian Gui, Jim Plusquellic, Marten van Dijk, Fareena Saqib:
Multilayer Camouflaged Secure Boot for SoCs. MTV 2019: 56-61 - 2018
- [j25]Don Owen Jr., Derek Heeger, Calvin Chan, Wenjie Che, Fareena Saqib, Matthew Areno, Jim Plusquellic:
An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays. Cryptogr. 2(3): 15 (2018) - [j24]Jim Plusquellic, Matthew Areno:
Correlation-Based Robust Authentication (Cobra) Using Helper Data Only. Cryptogr. 2(3): 21 (2018) - [j23]Wenjie Che, Fareena Saqib, Jim Plusquellic:
Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 733-743 (2018) - [c57]Wenjie Che, Manel Martínez-Ramón, Fareena Saqib, Jim Plusquellic:
Delay model and machine learning exploration of a hardware-embedded delay PUF. HOST 2018: 153-158 - [c56]Goutham Pocklassery, Wenjie Che, Fareena Saqib, Matthew Areno, Jim Plusquellic:
Self-authenticating secure boot for FPGAs. HOST 2018: 221-226 - [c55]Ali Shuja Siddiqui, Yutian Gui, David Lawrence, Stuart Laval, Jim Plusquellic, Madhav D. Manjrekar, Badrul H. Chowdhury, Fareena Saqib:
Hardware Assisted Security Architecture for Smart Grid. IECON 2018: 2890-2895 - 2017
- [j22]Wenjie Che, Mitchell T. Martin, Goutham Pocklassery, Venkata K. Kajuluri, Fareena Saqib, Jim Plusquellic:
A Privacy-Preserving, Mutual PUF-Based Authentication Protocol. Cryptogr. 1(1): 3 (2017) - [j21]Wenjie Che, Venkata K. Kajuluri, Mitchell T. Martin, Fareena Saqib, Jim Plusquellic:
Analysis of Entropy in a Hardware-Embedded Delay PUF. Cryptogr. 1(1): 8 (2017) - [j20]Wenjie Che, Venkata K. Kajuluri, Fareena Saqib, Jim Plusquellic:
Leveraging Distributions in Physical Unclonable Functions. Cryptogr. 1(3): 17 (2017) - [c54]Ali Shuja Siddiqui, Chia-Che Lee, Wenjie Che, Jim Plusquellic, Fareena Saqib:
Secure intra-vehicular communication over CANFD. AsianHOST 2017: 97-102 - [c53]Goutham Pocklassery, Venkata K. Kajuruli, James F. Plusquellic, Fareena Saqib:
Physical unclonable functions and dynamic partial reconfiguration for security in resource-constrained embedded systems. HOST 2017: 116-121 - [c52]Wenjie Che, Jim Plusquellic, Fareena Saqib:
A novel offset method for improving bitstring quality of a Hardware-Embedded delay PUF. HOST 2017: 157 - [c51]Ali Shuja Siddiqui, Yutian Gui, Jim Plusquellic, Fareena Saqib:
Secure communication over CANBus. MWSCAS 2017: 1264-1267 - 2016
- [c50]Fengchao Zhang, Shuo Yang, Jim Plusquellic, Swarup Bhunia:
Current based PUF exploiting random variations in SRAM cells. DATE 2016: 277-280 - [c49]Dylan Ismari, Jim Plusquellic, Charles Lamech, Swarup Bhunia, Fareena Saqib:
On detecting delay anomalies introduced by hardware trojans. ICCAD 2016: 44 - [c48]Ali Shuja Siddiqui, Yutian Gui, Jim Plusquellic, Fareena Saqib:
Poster: Hardware based security enhanced framework for automotives. VNC 2016: 1-2 - 2015
- [j19]Fareena Saqib, Aindrik Dutta, Jim Plusquellic, Philip Ortiz, Marios S. Pattichis:
Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF). IEEE Trans. Computers 64(1): 280-285 (2015) - [j18]Fareena Saqib, Dylan Ismari, Charles Lamech, Jim Plusquellic:
Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 776-780 (2015) - [c47]Charalambos Konstantinou, Michail Maniatakos, Fareena Saqib, Shiyan Hu, Jim Plusquellic, Yier Jin:
Cyber-physical systems: A security perspective. ETS 2015: 1-8 - [c46]Ian Wilcox, Fareena Saqib, James F. Plusquellic:
GDS-II Trojan detection using multiple supply pad VDD and GND IDDQs in ASIC functional units. HOST 2015: 144-150 - [c45]Wenjie Che, Fareena Saqib, Jim Plusquellic:
PUF-Based Authentication. ICCAD 2015: 337-344 - 2014
- [j17]Fareena Saqib, Matthew Areno, Jim Aarestad, James F. Plusquellic:
ASIC implementation of a hardware-embedded physical unclonable function. IET Comput. Digit. Tech. 8(6): 288-299 (2014) - [c44]Dylan Ismari, Jim Plusquellic:
IP-level implementation of a resistance-based physical unclonable function. HOST 2014: 64-69 - [c43]Wenjie Che, Jim Plusquellic, Swarup Bhunia:
A non-volatile memory based physically unclonable function without helper data. ICCAD 2014: 148-153 - 2013
- [j16]Jim Aarestad, Philip Ortiz, Dhruva Acharyya, Jim Plusquellic:
HELP: A Hardware-Embedded Delay PUF. IEEE Des. Test 30(2): 17-25 (2013) - [j15]Swarup Bhunia, Miron Abramovici, Dakshi Agrawal, Paul Bradley, Michael S. Hsiao, Jim Plusquellic, Mohammad Tehranipoor:
Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution. IEEE Des. Test 30(3): 6-17 (2013) - [c42]Raj Chakraborty, Charles Lamech, Dhruva Acharyya, Jim Plusquellic:
A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique. DAC 2013: 59:1-59:10 - [c41]J. Ju, Ray Chakraborty, Charles Lamech, Jim Plusquellic:
Stability analysis of a physical unclonable function based on metal resistance variations. HOST 2013: 143-150 - [c40]Jim Aarestad, Jim Plusquellic, Dhruva Acharyya:
Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF. HOST 2013: 151-158 - [c39]Matthew Areno, James F. Plusquellic:
Secure mobile authentication and device association with enhanced cryptographic engines. PRISMS 2013: 1-8 - 2012
- [j14]Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic:
A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 112-125 (2012) - [c38]Jing Ju, Jim Plusquellic, Raj Chakraborty, Reza M. Rad:
Bit string analysis of Physical Unclonable Functions based on resistance variations in metals and transistors. HOST 2012: 13-20 - [c37]Charles Lamech, Jim Plusquellic:
Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structure. HOST 2012: 75-82 - [c36]Matthew Areno, Jim Plusquellic:
Securing Trusted Execution Environments with PUF Generated Secret Keys. TrustCom 2012: 1188-1193 - 2011
- [j13]Charles Lamech, Reza M. Rad, Mohammad Tehranipoor, Jim Plusquellic:
An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities. IEEE Trans. Inf. Forensics Secur. 6(3-2): 1170-1179 (2011) - [c35]Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal:
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect. DAC 2011: 534-539 - [c34]Charles Lamech, Jim Aarestad, Jim Plusquellic, Reza M. Rad, Kanak Agarwal:
REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations. ICCAD 2011: 170-177 - [c33]Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal:
Measuring within-die spatial variation profile through power supply current measurements. ISQED 2011: 711-715 - 2010
- [j12]Jim Aarestad, Dhruva Acharyya, Reza M. Rad, Jim Plusquellic:
Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad IDDQ s. IEEE Trans. Inf. Forensics Secur. 5(4): 893-904 (2010) - [j11]Reza M. Rad, James F. Plusquellic, Mohammad Tehranipoor:
A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1735-1744 (2010) - [c32]Ryan Helinski, Dhruva Acharyya, Jim Plusquellic:
Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. DAC 2010: 240-243 - [c31]Dhruva Acharyya, Kanak Agarwal, Jim Plusquellic:
Leveraging existing power control circuits and power delivery architecture for variability measurement. ITC 2010: 645-653 - [c30]Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic:
A layout-aware approach for improving localized switching to detect hardware Trojans in integrated circuits. WIFS 2010: 1-6 - [e3]Jim Plusquellic, Ken Mai:
HOST 2010, Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 13-14 June 2010, Anaheim Convention Center, California, USA. IEEE Computer Society 2010, ISBN 978-1-4244-7810-1 [contents]
2000 – 2009
- 2009
- [j10]Reza M. Rad, Jim Plusquellic:
A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients Signals. J. Electron. Test. 25(2-3): 169-185 (2009) - [c29]Ryan Helinski, Dhruva Acharyya, Jim Plusquellic:
A physical unclonable function defined using power distribution system equivalent resistance variations. DAC 2009: 676-681 - [c28]Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic:
New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. HOST 2009: 66-73 - [c27]Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic:
Characterizing within-die variation from multiple supply port IDDQ measurements. ICCAD 2009: 418-424 - [e2]Mohammad Tehranipoor, Jim Plusquellic:
IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2009, San Francisco, CA, USA, July 27, 2009. Proceedings. IEEE Computer Society 2009, ISBN 978-1-4244-4805-0 [contents] - 2008
- [c26]Xiaoxiao Wang, Hassan Salmani, Mohammad Tehranipoor, James F. Plusquellic:
Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis. DFT 2008: 87-95 - [c25]Reza M. Rad, Jim Plusquellic, Mohammad Tehranipoor:
Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals. HOST 2008: 3-7 - [c24]Xiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquellic:
Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions. HOST 2008: 15-19 - [c23]Reza M. Rad, Xiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquellic:
Power supply signal calibration techniques for improving detection resolution to hardware Trojans. ICCAD 2008: 632-639 - [e1]Mohammad Tehranipoor, Jim Plusquellic:
IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2008, Anaheim, CA, USA, June 9, 2008. Proceedings. IEEE Computer Society 2008, ISBN 978-1-4244-2401-6 [contents] - 2007
- [j9]Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic:
Securing Designs against Scan-Based Side-Channel Attacks. IEEE Trans. Dependable Secur. Comput. 4(4): 325-336 (2007) - 2006
- [j8]Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel:
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. IEEE Des. Test Comput. 23(4): 278-293 (2006) - [j7]Abhishek Singh, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel:
Defect Simulation Methodology for iDDT Testing. J. Electron. Test. 22(3): 255-272 (2006) - [c22]Jeremy Lee, Mohammad Tehranipoor, Jim Plusquellic:
A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks. VTS 2006: 94-99 - 2005
- [j6]Chintan Patel, Abhishek Singh, Jim Plusquellic:
Defect Detection Using Quiescent Signal Analysis. J. Electron. Test. 21(5): 463-483 (2005) - [j5]Sanat Kamal Bahl, James F. Plusquellic, Joseph Thomas:
A Comparitive Study of W-cdma Cell Search Designs. J. Circuits Syst. Comput. 14(1): 129-136 (2005) - [c21]Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic:
Securing Scan Design Using Lock and Key Technique. DFT 2005: 51-62 - [c20]Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic:
At-Speed Transition Fault Testing With Low Speed Scan Enable. VTS 2005: 42-47 - [c19]Dhruva Acharyya, Jim Plusquellic:
Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. VTS 2005: 433-438 - 2004
- [c18]Abhishek Singh, Chintan Patel, Jim Plusquellic:
On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing. ITC 2004: 262-270 - [c17]Chintan Patel, Abhishek Singh, Jim Plusquellic:
Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement. ITC 2004: 319-328 - [c16]Abhishek Singh, Chintan Patel, Jim Plusquellic:
Fault Simulation Model for i{DDT} Testing: An Investigation. VTS 2004: 304-312 - 2003
- [j4]Dhananjay S. Phatak, Tom Goff, Jim Plusquellic:
IP-in-IP tunneling to enable the simultaneous use of multiple IP interfaces for network level connection striping. Comput. Networks 43(6): 787-804 (2003) - [j3]Chintan Patel, Ernesto Staroswiecki, Smita Pawar, Dhruva Acharyya, Jim Plusquellic:
Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids. J. Electron. Test. 19(6): 611-623 (2003) - [j2]James F. Plusquellic, Abhishek Singh, Chintan Patel, Anne E. Gattiker:
Power supply transient signal analysis for defect-oriented test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 370-374 (2003) - [c15]Abhishek Singh, Dhananjay S. Phatak, Tom Goff, Mike Riggs, James F. Plusquellic, Chintan Patel:
Comparison of Branching CORDIC Implementations. ASAP 2003: 215-225 - [c14]Sanat Kamal Bahl, Jim Plusquellic:
FPGA implementation of a fast Hadamard transformer for WCDMA. FPGA 2003: 237 - [c13]Abhishek Singh, Jitin Tharian, Jim Plusquellic:
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis. ICCAD 2003: 748-753 - [c12]Dhruva Acharyya, Jim Plusquellic:
Impedance Profile of a Commercial Power Grid and Test System. ITC 2003: 709-718 - 2002
- [c11]Abhishek Singh, Jim Plusquellic, Anne E. Gattiker:
Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models. VTS 2002: 357-366 - 2001
- [j1]Jim Plusquellic:
IC Diagnosis Using Multiple Supply Pad IDDQs. IEEE Des. Test Comput. 18(1): 50-61 (2001) - [c10]Abhishek Singh, Chintan Patel, Shirong Liao, James F. Plusquellic, Anne E. Gattiker:
Detecting delay faults using power supply transient signal analysis. ITC 2001: 395-404 - [c9]Chintan Patel, Fidel Muradali, James F. Plusquellic:
Power supply transient signal integration circuit. ITC 2001: 704-712 - [c8]Chintan Patel, Jim Plusquellic:
A Process and Technology-Tolerant IDDQ Method for IC Diagnosis. VTS 2001: 145-152 - 2000
- [c7]James F. Plusquellic, Amy Germida, Jonathan Hudson, Ernesto Staroswiecki, Chintan Patel:
Predicting device performance from pass/fail transient signal analysis data. ITC 2000: 1070-1079 - [c6]Amy Germida, James F. Plusquellic:
Detection of CMOS Defects under Variable Processing Conditions. VTS 2000: 195-204
1990 – 1999
- 1999
- [c5]James F. Plusquellic, Amy Germida, Zheng Yan:
8-Bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS Defects. DFT 1999: 68-76 - [c4]Amy Germida, Zheng Yan, James F. Plusquellic, Fidel Muradali:
Defect detection using power supply transient signal analysis. ITC 1999: 67-76 - 1998
- [c3]James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan:
Characterization of CMOS Defects using Transient Signal Analysis. DFT 1998: 93-101 - 1997
- [c2]James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan:
Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data. ITC 1997: 40-49 - 1996
- [c1]James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan:
Digital Integrated Circuit Testing using Transient Signal Analysis. ITC 1996: 481-490
Coauthor Index
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last updated on 2025-03-04 21:19 CET by the dblp team
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