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ORCIDHiroyuki Yotsuyanagi
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2020 – today
- 2024
[c54]Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen:
Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs. ITC-Asia 2024: 1-6- 2023
- [c53]Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults. ITC-Asia 2023: 1-6 - 2022
- [c52]Masao Ohmatsu, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume:
Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators. ATS 2022: 49-53 - 2020
- [j13]Shyue-Kung Lu
, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume, Hiroyuki Yotsuyanagi:
Fault-Aware Dependability Enhancement Techniques for Flash Memories. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 634-645 (2020)
2010 – 2019
- 2019
- [c51]Toshiaki Satoh, Hiroyuki Yotsuyanagi, Masaki Hashizume:
On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection. 3DIC 2019: 1-4 - [c50]Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes. 3DIC 2019: 1-5 - [c49]Shuya Kikuchi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC. ITC-Asia 2019: 169-174 - 2018
- [j12]Fara Ashikin, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Zvi Roth:
A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs. IEICE Trans. Inf. Syst. 101-D(8): 2053-2063 (2018) - [c48]Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design. ATS 2018: 7-12 - [c47]Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume:
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification. IOLTS 2018: 43-46 - 2017
- [j11]Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi:
Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2842-2850 (2017) - [c46]Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu:
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs. ATS 2017: 242-247 - [c45]Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume, Hiroyuki Yotsuyanagi:
Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories. ATS 2017: 254-259 - [c44]Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type. DFT 2017: 1-4 - [c43]Yuuya Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi:
On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects. ISCIT 2017: 1-5 - [c42]Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume. ISCIT 2017: 1-5 - 2016
- [j10]Widianto, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu, Zvi Roth:
A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs. IEICE Trans. Inf. Syst. 99-D(11): 2723-2733 (2016) - 2015
- [c41]Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
Electrical interconnect test method of 3D ICs by injected charge volume. 3DIC 2015: TS8.19.1-TS8.19.6 - [c40]Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit. 3DIC 2015: TS8.22.1-TS8.22.5 - [c39]Hiroyuki Yotsuyanagi, Akihiro Fujiwara, Masaki Hashizume:
On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs. 3DIC 2015: TS8.24.1-TS8.24.4 - 2014
- [c38]Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
A built-in supply current test circuit for electrical interconnect tests of 3D ICs. 3DIC 2014: 1-6 - 2013
- [j9]Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Takanobu Nimiya, Masaki Hashizume:
On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan. IEICE Trans. Inf. Syst. 96-D(9): 1986-1993 (2013) - [j8]Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Kozo Kinoshita:
SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2561-2567 (2013) - [c37]Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs. Asian Test Symposium 2013: 13-18 - 2011
- [c36]Tomoaki Konishi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture. 3DIC 2011: 1-6 - [c35]Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume:
A built-in test circuit for open defects at interconnects between dies in 3D ICs. 3DIC 2011: 1-5 - [c34]Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Masaki Hashizume:
A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing. Asian Test Symposium 2011: 539-544 - [c33]Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi, Yukiya Miura:
A supply current testable register string DAC of decoder type. ISCIT 2011: 58-63 - 2010
- [j7]Hiroyuki Yotsuyanagi, Masayuki Yamamoto, Masaki Hashizume:
Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops. IEICE Trans. Inf. Syst. 93-D(1): 10-16 (2010) - [c32]Masashi Ishikawa, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code. Asian Test Symposium 2010: 163-166 - [c31]Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita:
Current-based testable design of level shifters in liquid crystal display drivers. ETS 2010: 262
2000 – 2009
- 2009
- [c30]Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
New Class of Tests for Open Faults with Considering Adjacent Lines. Asian Test Symposium 2009: 301-306 - [c29]Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design 2009: 85-90 - [c28]Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu:
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design 2009: 91-96 - 2007
- [c27]Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. ATS 2007: 39-44 - [c26]Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura:
Current Testable Design of Resistor String DACs. ATS 2007: 399-403 - [c25]Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. DFT 2007: 243-251 - 2006
- [c24]Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura:
A BIC Sensor Capable of Adjusting IDDQ Limit in Tests. ATS 2006: 69-74 - [c23]Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura:
Current Testable Design of Resistor String DACs. DELTA 2006: 197-200 - 2005
- [j6]Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita:
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. J. Electron. Test. 21(6): 613-620 (2005) - [c22]Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Electric field for detecting open leads in CMOS logic circuits by supply current testing. ISCAS (3) 2005: 2995-2998 - 2004
- [j5]Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada:
Test Sequence Generation for Test Time Reduction of IDDQ Testing. IEICE Trans. Inf. Syst. 87-D(3): 537-543 (2004) - [j4]Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits. IEICE Trans. Inf. Syst. 87-D(3): 571-579 (2004) - [j3]Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
A test circuit for pin shorts generating oscillation in CMOS logic circuits. Syst. Comput. Jpn. 35(13): 10-20 (2004) - [c21]Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada:
I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment. Asian Test Symposium 2004: 112-117 - [c20]Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
CMOS Open Fault Detection by Appearance Time of Switching Supply Current. DELTA 2004: 183-188 - [c19]Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Practical Fault Coverage of Supply Current Tests for Bipolar ICs. DELTA 2004: 189-194 - [c18]Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita:
On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. DELTA 2004: 269-274 - [c17]Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits. DELTA 2004: 306-311 - 2003
- [c16]Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita:
Reducing Scan Shifts Using Folding Scan Trees. Asian Test Symposium 2003: 6-11 - [c15]Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita:
A BIST Circuit for IDDQ Tests. Asian Test Symposium 2003: 390-395 - 2002
- [c14]Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada:
Test Time Reduction for I DDQ Testing by Arranging Test Vectors. Asian Test Symposium 2002: 423-428 - [c13]Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada:
Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field. DELTA 2002: 387-391 - [c12]Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits. DELTA 2002: 459-461 - 2001
- [c11]Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada:
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States. Asian Test Symposium 2001: 23- - [c10]Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita:
IDDQ Sensing Technique for High Speed IDDQ Testing. Asian Test Symposium 2001: 111-116 - [c9]Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application. Asian Test Symposium 2001: 117-122 - [c8]Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
CMOS open defect detection by supply current test. DATE 2001: 509 - [c7]Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada:
Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. DFT 2001: 287- - 2000
- [c6]Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda:
High speed IDDQ test and its testability for process variation. Asian Test Symposium 2000: 344-349 - [c5]Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda:
Testability Analysis of IDDQ Testing with Large Threshold Value. DFT 2000: 367-375
1990 – 1999
- 1999
- [c4]Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
Identification of Feedback Bridging Faults with Oscillation. Asian Test Symposium 1999: 25- - 1998
- [c3]Hiroyuki Yotsuyanagi, Kozo Kinoshita:
Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. VTS 1998: 176-183 - 1997
- [j2]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita:
Synthesis of Sequential Circuits by Redundancy Removal and Retiming. J. Electron. Test. 11(1): 81-92 (1997) - 1995
- [j1]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita:
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement. IEICE Trans. Inf. Syst. 78-D(7): 861-867 (1995) - [c2]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita:
Synthesis for Testability by Sequential Redundancy Removal Using Retiming. FTCS 1995: 33-40 - [c1]Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita:
Resynthesis for sequential circuits designed with a specified initial state. VTS 1995: 152-157
Coauthor Index
[c53] [c52] [j13] [c51] [c50] [c49] [j12] [c48] [c47] [j11] [c46] [c45] [c44] [c43] [c42] [j10] [c41] [c40] [c39] [c38] [j9] [j8] [c37] [c36] [c35] [c34] [c33] [j7] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [j6] [c22] [j5] [j4] [j3] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4]
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