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ORCIDMing Ming Wong
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2020 – today
- 2024
[j10]Dongrui Li, Ming Ming Wong, Yi Sheng Chong, Jun Zhou, Mohit Upadhyay, Ananta Narayanan Balaji, Aarthy Mani, Weng-Fai Wong, Li-Shiuan Peh, Anh Tuan Do, Bo Wang:
1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2085-2092 (2024)- 2023
- [c25]Bo Wang, Ming Ming Wong, Dongrui Li, Yi Sheng Chong, Jun Zhou, Weng-Fai Wong, Li-Shiuan Peh, Aarthy Mani, Mohit Upadhyay, Ananta Narayanan Balaji, Anh Tuan Do:
1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing. ISCAS 2023: 1-5 - 2022
- [j9]Liwei Yang, Huaipeng Zhang, Tao Luo
, Chuping Qu, Myat Thu Linn Aung, Yingnan Cui, Jun Zhou, Ming Ming Wong, Junran Pu, Anh Tuan Do, Rick Siow Mong Goh, Weng-Fai Wong:
Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency. Neurocomputing 474: 128-140 (2022) - [j8]Liwei Yang, Huaipeng Zhang, Tao Luo, Chuping Qu, Myat Thu Linn Aung, Yingnan Cui, Jun Zhou, Ming Ming Wong, Junran Pu, Anh Tuan Do, Rick Siow Mong Goh, Weng-Fai Wong:
Corrigendum to "Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency" [Neurocomputing (2022) 128-140]. Neurocomputing 508: 109 (2022) - [c24]Jingjing Lan, Vishnu P. Nambiar, Ming Ming Wong, Fei Li, Yuan Gao, Kevin Tshun Chuan Chai, Anh Tuan Do:
A 1800μm2, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS. ISCAS 2022: 2433-2437 - 2021
- [j7]Junran Pu, Wang Ling Goh, Vishnu P. Nambiar, Ming Ming Wong, Anh Tuan Do:
A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 5081-5094 (2021) - [j6]Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do:
Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3148-3152 (2021) - [c23]Xuyang Huang, Ming Ming Wong, Anh Tuan Do, Wang Ling Goh:
A Backpropagation Extreme Learning Machine Approach to Fast Training Neural Network-Based Side-Channel Attack. AsianHOST 2021: 1-6 - [c22]Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do:
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSCIRC 2021: 95-98 - [c21]Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do:
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. ESSDERC 2021: 95-98 - [c20]Ming Ming Wong, Lu Chen, Anh Tuan Do:
A 25 TOPS/W High Power Efficiency Deterministic and Split Stochastic MAC (SC-MAC) Design. VLSI-SoC 2021: 1-6 - [c19]Ming Ming Wong, Lu Chen, Anh Tuan Do:
An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency Design. VLSI-SoC (Selected Papers) 2021: 245-266 - 2020
- [c18]Vishnu P. Nambiar, Junran Pu, Yun Kwan Lee, Aarthy Mani, Tao Luo, L. Yang, Eng-Kiat Koh, Ming Ming Wong, Fei Li, Wang Ling Goh, Anh Tuan Do:
0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron. A-SSCC 2020: 1-4 - [c17]Aarthy Mani, Fei Li, Ming Ming Wong, Luo Tao, Liwei Yang, Vishnu Paramasivam, Anh Tuan Do:
Ultra-Low Leakage, High Fan-Out Neuro Connection Map with TCAM-Based LUT, Localized Priority Encoder and Decoder-Less SRAM. ISCAS 2020: 1-4 - [c16]Vishnu P. Nambiar, Eng-Kiat Koh, Junran Pu, Aarthy Mani, Ming Ming Wong, Li Fei, Wang Ling Goh, Anh Tuan Do:
Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c15]Fei Li, Ming Ming Wong, Aarthy Mani, Vishnu Paramasivam, Anh-Tuan Do:
0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications. A-SSCC 2019: 141-144 - [c14]Jawad Haj-Yahya, Ming Ming Wong, Vikramkumar Pudi, Shivam Bhasin, Anupam Chattopadhyay:
Lightweight Secure-Boot Architecture for RISC-V System-on-Chip. ISQED 2019: 216-223 - [c13]Ming Ming Wong, Anh-Tuan Do:
Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function. SoCC 2019: 103-108 - [c12]Swagata Mandal, Sreetama Sarkar, Ming Ming Wong, Anupam Chattopadhyay, Amlan Chakrabarti:
Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA. VLSID 2019: 257-262 - 2018
- [j5]Jia Jun Tay, M. L. Dennis Wong, Ming Ming Wong, Cishen Zhang, Ismat Hijazin:
A tree search algorithm for low multiplicative complexity logic design. Future Gener. Comput. Syst. 83: 132-143 (2018) - [c11]Ming Ming Wong, Jawad Haj-Yahya, Anupam Chattopadhyay:
SMARTS: secure memory assurance of RISC-V trusted SoC. HASP@ISCA 2018: 6:1-6:8 - [c10]Ming Ming Wong, Jawad Haj-Yahya, Suman Sau, Anupam Chattopadhyay:
A New High Throughput and Area Efficient SHA-3 Implementation. ISCAS 2018: 1-5 - [c9]Jia Jun Tay, M. L. Dennis Wong, Ming Ming Wong, Cishen Zhang, Ismat Hijazin:
Construction of a Low Multiplicative Complexity GF (24) Inversion Circuit for Compact AES S-Box. TENCON 2018: 540-544 - [c8]Ming Ming Wong, Vikramkumar Pudi, Anupam Chattopadhyay:
Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor. VLSI-SoC 2018: 95-100 - [i1]Swagata Mandal, Sreetama Sarkar, Ming Ming Wong, Anupam Chattopadhyay, Amlan Chakrabarti:
Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA. CoRR abs/1810.09661 (2018) - 2017
- [j4]Ming Ming Wong, Mou Ling Dennis Wong:
Stochastic Computing with Spiking Neural P Systems. J. Univers. Comput. Sci. 23(7): 589-602 (2017) - [c7]Suman Sau, Jawad Haj-Yahya, Ming Ming Wong, Kwok-Yan Lam, Anupam Chattopadhyay:
Survey of secure processors. SAMOS 2017: 253-260 - 2015
- [c6]Ming Ming Wong, Mou Ling Dennis Wong, C. Zhang, Ismat Hijazin:
Compact and short critical path finite field inverter for cryptographic S-box. DSP 2015: 775-779 - 2014
- [c5]Jia Jun Tay, Ming Ming Wong, Ismat Hijazin:
Compact and low power AES block cipher using lightweight key expansion mechanism and optimal number of S-Boxes. ISPACS 2014: 108-114 - [c4]Ming Ming Wong, Mou Ling Dennis Wong:
New lightweight AES S-box using LFSR. ISPACS 2014: 115-120 - 2012
- [j3]Ming Ming Wong, M. L. Dennis Wong, Asoke K. Nandi, Ismat Hijazin:
Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1151-1155 (2012) - [c3]Ming Ming Wong, M. L. Dennis Wong, Asoke K. Nandi, Ismat Hijazin:
AES S-box using Fermat's Little Theorem for the highly constrained embedded devices. EUSIPCO 2012: 1039-1043 - [c2]Ming Ming Wong, Mou Ling Dennis Wong, Ka Lok Man:
Compact Multiplicative Inverter for Hardware Elliptic Curve Cryptosystem. NPC 2012: 492-499 - 2011
- [j2]Ming Ming Wong, M. L. Dennis Wong, Asoke K. Nandi, Ismat Hijazin:
Composite field GF(((22)2)2) advanced encryption standard (AES) S-box with algebraic normal form representation in the subfield inversion. IET Circuits Devices Syst. 5(6): 471-476 (2011) - 2010
- [j1]Ming Ming Wong, M. L. Dennis Wong, Ismat Hijazin:
A throughput maximised parallel architecture for 2D fast Discrete Pascal Transform. Comput. Electr. Eng. 36(3): 585-591 (2010) - [c1]Ming Ming Wong, M. L. Dennis Wong:
A new common subexpression elimination algorithm with application in composite field AES S-box. ISSPA 2010: 452-455
Coauthor Index
aka: Anh Tuan Do
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last updated on 2024-11-11 21:24 CET by the dblp team
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